NASH: Neuro-inspired ArchitectureS in Hardware Project

Design of Neural Network Architecture on Reconfigurable Hardware for Traffic Light Detection in Autonomous Driving Vehicle

On-going Paper


Research Schedule - Please update it always according to your progress

please insert your reseach schedule here. Due date: July 7, 2017


NASH seminars


Background and Motivation

The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network. SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse. Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.

Goal

The goal of this research is to (1) Design a Feed-Forward Neural-Network on FPGA for Traffic Light Recognition, (2) Design space exploration.

NN_on_FPGA.jpg
Overall Implementation Approach
stop-sign-recognition.jpg
Stop sign Recognition

RPS and RPR

References

Others


添付ファイル: fileRPS_20181207.pdf 13件 [詳細] file10_15.pptx [詳細] file10_15.pdf 6件 [詳細] fileACO.key 1件 [詳細] fileIPSJ_ENG.zip 3件 [詳細] fileThesis_Japanes_2.pdf 10件 [詳細] fileThesis_Japanes.pdf 8件 [詳細] fileYuji_Murakami_Dec_18.zip 6件 [詳細] fileRPS_20170426.pdf [詳細] fileRPS_20170607.pdf [詳細] fileRPS_20170705.pdf 1件 [詳細] fileRPS_20170920.pdf 2件 [詳細] fileRPR_20170510.pdf [詳細] fileRPR20170621.pdf 1件 [詳細] fileResearch_Plan_Seminar_07312017 .pptx 5件 [詳細] filestop-sign-recognition.jpg 2件 [詳細] fileOverview.pdf 2件 [詳細] fileOverview.pptx 1件 [詳細] fileBR.pptx 1件 [詳細] fileBR.pdf [詳細] file 2件 [詳細] fileBR.key [詳細] fileAutonomous-Car.jpg 3件 [詳細] fileNN_on_FPGA.jpg 9件 [詳細]

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Last-modified: 2018-12-07 (金) 16:46:29