2018
 The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah, ”Comprehensive Analytic Performance Assessment and Lowlatency Algorithm for Spike Traffic Routing in 3DNoC of Spiking Neurons (3DNOCSNN)”, ACM Journal on. Emerging Technologies in Computing (JETC), July 2018 (under review).
 Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”SAFTPHENIC: a thermalaware microring faultresilient photonic NoC”, The Journal of Supercomputing, June 2018 (in press) [LocalOnly]
 Abderazek Ben Abdallah, ”Neuroinspired Computing Systems & Applications”, Keynote Speech, 2018 International Conference on Intelligent Autonomous Systems (ICoIAS’2018), March 13, 2018, Singapore.[slides.pdf]
 The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuroinspired Architecture in Hardware”, Proc. of the IEEE International Conference on Big Data and Smart Computing (BigComp2018), pp. 326332, January 1518, 2018, Shanghai, China. [paper.pdf], [slides.pdf]
 Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolutional Neural Networks for Farm Monitoring”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018 [slides.pdf]
 Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for TrafficLight Recognition in Autonomous Vehicles”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018. [slides.pdf]
 Kanta Suzuki, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hardware Design of a Leaky Integrate and Fire Neuron Core Towards the Design of a Lowpower Neuroinspired Spikebased Multicore SoC”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018. [slides.pdf]
 Khanh N. Dang, Abderazek Ben Abdallah, ”Architecture and Design Methodology for HighlyReliable TSVNoC Systems”, Invited Book Chapter, Nova Science Publishers, Feb. 2018, ISBN: 97815361332712018. [preprint.pdf]
Theses
 Maiko Tanaka, ”Hardwired Attitude Control System for Quadcopters”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Tomoaki Fukuchi, ”Performance Evaluation of Line Follower Robots for Sensor Locations Optimization Using Reinforcement Learning”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Maiko Arakawa, ”Horizonbased attitude estimation on Programmable SoC”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Kosuke Igarashi, ”Analysis of Execution Time of Visionbased SLAM Software for Realtime Embedded Systems ”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Nanase Yamaguchi, ”Video Classification Using Temporal Transition of Detected Trajectories Frequency ”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Yohei Symmyo, ”2D Mapping Correction for Embedded Systems Using LiDAR with Low Accuracy Actuator ”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Masaki Yamada, ”Performance Study of Character Recognition with FeedForward Neural Network”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Kanta Suzuki, ”Design of a Leaky, Integrate and Fire (LIF) Neuron Core for NASH System”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
 Kosuke Takakuwa, ”Study of a Neuroinspired Architecture in Hardware”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2018.
2017
 Khanh N. Dang, Akram Ben Ahmed, Yuichi Okuyama, and Abderazek Ben Abdallah, ”Scalable Design Methodology and Online Algorithm for TSVcluster Defects Recovery in Highly Reliable 3DNoC Systems”, IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2762407. [preprint.pdf]
 Abderazek Ben Abdallah, Khanh N. Dang, Yuichi Okuyama, ”A Lowoverhead Fault tolerant Technique for TSVbased Interconnects in 3DIC Systems”, The 18th International Conference on Sciences and Techniques of Automatic control and computer engineering (STA’2017), December 2123, 2017. [paper.pdf], [slides.pdf]
 Achraf Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic NetworksonChip Architecture Based on a Novel WavelengthShifting Mechanism”, IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2737016
 Khanh N. Dang, Akram Ben Ahmed, XuanTu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of FaultResilient NetworkonChip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, Nov. 2017. DOI:10.1109/TVLSI.2017.2736004. [preprint.pdf]
 Abderazek Ben Abdallah, ”NeuroInspired Adaptive Manycore SoCs and Applications”, Keynote Speech, International Conference on Control, Automation and Robotics, April 2224, 2017, Nagoya, Japan.
 Book: Abderazek Ben Abdallah (Author), ”Advanced Multicore Systems OnChip: Architecture, OnChip Network, Design”, Publishers: Springer; 1st ed, 2017, ISBN13: 9789811060915, ISBN10: 98110609162017.
 Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Lowoverhead SoftHard Fault Tolerant Architecture, Design, and Management Scheme for Reliable Highperformance Manycore 3DNoC Systems”, Journal of Supercomputing, Volume 73, Issue 6, pp 2705–2729, 2017. doi:10.1007/s1122701619510 [Springer Nature (.pdf)]
 Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Faultresilient Photonic NetworkonChip for Reliable Highperformance Manycore Systems”, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s1122701618460. [Springer Nature (.pdf)]
 Achraf Ben Ahmed, A. Ben Abdallah, Architecture and Design of RealTime Systems for Elderly Health Monitoring, Journal of Embedded Systems, Int. J. of Embedded Systems, 2017 Vol.9, No.5, pp.484 – 494 DOI: 10.1504/IJES.2017.10007717
Theses
 Nam Khanh Dang, ”Development of OnChip Communication FaultResilient Adaptive Architectures and Algorithms for 3DIC Technologies (3次元IC技術のための適応型耐障害チップ内通信アーキテクチャとアルゴリズムの開発)”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, September 2017. [thesis.pdf]
2016
 Abderazek Ben Abdallah, ‘‘Adaptive SoCs for Smart Autonomous Systems”, Keynote Speech, 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 1921, 2016. [slides.pdf], [BibTex]
 Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Reliability Assessment and Quantitative Evaluation of SoftError Resilient 3D NoC System”, Prof. of the 25thIEEE Asian Test Symposium (ATS’16), Hiroshima, November 2124, 2016. [slides.pdf], [BibTex]
 Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Power Estimation Method for Meshbased Photonic NoC Routing Algorithms”, Proc. of the Fourth International Symposium on Computing and Networking, Hiroshima, pp. 452453, November 2225, 2016. [BibTex]
 Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah, ”SoftError Resilient NetworkonChip for SafetyCritical Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Ho Chi Minh, June 27 – 29, 2016. [slides.pdf], [BibTex]
 Akram Ben Ahmed, Abderazek Ben Abdallah, “Adaptive faulttolerant architecture and routing algorithm for reliable manycore 3DNoC systems“, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 3043, ISSN 07437315, doi:10.1016/j.jpdc.2016.03.014. [preprint.pdf], [BibTex]
 Achraf Ben Ahmed, Abderazek Ben Abdallah, ”An Energyefficient Highthroughput Meshbased Phototonic Onchip Interconnect for Manycore Systems”, Photonics, 2016; 3(2):15. doi:10.3390/photonics3020015. [paper.pdf], [BibTex]
Theses
 Michael Meyer, ”Microring Faultresilient Photonic Onchip Network for Reliable Highperformance Manycore SystemsonChip”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017.
 Yusuke Sato, “FPGA Implementation of Heading Reference System Based on Extended Kalman Filter”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Shun Hayamizu, “Automatic Trajectory Selection with Genetic Algorithm for Video Recognition using TimeSpace Continuous Dynamic Programming”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Ryunosuke Murakami, “Implementation and Evaluation of SoftError Resilience for OASIS NetworkonChip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Hiroki Yomogita, “Hardware Implementation and Evaluation of a SoftNode for PacketSwitched NetworkonChip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Shunsuke Mie, “Realtime AHRS circuit from Cbased code for System on a programmable chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Yuji Murakami, “Design of a LightWeight Control Network for HighBandwidth Photonic NetworkonChip Systems”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Nao Miyamoto, “Video Classification with Numbers of Detected Trajectories Using Timespace Continuous Dynamic Programming”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
 Kaori Yatsu, “Visualization of Educational Processor in UML”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
2015
 Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, XuanTu Tran, “SoftError Resilient 3D NetworkonChip Router“, Proc. of IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), pp. 84 – 90, Sep. 2224, 2015. [BibTex]
 Achraf Ben Ahmed, Abderazek Ben Abdallah, “Hybrid SiliconPhotonic NetworkonChip for Future Generations of Highperformance Manycore Systems,” Journal of Supercomputing, Dec. 2015, Vol. 71, Issue 12, pp 44464475. [preprint.pdf]. [BibTex]
 Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Faulttolerant Photonic NetworkonChip,” Proc. of IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 912, 2015, pp. 821 – 826. [BibTex]
 Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”FTTDOR: Microring Faultresilient Optical Router for Reliable NetworkonChip Systems”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC15), pp. 227 – 234, Sep 2325, 2015. [BibTex]
 Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hybrid Photonic NoC based on Nonblocking Photonic Switch and Lightweight Electronic Router”, Proc. of IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), pp. 56 – 61, Oct. 912, 2015. [BibTex]
 Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Contentionfree Routing for Hybrid Photonic Meshbased NetworkonChip Systems”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC15), pp. 235 – 242, Sep 2325, 2015. [BibTex]
 Abderazek Ben Abdallah, Mitsuhiro Nakamura, Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, “Faulttolerant Router for Highlyreliable Manycore 3DNoC Systems”, Proc. of the 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 2931, 2015, Okinawa, Japan. [BibTex]
 Ben Ahmed, Ashraf; Okuyama, Yuichi; Ben Abdallah, Abderazek, “Nonblocking electrooptic networkonchip router for highthroughput and lowpower manycore systems,” in Information Technology and Computer Applications Congress (WCITCA), 2015 World Congress on, vol., no., pp.17, 1113 June 2015 doi: 10.1109/WCITCA.2015.7367068. [BibTex]
 Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah,”Efficient Router Architecture, Design and Performance Exploration for Manycore Hybrid Photonic NetworkonChip (2DPHENIC)”, Proc. of the International Conference on Information Science and Control Engineering, pp. 202 – 206, April 2426, 2015. [BibTex]
Theses
 Achraf Ben Ahmed, ‘‘Highperformance Scalable Photonics Onchip Network for Manycore SystemsonChip”, Ph.D. Thesis, GraduteSchool of Computer Science and Engineering, The University of Aizu, March 2016, [thesis.pdf], [BibTex]
 Mitsuhiro Nakamura, “Implementation of Matrix Processing Array on a Highly Reliable Network on Chip,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
 Sean Ito, “Feature Extraction using kernel PCA for Estimation of Calculation Capability with Portable EEG Devices,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
 Shunsuke Ishikuro, “Arithmetic Resource Optimization for Implementation of a Graphbased Reconfigurable Processor,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
 Kajikawa, Akihito, Evaluation of Error Detection Mechanism for 3DOASISNetworkonChip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
 Saito, Ken, Design, and Analysis of Electrical Control Router for Hybrid Photonics NOC System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
 Okada, Ryoga, Power and Performance Comparison of Electronic 2DNoC and OptoElectronic 2DNoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
 Ishii, Yosuke, Evaluation of Knearest neighbor search algorithms forNonlinerState Space Projection on Portable Devices, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
 Sasamoto, Kazuaki, Video Recognition using Trajectories Parameterized by Trigonometric Functions with TimeSpace Continuous Dynamic Programming, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
2014
 Akram Ben Ahmed, ”Highthroughput Architecture and Routing Algorithms Towards the Design of Reliable Meshbased ManyCore NetworkonChip Systems”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015
 Abderazek Ben Abdallah, ”SiPhotonics Technology Towards femtoJoule/bit Optical Communication in Manycore Chips”, Keynote Speech, 15th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2014), Hammamet, Dec. 2123, 2014
 Akram Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, Adaptive Error and Traffic Aware Router Architecture for 3D NetworkonChip Systems, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC14), pp. 197204, Sept. 2014. [DOI], [slides.pdf]
 Yuichi Okuyama, Shigeyuki Takano, and Tokimasa Shirai, “Design of a Coarsegrained Processing Element for Matrix Multiplication on FPGA,” IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC14), pp.237241, Sept. 2014. [DOI]
 Abderazek Ben Abdallah, OnChip Optical Interconnects: Prospects and Challenges, Keynote Talk, 6th International Conference on Soft Computing and Pattern Recognition, Tunis, August 1114, 2014.
 Akram Ben Ahmed, A. Ben Abdallah, Graceful DeadlockFree FaultTolerant Routing Algorithm for 3D NetworkonChip Architectures, Journal of Parallel and Distributed Computing 74/4 (2014), pp. 22292240 [DOI]
Theses
 Akram Ben Ahmed, ”Highthroughput Architecture and Routing Algorithms Towards the Design of Reliable Meshbased ManyCore NetworkonChip Systems”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [thesis.pdf],,[BibTex]
 Mitsunari Ishii, Architecture, and Design of an Efficient Router for OASIS 3D NetworkonChip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [slides.pdf]
 Yuuki Tanaka, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3DNoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [slides.pdf]. [Technical Report]
2013
 Achraf Ben Ahmed, A. Ben Abdallah, PHENIC: Towards Photonic 3DNetworkonChip Architecture for Highthroughput Manycore SystemsonChip, IEEE Proceedings of the 14th International Conference on Sciences and Techniques of Automatic control and computer engineering (STA’2013), pp.508516, Dec. 2013.
 Toshihiro Sato, Yuichi Okuyama, and Motoki Sakai,”Simulation Study of a P300 Speller for SingleLead Hybrid BCI,” SICE Annual Conference 2013 (SICE2013), Sep.2013 (Young Author’s Award Finalist)
 Akram Ben Ahmed, Ashraf Ben Ahmed, A. Ben Abdallah, DeadlockRecovery Support for Faulttolerant Routing Algorithms in 3DNoC Architectures, IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC13), pp. 6772, 2013. [DOI]
 Akram Ben Ahmed, A. Ben Abdallah, Architecture, and Design of Highthroughput, Lowlatency and FaultTolerant Routing Algorithm for 3DNetworkonChip, The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 15071532. [DOI]
 Achraf Ben Ahmed, A. Ben Abdallah, Hardware/Software Prototyping of Dependable RealTime System for Elderly Health Monitoring, IEEE Proc. of the World Congress on Computer and IT (ICMAES), June 2013. [DOI]
 Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, RunTime Monitoring Mechanism for Efficient Design of Applicationspecific NoC Architectures in Multi/Manycore Era, IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013), July 2013.”’ [DOI]
 A. Ben Abdallah, Keynote Speech: Towards the Development of Smart Multicore BioChip for BodyArea Networks, IEEEPCSJ Conference, November 2, 2013.
 A. Ben Abdallah, Book: Multicore SystemsonChip: Practical Hardware/Software Design, 2nd Edition &ref(): File not found: “Amazonlogo.gif” at page “Publications”;, Publisher: Springer/Atlantis,(2013), ISBN13: 9789491216916.
 A. Ben Abdallah, PHENIC: Silicon Photonic 3DNetworkonChip Architecture for Highperformance Heterogeneous Manycore SystemonChip, Technical Report, Ref. PTR0901A07152013, September 1, 2013.
2012
 Ben Ahmed Akram, A. Ben Abdallah, On the Design of a 3D NetworkonChip for Manycore SoC, Technical Report, The University of Aizu, Feb. 2012.
 Akram Ben Ahmed, A. Ben Abdallah, Lowoverhead Routing Algorithm for 3D NetworkonChip, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 2332, 2012. [DOI]
 Akram Ben Ahmed, A. Ben Abdallah, LAXYZ: Low Latency, High Throughput LookAhead Routing Algorithm for 3D NetworkonChip (3DNoC) Architecture, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC12), pp. 167174, 2012. [DOI]
 Junko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, and Kenichi Kuroda, “Hardware Implementation of Accumulated Value Calculation for TwoDimensional Continuous Dynamic Programing,” IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC 2012), DOI 10.1109 /MCSoC.2012.10, Sep. 2012.
 Achraf Ben Ahmed, Yumiko Kimezawa, A. Ben Abdallah, Towards Smart Health Monitoring System for Elderly People, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 248253, 2012. [DOI]
 Akram Ben Ahmed, A. Ben Abdallah, ONoCSPL Customized NetworkonChip (NoC) Architecture and Prototyping for Dataintensive Computation Applications, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257262, 2012. DOI
 M. Sakai, Y. Okuyama, T. Sato, D. Wei, “Nonlinear StateSpace Projection Based Method to Acquire EEG and ECG Components Using a Single Electrode”, International Journal of Life Science and Medical Research, Vol. 2, Iss. 4, pp. 96100, 2012.
 Sakai M, Okuyama Y, Wei D., “Separation of EEG and ECG components based on wavelet shrinkage and variable cosine window,” J Med Eng Technol. 2012 Feb;36(2):13543, Feb. 2012.
 Kenichi Mori, OASIS NetworkonChip Prototyping on FPGA, Technical Report, Adaptive Systems Lab, The University of Aizu, Feb., 2012. PDF
 R. Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NOC, Technical Report, Adaptive Systems Lab, The University of Aizu, Feb., 2012. PDF
Theses
 Y. Kimezawa, ”Towards the Design of Dependable RealTime System for Remote Health Monitoring of Elderly People, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013. [slides.pdf], [BibTex]
 Achraf Ben Ahmed, Interactive Realtime Interface for Smart Remote Health Monitoring and Analysis, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
 Takayuki Ochi, ”A Quantitative Performance Study of Shared Memory Multicore Systems”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
 Shuu Endou, Hardware Prototyping and Evaluation of Distributed Routing Core NetworkInterface for OASIS NoC Architecture, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
 小林 一樹, Yuichi Okuyama,”A Design ofHigh Performance Transfer API for Portable PCI Express Interface on an FPGA,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
 長谷川 徹, Yuichi Okuyama,”Development of an EEGbased Biofeedback System using BCI2000″, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
2011
 A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, Natural Instruction Level Parallelismaware Compiler for HighPerformance QueueCore Processor Architecture, ”’Journal of Supercomputing, Vol. 57, No. 3, pp. 314338, Sept. 2011.[DOI]
Theses
 Kenichi Mori, OASIS NetworkonChip Prototyping on FPGA, ”’Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Ref. 19KMMT11. [slides]. Supervisor: Prof. A. Ben Abdallah.
 Ben Ahmed Akram, On the Design of a 3D NetworkonChip for Manycore SoC, Master’s Thesis, The University of Aizu, Feb. 2012. [Thesis], [slides] Supervisor: Prof. A. Ben Abdallah.
 Shohei Miura, ”Design of Parametrizable NetworkonChip”, ”’Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, 17SMMT11.
 田沢 純子, Yuichi Okuyama,”Hardware Implementation of Accumulated Value Calculation for TwoDimensional Continuous Dynamic Programming,” Master’s Thesis, The University of Aizu, Feb. 2012.
 五十嵐 翔一, Yuichi Okuyama,”A Design Framework for HighlyPortable PCIExpress Interface FPGA Boards,” Master’s Thesis, The University of Aizu, Feb. 2012.
 森田 竜平, Yuichi Okuyama,”A Retargetable PROGRAPE System with a PCIExpress Framework,” Master’s Thesis, The University of Aizu, Feb. 2012.
 吉田 幸祐, Yuichi Okuyama,”An acceleration method of 2D Continuous Dynamic Programming with Multicore processor and GPGPUs”, Master’s Thesis, The University of Aizu, Feb. 2012.
 Ryuya Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NOC, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012.
 Tomotaka Kasahara, ”Performance and Complexity Study of MultiQueueCore Systems”, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Ref. 15TKGT11.
 加治 良亮, Yuichi Okuyama,”Acceleration of accumulated value calculation for 2D Continuous Dynamic Programming with GPGPU”, Graduation Thesis, The University of Aizu, Feb.2012.
 佐藤 俊裕, Yuichi Okuyama,”Evaluation of Error Bound and Processing Time in Approximated Nearest Neighbor Searching for Nonlinear Projective Algorithm,” Graduation Thesis, The University of Aizu, Feb. 2012.
2010
 A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, Architecture and Design of Efficient 3D NetworkonChip (3D NoC) for Custom Multicore SoCs, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA2010), Nov. 2010. [DOI] (Best Paper Award).
 K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS NetworkonChip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA2010), Nov. 2010, pp. 7479.
 Yukihiro Yoshida, Koushi Yamaguchi, Yuichi Yaguchi, Yuichi Okuyama, Kenichi Kuroda and Ryuichi Oka, “Acceleration of TwoDimensional Continuous Dynamic Programming by Memory Reduction and Parallel Processing, IADIS International Conference Applied Computing 2010, pp6168, Timisoara, Romania, Oct. 2010.
 A. Ben Abdallah, Efficient Parallel ECG Processing Algorithm and Design of Flexible Health Monitoring System for Elderly People, Innovation Research Journal, March 2010, pp. 2427.
 A. Ben Abdallah, Y. Haga, K. Kuroda, ”An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multilead Electrocardiogram Records”, ”’IEEE Proc. of the 39th he International Conference on Parallel Processing Workshop, San Diego, pp.99103, Sept. 1316, 2010.”’
 ”Multicore SystemsOnChip: Practical Hardware/Software Design”, ”’ISBN 9789078677222, Author: A. Ben Abdallah, Publishers: World Scientific, 2010,”’
 Dorothy Maduagwu, Performance Evaluation of Queue Processor Vs. RISC Architecture, MS Thesis, AUST University, 2010.
 Aminu Mahdi, Effective Dynamic Remapping Algorithm for low power Networkon Chip (NoC), MS Thesis, AUST University, 2010.
 Dwumfour Abdullai, Designing a Runtime Simulator for QueueCore Processor, MS Thesis, AUST University, 2010.
 Aliu Sunday Jhon, AFRIHEALTH Care Monitoring System Using Multicore System on Chip Electrocardiography, MS Theis, AUST University, 2010.
 Arquimedes Canedo, Ben Abdallah Abderazek, and Masahiro Sowa. 2010. Compiling for Reduced BitWidth Queue Processors. J. Signal Process. Syst. 59, 1 (April 2010), 4555. DOI=http://dx.doi.org/10.1007/s1126500802863
Theses
 Hiroki Hoshino, Development of Parallel Queue Processor Architecture and its Integrated Development Environment, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
 Taichi Maekawa, Design, and Evaluation of Dual Mode Processor Architecture, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
 Masashi Masuda, ”Produced Order Queue Compiler Design”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
 Takahiro Uesaka, ”OASIS NoC Topology Optimization with ShortPath Link”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011, Ref. 11TUGT10.
 Shunichi Kato, Shared Memory MultiQueueCore Processor Design>, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011, Ref. 10SKGT10.
 Yumiko Kimezawa, ”Multicore SoC Architecture for Realtime Data Intensive ECG Processing”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.”’9UKGT10 . Supervisor: Prof. A. Ben Abdallah.
 仁木 翔太, Yuichi Okuyama, “GPGPU Acceleration of Smoothed Particle Hydrodynamics Simulation, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
 前田 和広, Yuichi Okuyama, “Precision Improvement in SPH Simulation Using a Computational Grid, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
2009
 Fumiko OHORI, Yuichi OKUYAMA, Junji KITAMICHI, Kenichi KURODA, and Tsuyoshi HAMADA, “Evaluation of an Image Filtering Algorithm using the Particle Interaction Accelerator on FPGA,” The 24th International Technical Conference on Circuits / Systems, Computers and Communications (ITCCSCC 2009 ), July 2009.
 Y. Haga, A. Ben Abdallah, and K. Kuroda, ”Embedded MCSoC Architecture and PeriodPeak Detection (PPD) Algorithm for ECG/EKG Processing”, ”’The 19th Intelligent System Symposium (FAN 2009), pp.298303, Sep. 2009.”’
 S. Miura, A. Ben Abdallah, and K. Kuroda, ”PNoC – Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration”, ”’The 19th Intelligent System Symposium (FAN 2009), pp.314317, Sep. 2009.”’
 K. Mori, A. Ben Abdallah, and K. Kuroda, ”Design and Evaluation of a ComplexityEffective NetworkonChip Architecture on FPGA”,”’ The 19th Intelligent System Symposium (FAN 2009), pp.318321, Sep. 2009”’.
 M. Masuda, A. Canedo, A. Ben Abdallah, ”Efficient Code Generation Algorithm for Natural Instruction Level Parallelismaware Queue Architecture”,”’ The 19th Intelligent System Symposium (FAN 2009), pp.308313, Sep. 2009.”’ (Best Presentation Award).
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”Efficient Compilation for Queue SizeConstrained Queue Processors”, The Journal of Parallel Computing, Vol.35, pp. 213225, 2009. (Reprint PDF)
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Support for Code Size Reduction using a Queuebased Processor”, ”’Transactions on HighPerformance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269285, 2009.
Theses
 Yuuki Omoto, ”Development Environment for Single Chip Computer intended for Queue Computing Development and Education”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 8YOGT09.
 Haga Yasuyoshi, ”Architecture and Design of Application Specific Multicore SoC”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 7HYGT09 .
 Reo Honjoya,”Development ofUser Friendly Assembler for Queue Computers”, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 6ROGT09 .
 Mori Kenichi, ”Optimizations Techniques and FPGA Prototyping of OASIS NetworkonChip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 5MKGT09 ”’
 Miura Shohei,”Architecture and Design of Parameterizable NetworkonChip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 4MSMT09.
 新沼晴香, Yuichi Okuyama, “proposal of an Automatic Classification Method for Pulse Diagnosis Using SelfOrganizing Maps, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
 吉田幸祐, Yuichi Okuyama, “Acceleration of 2D Continuous Dynamic Programming by Memory Reduction and Parallelization”, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
2008
 A. Ben Abdallah, A. Canedo, T. Yoshinaga, and M. Sowa, The QC2 Parallel Queue Processor Architecture, ”’Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235245, 2008.”’
 T. Maekawa, A. Ben Abdallah, and K. Kuroda, ”Single Instruction DualExecution Model Processor Architecture”, ”’Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.3036, Dec. 2008.”’
 H. Hoshino, A. Ben Abdallah, and K. Kuroda, ”Advanced Optimization and Design Issues of a 32bit Embedded Processor Based on Produced Order Queue Computation Model”, ”’IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.1622, Dec.2008.”’
 Takahiro Machino, Shinya Iwazaki, Yuichi Okuyama, Junji Kitamichi, Kenichi Kuroda, and Ryuichi Oka, “Optimizing TwoDimensional Continuous Dynamic Programming for Cell Broadband Engine Processors,” JapanChina Joint Workshop on Frontier of Computer Science and Technology (FCST) 2008, pp.186193, Nagasaki, Japan, Dec. 2008.
 Toshiyuki Ito, Kazuya Mishou, Yuichi Okuyama, and Kenichi Kuroda, “A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices,” JapanChina Joint Workshop on Frontier of Computer Science and Technology (FCST) 2006, pp.196202, Japan, Nov. 2008.
 Daisuke Ohwada, Yuichi Okuyama, and Kenichi Kuroda, “Implementation of a Combined Autocorrelation Method for Realtime Tissue Elasticity Imaging on FPGA,” IEEE 8th International Conference on Computer and Information Technology, pp.891897, Sydney, Australia, July 2008.
 Kaai Kojima, Yuichi Okuyama, and Kenichi Kuroda, “Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation,” IEEE 8th International Conference on Computer and Information Technology, pp.886890, Sydney, Australia, July 2008.
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”Quantitative Evaluation of Common Subexpression Elimination on Queue Machines”, ”’Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (ISPAN 2008), pp.2530. 2008.”’
 A. Ben Abdallah, A. Canedo, and K. Kuroda, ”Processor for Mobile Applications”, ”’ISBN: 9781605660462, IGI Publishers, 2008.”’
 M. Akanda, A. Ben Abdallah, and M. Sowa, ”DualExecution Mode Processor Architecture”, ”’Journal of Supercomputing, Vol. 44, No. 2, pp. 103125, 2008.”’
 Md, M. Akanda, Architecture and Hardware Design of a DualExecution mode Processor Based on Produced Order Queue Execution Model, Doctor Thesis, UEC, 2008/3.
Theses
 Masashi Masuda, Graph Transformation Methods and Theoretical Performance Evaluation of Queue Computation Models, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
 Hiroki Hoshino, Advanced Hardware Optimization Algorithms for HighPerformance Queue Processor Architecture, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
 Tachi Maekawa, Research on Hardware Design of DualMode Processor Architecture, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
 猪狩修平, Yuichi Okuyama, “Implementation of Dynamic Instruction Set Computer using Dynamic Partial Reconfiguration Technology,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
 志賀瑞穂, Yuichi Okuyama, “Study on Convolution Systolic Array Adopted to the Digital Signal Processors on FPGA,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
 八巻翔, Yuichi Okuyama, “Design of Efficient Interface for RapidMatriX Considering Size and Locality of Matrix Multiplication,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
2007
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”A New Code Generation Algorithm for 2offset Producer Order Queue Computation Model”, ”’Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184194, 2007”’
 A. Ben Abdallah, and M. Sowa, ”Advanced Power Management Techniques for Mobile Communication Systems”, ”’Journal of Computer Research, Vol. 14, No.2, pp. 109128, 2007”’
 Mushiq Akanda, A. Ben Abdallah, and M. Sowa, ”DualExecution Mode Processor Architecture for Embedded Applications”, ”’Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347370, 2007.”’
 Y. Nakanishi, A. Canedo, A. Ben Abdallah, and M. Sowa, ”Optimizing Reaching Definitions Overhead in Queue Processors”, ”’Journal of Convergence Information Technology, 2007, Vol. 2, No. 4, pp. 3640, 2007.”’
 ”Multicore Systems on Chips”, ”’ISBN: ISBN 9788178952581, Editor (and one of the Authors): A. Ben Abdallah, Publishers: Signpost, 2007.”’
 A. Ben Abdallah, and M. Sowa, ”Efficient Design Methodology and Synthesizable Core for Multicore SoCs”, ”’ISBN: 9788178952581, Signpost Publishers, 2007”’
 A. Ben Abdallah, and M. Sowa, ”Buffer Design in Packet Switched Networks for MCSoCs Applications”, ”’ISBN: 9788178952581, Signpost Publishers, 2007.”’
 A. Ben Abdallah, and M. Sowa, ”Power Optimization Techniques for Mobile Multicore SoCs”, ”’ISBN: 9788178952581, Signpost Publishers, 2007.”’
 A. Ben Abdallah, T Yoshinaga, and M. Sowa, ”Mathematical Model for Multiobjective Synthesis of NoC Architectures”, ”’IEEE Proc. of the 36th International Conference on Parallel Processing, Sept., 2007.”’
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”Queue Register File Optimization Algorithm for QueueCore Processor”, ”’Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBACPAD 2007), pp. 169176, 2007.”’
 A. Canedo,A. Ben Abdallah, and M. Sowa, ”An Efficient Code Generation Algorithm for Code Size Reduction using 1offset PCode Queue Computation Model”, ”’Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196208, 2007”’
 A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Framework for an Embedded 32bit Queue Processor”, ”’Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877884, 2007.”’
 A. Ben Abdallah, On a Practical Queue Execution Model, Technical Report, School of Computer Science and Engineering, University of Aizu, 1/2007
2006
 A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”HighLevel Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core”, ”’Journal of Supercomputing, Vol. 38, Number 1, pp. 315, 2006.”’
 A. Ben Abdallah, Sotaro Kawata, and M. Sowa, ”Design and Architecture for an Embedded 32bit QueueCore”, ”’Journal of Embedded Computing, Special Issue in embedded singlechip multicore architectures, Vol. 2, No. 2, pp. 191205, 2006.”’
 A. Ben Abdallah, and M. Sowa, ”Advanced Power Reduction Techniques in Mobile Computing Systems”, ”’ISBN:1600212077, Nova Science Publishers, 2006.”’
 A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Scalable CoreBased Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)”, ”’Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 1418th, pp. 345352, 2006.”’
 A. Ben Abdallah, Masahiro Sowa, Basic NetworkonChip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization, Proc. of the Symposium on Science, Society, and Technology (TJASSST2006), pp. 17, 2006/12
2005
 T. Viet, T. Toshinaga ,A. Ben Abdallah, and M. Sowa, ”Construction of Hybrid MPIOpenMP Solutions for SMP Clusters”, ”’IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.2537, Jan. 2005.”’
 Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, Kenichi Kuroda, “A masterslave adaptive loaddistribution processor model on PCA,” The 12th Reconfigurable Architectures Workshop (RAW 2005), April 2005.
 M. Sowa, A. Ben Abdallah, and T. Yoshinaga, ”Processor Architecture Based on Produced Order Computation Model”, ”’Journal of Supercomputing, Vol. 32, No. 3, pp. 217229, June 2005.”’
 A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Modular Design Structure and HighLevel Prototyping for Novel Embedded Processor Core”, ”’Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340349, 2005.”’
 M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa, ”An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture”, ”’Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 7786, Dec. 2005.”’
 A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, ”Architecture of Producedorder Parallel Queue Processor: Preliminary Evaluation”, ”’Proc. of the 38th International Symposium on Microarchitecture (MICRO38), Nov. 2005.”’
 A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing”, ”’Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.”’
 Ta Quo Viet, T. Yoshinaga, and A Ben Abdallah, ”Performance Enhancement for Matrix Multiplication on an SMP PC Cluster”, ”’Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005. ”’
2004
 A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme”, ”’Proc. IEEE of the 7th HighPerformance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169177, July 2004.”’
 Shigeta, L.Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”QJava: Integrate Queue Computational Model into Java”, ”’Proc. of the Joint JapanTunisia Workshop on Computer Systems and Information Technology (JTCSIT’04), July 2004.”’
 A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, ‘7Design of ProducerOrder Parallel Queue Processor Architecture”, ”’Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 23, 2004.”’
 M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Highperformance Hybrid Processor Architecture with Efficient Hardware Usability”,”’ Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 23, 2004.”’
 H. Sasaki, Y. Okumura, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Theoretical Evaluation of Simultaneous Multi threading Parallel Queue Processor Architecture”, ”’Proc. International Conference on Circuits/Systems, Computers, and Communications, July 2004.”’
 A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, ”PQPpfB: Parallel Queue Processor Architecture in VerilogHDL”, ”’Proc. of 66th Information Processing Society of Japan, pp. 3F4, March 2004.”’
 T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, ”Optimization for Hybrid MPIOpenMP Programs on a Cluster of SMPs”, ”’SACSIS 2004”’.
 A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor”, ”’Proc. Of Information Processing Society of Japan, Vol. 60, pp. 3F4, 2004.”’
2003
 Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, and Kenichi Kuroda, “Reconfigurable InstructionLevel Parallel Processor Architecture,” ACSAC2003(LNCS 2823), pp.208220, Sep.2003.
 A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”On the Design of a Register Queue Based Processor Architecture (FaRMrq)”, ”’Proc. of the International Symposium on Parallel and Distributed Processing and Applications (ISPA 2003), pp.248262, July 2003.”’
 L. Q. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: QueueJava Compiler Design for High Parallelism Queue Java Bytecode”, ”’Proc. of International Technical Conference on Circuits/Systems, Computers, and Communications (ITCCSCC2003), pp. 900903, July 2003.”’
 A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Architectural Issues in the Design of a HighPerformance Parallel Queue Processor”, ”’Proc. of 4th TunisiaJapan Symposium on Science and Technology (TJASSST2003), April 2003.”’
 Tao. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPIOpenMP Solution for a Linear System on a Cluster of SMPP”, ”’SACSIS03, pp.299306, 2003.”’
 A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Reduced BitWidth Instruction Set Architecture for Qmode Execution in Hybrid Processor Architecture (FaRMrq)”, ”’Proc. of Information Processing Society of Japan, pp. 1923, June 2003.”’
 L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Fast, Effective Instruction Generation Algorithm For QueueJava Compiler (QJAVAC)”,”’ Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.5560, 2003. ”’
 L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”An Ambiguous ContextFree Grammar for Deterministic Parsing In QueueJava Compiler”, ”’Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.712, 2003. ”’
 L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: QueueJava Compiler Design for High Parallelism Queue Java”, ”’Proc. of IIEICE Technical Conference, 2003”’.
 T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPIOpenMP Solution for a Linear System on a Cluster of SMPs”,”’ Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299306, 2003. ”’
200102
 A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Complexity Analysis of a Functional Assignment Register Microprocessor”, ”’Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116123, Sep. 2002”’.
 Nattha Sretasereekul, Yuichi Okuyama, Hiroshi Saito, Masashi Imai, Kenichi Kuroda and Takashi Nanya, “Flexible Partitioning of CDFGs for Compact Asynchronous Controllers,” ITCCSCC2002, Vol.3, pp.17241727, Jul.2002.
 A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARMQueue Mode: On a Practical Queue Execution Model”, ”’Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939944, July 2001.”’
 Introduction to the Adaptive Systems Laboratory, ASL, UoA, Ref. TR2018O1, October 2018
 Kiriuka Nikolova, A. Ben Abdallah, and M. Sowa, ”Dynamical Critical Path ParallelismIndependent Scheduling Algorithm for Distributed Computing Systems”, ”’Proc. Of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929934, July 2001.”’
 A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, ”FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)”, TIWSS’01, October 2001.”’
2000
 A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamental of Electronics, Communications, and Computer Science, Vol. E83A No.12 pp.24172425, Dec. 2000.
 A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARMQueue Execution Model: Towards an Alternative Computing Paradigm”, ”’Proc. of IPSJ Symposium, Yokohama pp.99100, March 2000.”’
 A. Ben Abdallah, M. Sarem., and M. Sowa, ”Acyclic DFG on a Queue Machine”,”’ Proc. of JSPP, Tokyo, pp.119120, 2000.”’
 A. Ben Abdallah, and M. Sarem., ”Instruction Scheduling System for Super scalar Processor”, ”’JSPP, Tokyo, pp.161, Apr. 2000.”’
 Y. Okuyama, K. Kuroda, and K. Oguri, “Design Methodology for Applications Based on an Asynchronous Reconfigurable Architecture,” IS2000, pp.356361, Nov.2000.
 A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, ”’IEICE transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E83A No.12 pp.24172425, Dec. 2000.”’
 Ryoga Okada,Power and Performance Comparison of Electronic 2DNoC and OptoElectronic 2DNoC, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, March 2016. Technical Report.pdf
19961999
 A. Ben Abdallah, and M. Sowa, ”DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor”, ”’Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT’99), pp.131136, October 1999.”’
 A. Ben Abdallah, M. Sarem, and M. Sowa, ”A Survey on the advances of Disc I/O performance metrics”, ”’Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522527, July 1999.”’
 A. Ben Abdallah, A. Kazi, and L. L. Shan, ”MultiFunction Interface Board for Teaching Topics and Development System”, ”’APST97, Yata, PRC. pp.134139, Sep. 1997.”’
 L. L. Shan, L. Liu, and A. Ben Abdallah, ”The MasterSlave Two Level Distributed Microcomputer Measuring and Monitoring System”, ”’ISMTIT, Japan, pp. 161164, 1996”’
Technical Reports

 Achraf Ben Ahmed, PHENIC DesignFlow Poster, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, January 18, 2016.
 Akram Ben Ahmed et al. ”OASIS 3D Fault Tolerant Router Hardware Physical Design with TSVs”, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, May 28, 2015.
 Achraf Ben Ahmed, Introduction To Network Simulation With OMNET++ A case of PhoenixSim, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, 2015.
 Akram Ben Ahmed, OASIS 3DRouter Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
 Ben Ahmed Akram, A. Ben Abdallah, On the Design of a 3D NetworkonChip for Manycore SoC, Technical Report, The University of Aizu, Feb. 2012.
 A. Ben Abdallah, PHENIC: Silicon Photonic 3DNetworkonChip Architecture for Highperformance Heterogeneous Manycore SystemonChip, Technical Report, Ref. PTR0901A07152013, September 1, 2013.
 A. Ben Ahmed, Running BANSMOM System, Tutorial 1, July 2011.
 H. Hoshino, QSoC: Implementation of a Simple Queue SoC on FPGA, Technical Report, Adaptive Systems Lab, School of Computer Science and Engineering, The University of Aizu, Jan. 2009.
 T. Omoto, Qasm – UserFriendly Assembler for Queue Computers, Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, 2010.
 H. Hoshino, QC2 Data Path, Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Oct. 2009
 A. Ben Abdallah, QueueCore – The Strong Wave!, Technical report, Network Computing Laboratory, Graduate School of Information Systems, The University of Electrocommunications, May 2007
 A. Ben Abdallah, QueueCore Instruction Set Architecture, Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electrocommunications, January 2003.
 A. Ben Abdallah, QC1 Processing Stages Algorithms, Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electrocommunications, 2003.
 Kenichi Mori, OASIS NetworkonChip Prototyping on FPGA, Technical Report, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Technical Report
 Adaptive Systems Laboratory Research Introduction, Technical Report, Graduate School of Computer Science and Engineering, The University of Aizu, April 2018, [Technical Report]
 Akram Ben Ahmed, On the Design of a 3D NetworkonChip for Manycore SoC [#k7419422] Technical Report, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Technical Report
 Ryuya Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NOC, Technical Report, School of Computer Science and Engineering, The University of Aizu, Feb. 2012 Technical Report
 Vu Huy The, A Survey of Neuroinspired Computing Systems , Ref. 01162017, Adaptive Systems Laboratory, January 16, 2017
 Vu Huy The, A Comparison between OASIS NoC and Conventional Wormhole NoC Systems, Ref. 12082016, Adaptive Systems Laboratory, December 08, 2016
 Vu Huy The, OASIS NoC Survey, Ref. 11292016, Adaptive Systems Laboratory