Mitsuhiro Nakamura にそのファイルは見つかりません

Members-Internal

Background†

Problem†

Solution†

Research goal†

Design and Evaluation of 2D-OASIS-NoC Matrix Processor

Research Workflow†

Step1.SN/X + Matrix Processor(9/29 finish)
Step2.SN/X + Matrix Processor + Network Interface(10/25 now)
Step3.SN/X + Matrix Processor + Network Interface + Fault tolerant Router

Papers, Theses†

• 1. Akram Ben Ahmed, A. Ben Abdallah, LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture, '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012. [DOI]

• 2. OASIS-NoC Benchmark suite, April 2013.

• 3. 3D OASIS NoC Verilog HDL Code

• 4. OASIS 3D-Router Physical Design, Tutorial, July 5, 2014.

• 5. R. Okada, A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC Thesis, slides, Technical Report, Webpage

• 6 A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. Thesis, slides

• 7. About TSV: Physical design of a 3D router: reducing the number of vertical connections and enabling asynchronous Operation

3D-Matrix Processor

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