Vu Huy The - Oct. - Feb. 2017 の履歴(No.5)

• 履歴一覧
• 差分 を表示
• 現在との差分 を表示
• ソース を表示
• Vu Huy The - Oct. - Feb. 2017 へ行く。
  • 1 (2017-02-17 (金) 02:34:47)
  • 2 (2017-02-17 (金) 03:57:05)
  • 3 (2017-05-22 (月) 10:50:05)
  • 4 (2017-11-08 (水) 02:46:08)
  • 5 (2018-03-19 (月) 05:07:27)
  • 6 (2018-06-22 (金) 10:44:56)

---

Vu Huy The

Step 1 Due date: Nov. 11 18, 30 Dec 5 8, 2016†

• Step 1.1 OASIS NoC Survey Due date: Nov. 18 2016 [#e1465f0b]
  • &ref(): File not found: "onoc-survey-vht2016-v1.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (11/11/2016, Time:12:40 PM)
  • &ref(): File not found: "Onoc-Survey-Vht2016-V2.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (11/15/2016, Time:13:40 PM)
  • &ref(): File not found: "onoc-survey-vht2016-v3.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (11/18/2016, Time:16:31 PM)
  • &ref(): File not found: "onoc-survey-vht2016-v4.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (11/29/2016, Time:15:55 PM) (&ref(): File not found: "oasis-noc-survey_latex.zip" at page "Vu Huy The - Oct. - Feb. 2017";)

• Step 1.2 Compare OASIS-NoC with Conventional NoC (supporting VCs and WH) Due date: Nov. 30, Dec 5, 8, 2016

• The following is a Verilog source code of a (conventional) router and a 3x3 NoC which implements VCs and WH. (A) Verilog HDL source code of VC-WH Router/NoC (B) [Read this RELATED reference (Efficient_Microarchitecture_for_Netwok-on-Chip.pdf (Ph.D. Thesis, 2012.)) for details about the conventional NoC architecture.]

• 1. Synthesize a conventional 3x3 NoC system (VCs and WH) with QII and extract the complexity, speed, and power.
• 2. Use some benchmarks (test-benches) and evaluate the conventional 3x3 NoC system performance - bandwidth and ETE latency.
• 3 (Option). Use a DE2 FPGA board and test/simulate a conventional 3x3 NoC system.

• &ref(): File not found: "onoc-cnoc-study-vht2016-v1.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (12/5/2016, Time:14:20 PM)

• &ref(): File not found: "onoc-cnoc-study-vht2016-v2.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (12/8/2016, Time:14:08 PM ) (&ref(): File not found: "comparison-oasis-noc_latex.zip" at page "Vu Huy The - Oct. - Feb. 2017";)

Step 2 Due date: Dec. 20 26 31, 2016†

• Step 2.1 Study of Neural Network kown topology/network
  • Reference:
    • Neural Networks Fundamental
    • NN Basics

• &ref(): File not found: "NeuroArch-survey-vht2016-v1.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (12/31/2016, Time:17:10 PM)

• Step 2.2 Study of Neuro-inspired Computing Systems (survey ASIC Analog SNN/ANN; ASIC Digital SNN/ANN; FPGA SNN/ANN; DSP SNN/ANN)

• References:

• Artificial neural networks in hardware: A survey of two decades of progress, 2010.

• Exploring the potential of brain-inspired computing, Ph.D. Thesis, 2015.

• &ref(): File not found: "neuro-survey-vht2016-v1.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (12/24/2016, Time:17:05 PM)
• &ref(): File not found: "neuro-survey-vht2016-v2.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (12/31/2016, Time:17:05 PM)

• &ref(): File not found: "neurosystem-survey-vht2016.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (01/16/2017, Time:12:25 PM)

Step 3 Due date: January 18 10, 2017†

• Step 3.1 Study and design in Verilog HDL only ONE Neuron Circuit.
  • Use Quartus II for the synthesis of a single neuron.
  • The resource needed for a single neuron are: (1) A multiplication block, (2) An accumulation block, and (3) an active function block (use sigmoid as the active function).

• Step 3.2 Implementation of a Simple Neural Network on DE2 FPGA board (Refer to this open source simple NN Project in VHDL)
  • Note: This task is also needed for your next COSCO Demo on Jan 18, 2017.

• &ref(): File not found: "ann-imp-study-vht2017-v1.pdf" at page "Vu Huy The - Oct. - Feb. 2017"; (01/10/2017, Time:18:05 PM)

Step 4 Due date: Jan. 31, 2017†

• Step 4.1 Detailed Survey of On-chip Learning/Training Algorithms and Architectures. Focus should be on embedded vision (video) applications; precisely on object detection/classification)

• Survey well-known algorithms and hardware for on-chip learning.
• Survey/explore the potential of on-chip learning to reveal algorithm and design needs.
• Survey fundamental learning theories, discuss numerical algorithms and their complexity in implementation.

References:

• Neuromorphic Learning VLSI Systems: A Survey
• Spike Timing Dependent Plasticity (STDP)
• Back-propagation,

• Optional: Hopfield; Boltzmann; Probabilistic NN; K-nearest neighbor (KNN); restricted coulomb energy (RCE); Region-of-Influence (ROI), Gradient-Descent (DL)

Please upload the survey.pdf here.

Jan 23 to Feb. 8, 2017 --> Return to Home Country (Holidays)†

Step 5: Due date: Feb. 10 15, 2017†

• Complete Doctoral Research Proposal and Plan

• Refer to these slides (from slide 33)

• Doctoral-Research-Proposal-and-Plan-v1.pdf (02/17/2017, Time:13:00 PM)

Note: No need for a report this time. We only need slides.

***Step 5 Due date: March 10 13, 2017. (Please prepare .ppt slides and make a presentation) [#hcfb473c]

• Step 5.1
  • Describe the overall system organization and Propose a light-weight learning algorithm for NASH System. (NASH stands for 'Neuro-inspired ArchitectureS in Hardware' Project in ASL)

• References:
  • 0. Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition, Nov. 2014.
  • 1. A Low-voltage, Low power STDP Synapse implementation using Domain-WallMagnets for Spiking Neural Networks

• 2. FPGA-based Architecture for Real-time Synaptic Plasticity computation

• 3. PhD Thesis -Theory of non-linear spike-time-dependent plasticity

• 4. Demonstration of STDP based Neural Networks on an FPGA

• 5. Neuron Models on FPGA, Verilog HDL

• 6.Design of silicon brains in the nano-CMOS era: Spiking neurons,learning synapses and neural architecture optimization, A.S. Cassidy et al. / Neural Networks 45 (2013) 4–26

• 7. ConvNet Hardware

• Step 5.2 Due date: April 30, 2017. Please prepare 8 to 10 pages draft and make a presentation without slides ---> Extended to May 8, 2017.

• Draft a conference paper about Acceleration (using FPGA) of Image Recognition with Deep Convolution Neural Network based on FT Packet Switched Network.

• Paper of NASH-CNN (5/22/2017, Time:7:25 PM) (&ref(): File not found: "20170522-NASH-CNN_Latex.zip" at page "Vu Huy The - Oct. - Feb. 2017";)

• Conf. http://www.mcsoc-forum.org/ http://www.aiccsa.net/AICCSA2017/

Step 6: LIF spiking neuron model, proposal of a light-weight spiking learning algorithm for NASH†

• Step 6.1: Study of CNN to SNN conversion
  • Pre-trained SNN: training CNN, then applying learned weights into SNN. (7/3/2017, Time:2:00 PM) (&ref(): File not found: "ANNtoSNN_survey.pdf" at page "Vu Huy The - Oct. - Feb. 2017";)
  • Directly training a SNN, due date: July 24.
• Step 6.2: Propose and evaluate learning method for SNN in hardware, due date: Aug. 28.

Step 7: A Scalable Fault-tolerant Multicast Routing Algorithm and Architectyure for for NASH Sytem†

• Step 7.1: Study related works, (due date: Sept. 30)
• Step 7.2: Propose a router architecture (due date: Oct. 10 6)
• Step 7.3: Implement a whole network architecture (due date: Oct. 31)
• Step 7.4: Evaluate the routing algorithm and write a draft conf. paper (due date: Nov. 30 24)

Step 8: An Enfficient Lighweight Fault-tolerant Multicast (3D)-Router for NASH Sytem†

• Step 8.1: Survey and report,(due date: Dec. 8, 2017.)

• Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations, 2013

• Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers, 2012

• An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations

• "Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations", Proc. 21th Int'l Conf. Artificial Neural Networks, pp. 77-84, 2011, S. Carrillo, J. Harkin, L. McDaid, S. Pande, S. Cawley, F. Morgan,
• "A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks," International Journal of Reconfigurable Computing, vol. 2009, pp. 1-13, J. Harkin, F. Morgan, L. McDaid, S. Hall, B. McGinley, and S. Cawley, Pelase make a presentaiton about this survey on Dec. 8, 2017.