Print this Page

Designing with Quartus II, SOPC and FPGA

Designing with Quartus II, SOPC and FPGA – All you need to know!

Authors: Hiroki Hoshino, Taichi Maekawa, Abderazek Ben Abdallah, April 2009.

Introduction to Verilog HDL

Before you use Quartus II and other CAD tools, you need first to understand how to program with Verilog HDL. To do so, read this tutorial about Verilog HDL.

Quartus II

  • Target Device
  • The desired desing

1 Starting a New Project

  1. Activation of Quartus 2
    Quartus_Quartus_0.png
  2. Select File->New Project Wizard
  3. New Project Wizard window appears
    Quartus_New_Project_Wiz_Intro.png
  4. Click Next
  5. Select introtutorial as a working directory
  6. Type light as a project name
  7. Automatily “light” appears as a top-level design entity
    Quartus_New_Project_Wiz_Dir.png
  8. Click Next
    Quartus_New_Project_Wiz_Add.png
  9. Click Next
  10. Select Cyclone 2 as a Family in Device family area
  11. Select EP2C35F672C6 as a target device name in Available devices area
    Quartus_New_Project_Wiz_Fam.png
  12. Click Next
    Quartus_New_Project_Wiz_EDA.png
  13. Click Next
    Quartus_New_Project_Wiz_Sum.png
  14. Click Finish
    Quartus_Quartus_light_0.png

2 Design Entry Using Verilog Code

  1. Select File->New
  2. Choose Design Files->Verilog HDL File
    Quartus_New_Verilg_HDL.png
  3. Click OK
    Quartus_light_0.png
  4. Make a program
    Quartus_light_1.png
  5. Select File->Save As
  6. Name “light”
  7. Choose Verilog VHL File as file type
    Quartus_light_save.png
  8. Click OK
    Quartus_light_2.png

3 Compiling the Designed Circuit

  1. Select Processing->Start compilation
    Quartus_Compilation.png
  2. Click OK
    Quartus_light_3.png

4 Pin Assignment

  1. Select Assignments->Pins
  2. Double Click a empty space on Location and f
  3. Scroll down and select PIN_AE22
  4. Double Click a empty space on Location and x1
  5. Scroll down and select PIN_N26
  6. Double Click a empty space on Location and x2
  7. Scroll down and select PIN_N25
    Quartus_Pin_Planner_1.png
  8. Select File->Close
    Quartus_light_4.png

5.Simulation the Designed Circuit

5-1.Design Wave Form

  1. Select File->New
  2. Choose Design Verification/Debugging->Vector Waveform File
    Quartus_New_Vector_Waveform.png
  3. Click OK
    Quartus_light_5.png
  4. Select Edit->End Time
  5. Enter 200 and select ns
    Quartus_End_Time.png
  6. Click OK
    Quartus_light_8.png
  7. Select View->Fit in Window
    Quartus_light_9.png
  8. Select Edit->Insert->Insert Node or Bus
    Quartus_Insert_Node_or_Bus_0.png
  9. Click Node Finder
  10. Pull down and select Pin:all in Filter area
  11. Click >>
    Quartus_Node_Finder_0.png
  12. Click OK
    Quartus_Insert_Node_or_Bus_1.png
  13. Click OK
    Quartus_light_10.png
  14. Set x1 to 0 in the time interval 0 to 100ns
  15. Set x1 to 1 in the time interval 100 to 200 ns
  16. Set x2 to 0 in the time interval 0 to 50 ns and 100 to 150 ns
  17. Set x2 to 1 in the time interval 50 to 100 ns and 150 to 200 ns
    Quartus_light_11.png
  18. Select File->Save As (file name is light.vwf)
    Quartus_light_vwf_save.png
  19. Click OK
    Quartus_light_12.png

5-2.Performance the Simulation -Functional Simulation

  1. Select Assignments->Settings
  2. Select Simulator Settings on Category tree
  3. Choose Functional as the Simulation mode
  4. Choose light.vwf file as the Simulation input
    Quartus_Settings_Simulator.png
  5. Click OK
    Quartus_light_33.png
  6. Select Processing->Generate Functional Simulation Netlist
    Quartus_Netlist_Generation.png
  7. Select OK
    Quartus_light_14.png
  8. Select Processing->Start Simulation
    Quartus_Simulator.png
  9. Click OK
    Quartus_light_15.png
  10. Select View->Fit in Window
    Quartus_light_16.png

5-3.Performance the Simulation -Timing Simulation

  1. Select Assignments->Settings
  2. Select Simulator Settings on Category tree
  3. Choose Timing as the simulation mode
    Quartus_Settings_Simulator_2.png
  4. Click OK
    Quartus_light_17.png
  5. Select Processing->Start Simulation
    Quartus_Simulator_2.png
  6. Click OK
    Quartus_light_18.png

6.Programming and Configuring the FPGA Device

6-1.JTAG Programming (Hardware)

  1. Connect a host computer and the DE2 board
  2. Power on the DE2 board

6-2.JTAG Programming (Software)

  1. Flip the RUN/PROG switch into the RUN position
  2. Select Tools->Programmer
  3. Select JTAG in the Mode box
    Quartus_light_cdf_0.png
  4. Press Hardware Setup…
  5. Select USB Blaster
    Quartus_Hardware_Setup.png
  6. Click Close
    Quartus_light_cdf_1.png
  7. Press Start

7.Example

7-1.light design -complete design

filelight (new link – introtutorial)

7-2.Full adder design – complete design

fileFull Adder (new link – Sample)

SOPC builder

  • Configuration of the DE2 board with Nios2
    SOPC_Config_DE2_with_Nios_2.png
  • In this page, I make below configuration
    SOPC_DE2_config_example.png

1 Designing the hardware depicted above figure

  1. Activation of Quartus 2
    SOPC_initial_Quartus.png
  2. Select File->New Project Wizard
  3. New Project Wizard window appears
    SOPC_New_Project_Wiz_Intro.png
  4. Click Next
  5. Select sopc_builder_tutorial as a working directory
  6. Type lights as a project name
  7. Automatily “lights” appears as a top-level design entity
    SOPC_New_Project_Wiz_Dir.png
  8. Click Next
    SOPC_New_Project_Wiz_Add.png
  9. Click Next
  10. Select Cyclone 2 as a Family in Device family area
  11. Select EP2C35F672C6 as a target device name in Available devices area
    SOPC_New_Project_Wiz_Fam.png
  12. Click Next
    SOPC_New_Project_Wiz_EDA.png
  13. Click Next
    SOPC_New_Project_Wiz_Sum.png
  14. Click Finish
    SOPC_Quartus_lights_1.png
  15. Select Tools->SOPC Builder
  16. Enter nios_system as the system name
  17. Choose Verilog as the target HDL
    SOPC_SOPC_Cre_New_Name.png
  18. Click OK
    SOPC_initial_SOPC.png
  19. Select Nios 2 Processor and click Add
  20. Choose Nios 2/e
    SOPC_SOPC_Nios.png
  21. Click Finish
    SOPC_SOPC_2.png
  22. Select Memory and Memory Controllers->On-Chip->On-Chip Memory(RAM or ROM) and click Add
  23. Set the memory width to 32 bits and total memory size to 4Kbytes
    SOPC_SOPC_On_Chip_Mem.png
  24. Click Finish
    SOPC_SOPC_3.png
  25. Select Peripherals->Microcontroller Peripherals->PIO(Parallel I/O) and click Add
  26. Specify the width of the port to be 8bits
  27. Choose the direction of the port to be Input
    SOPC_SOPC_PIO_input.png
  28. Click Finish
    SOPC_SOPC_4.png
  29. Select Peripherals->Microcontroller Peripherals->PIO(Parallel I/O) and click Add
  30. Specify the width of the port to be 8bits
  31. Choose the direction of the port to be Output
    SOPC_SOPC_PIO_output.png
  32. Click Finish
    SOPC_SOPC_5.png
  33. Select Interface Protocols->Serial->JTAG UART and click Add
    SOPC_SOPC_JTAG_UART.png
  34. Click Finish
    SOPC_SOPC_6.png
  35. Right-click on the pio_0 name and then select Rename
  36. Change the name to Switches
  37. Right-click on the pi0_1 name and then select Rename
  38. Change the name to LEDs
    SOPC_SOPC_7.png
  39. Select System->Auto-Assign Base Addresses
    SOPC_SOPC_8.png
  40. Right-click on the cpu and then select Edit
  41. Select onchip_memory2_0 to be the memory device for both reset vector and exception vector
    SOPC_SOPC_Nios_2.png
  42. Click Finish
    SOPC_SOPC_9.png
  43. Select the System Generation tab
  44. Turn off Simulation. Create project simulator files
    SOPC_SOPC_10.png
  45. Click Generate
    SOPC_SOPC_11.png
  46. After “SUCCESS: SYSTEM GENERATION COMPLETED” appear, click Exit
    SOPC_Quartus_lights_2.png

2 Integration of the Nios 2 System into a Quartus 2 Project

To do list

  • Instantiate the module generated by the SOPC Builder into the Quartus 2 project
  • Assign the FPGA pins
  • Compile the designed circuit
  • Program and configure the Cyclone 2 device on the DE2 board

2-1. Instantiation of the Module Generated by the SOPC Builder

  1. Select File->New
    SOPC_Quartus_New.png
  2. Select Design Files->Verilog HDL File and click OK
    SOPC_Quartus_lights_3.png
  3. Copy below program and save the file called lights.v
    //Implements a simple Nios 2 system for the DE2 board
    //Inputs:  SW7-0 are parallel port inputs to the Nios 2 system
    //         CLOCK_50 are parallel port inputs to the Nios 2 system
    //         KEY0 is the active-low system reset
    //Outputs: LEDG7-0 are parallel port outputs from the Nios 2 system
    module lights(SW,KEY,CLOCK_50,LEDG);
       input [7:0] SW;
       input [0:0] KEY;
       input CLOCK_50;
       output [7:0] LEDG;
       
    //Instantiate the Nios 2 system module generated by the SOPC Builder
    //nios_system(clk, reset_n, out_port_fromm_the_LEDs, in_port_to_the_Switches)
       nios_system Nios2 (CLOCK_50, KEY[0], LEDG, SW);
    
    endmodule
    SOPC_Quartus_lights_4.png
  4. Select Project->Add/Remove File in Project
  5. Add all *.v files produced by the SOPC Builder except for nios_system_inst.v
    SOPC_Setting_Files_lights.png
  6. Click OK
    SOPC_Quartus_lights_5.png
  7. Select Asignments->Import Assignment
  8. Select filelights (new link – light) as File name
    SOPC_Import_Assignments.png
  9. Click OK
    SOPC_Quartus_lights_6.png
  10. Select Processing->Start Compilation
    SOPC_Quartus_lights_7.png

2. Programming and Configuration

  1. Connect the DE2 board to the host computer by means of a USB cable plugged into the USB-Blaster port.
  2. Turn on the power to the DE2 board.
  3. Ensure that the RUN/PROG switch is in the RUN position
  4. Select Tools->Programmer
  5. Select JTAG in the Mode box
  6. Press the Hardware Setup…
  7. Select the USB-Blaster
    SOPC_Programmer.png
  8. Press Start

Nios 2 IDE 9.1

  • Running the Application Program Using a Nios 2 Assembly Language Program
  • After you setup a hardware connection using DE2 board and host computer, you can run the assembly program.

1.Starting a new project

  1. Activation of Nios 2 IDE
    IDE_IDE_labwork_0.png
  2. Select File->New->Nios 2 C/C++ Application
    IDE_New_Project_1.png
  3. Select Blank Project in Select Project Template
  4. Type “labwork” as a project name in Name field
  5. Check Specify Location
  6. Select a location as a working directory
  7. Select a filetest (new link – labwork) as a SOPC Builder System PTF File in a Select Target Hardware field.
  8. Automatically “cpu” appears as a CPU in a Select Target Hardware field.
    IDE_New_Project_2.png
  9. Select Next
    IDE_New_Project_3.png
  10. Click Finish

2. Making an assembly file

IDE_IDE_labwork_1.png
  1. After right click on the labwork project, Select New->New Source File
    IDE_New_Source_File_0.png
  2. Type “labwork2.s” as a Source File (.s means assembly file)
    IDE_New_Source_File_1.png
  3. Click Finish
  4. Copy below  assembly program to labwork2.s
     	# Lab program for Nios-II IDE tutorial
            
            .text                   # 
    
            .global main            # makes label "main" globally known
    
    main:   movi    r10,0x41        # Load the hexadecimal value 41
                                    # to register r10
    
    loop:   mov     r4,r10          # Copy to r4  from r10
    
            nop                     # (later changed to call hexasc)
            nop                     # (later changed to mov r4, r2)
    
            movia   r15,putchar     # copy subroutine address to register
            callr   r15             # call subroutine via register
    
            addi    r10, r10,1      # Add 1 to register r10
            andi    r10, r10, 0x7f  # mask with 7 bits
            ori     r10, r10, 0x20  # set a bit to avoid control chars
    
            br      loop            # 
    
            .end                    # The assembler will stop here
            foo bar bletch          # comes after .end - ignored

3. Compiling the assembly program

  1. Focusing on a labworks2.s, Select File->Save
    IDE_IDE_labwork_2.png
  2. After right click on “labwork” project, select Run As->Nios 2 Instruction Set Simulator
  1. After some delay, you will see the ASC2 alphabet in the Console window of the Nios 2 IDE.
    IDE_IDE_labwork_3.png
  • This is the output from your assembler program
  1. If a configuration and an assembler program are correct, DE2 board will display the desired work

More information

SOCP_Name_Target_HDL.png SOCP_main.png Quartus_Open.png

Updated on April 2009.

Permanent link to this article: http://adaptive.u-aizu.ac.jp/?page_id=680