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開始行:
[[Internal/MULTICORE]]
#CONTENTS
#ref(multicore-chips-2010-survey.gif,,20%);
*Reducing Memory Operations [#s748a881]
***Approach 1 [#d92b569d]
-Active Memory Operation
--Seoul National University, Seoul
---[[Active Memory Processor for Network-on-Chip Based Architecture>http://doi.ieeecomputersociety.org/10.1109/TC.2011.66]], IEEE transaction on computer, Preprint. [[References>http://aslweb.u-aizu.ac.jp/benlab/index.php?references-korea]]
*** Approach 2 [#oca0e0d7]
--[[Task allocation with algorithm transformation>http://search.ieice.org/bin/pdf.php?lang=E&year=2010&fname=e93-a_12_2570&abst=]], IEICE transaction, Dec. 2010. [[References>http://aslweb.u-aizu.ac.jp/benlab/index.php?task-allocation-ref]]
----
* Coherence [#ff02f254]
-[[Cache Coherence Mechanism>Cache-Coherence]]
--[[Espana>http://www.gap.upv.es/index.php/home/list-of-publications.html]]
---[[Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks>http://skywalker.inf.um.es/~aros/papers/bcuesta-isca11.pdf]]. In 38th International Symposium on Computer Architecture (ISCA), pages 93-103. San Jose (California) : Association for Computing Machinery (ACM), 2011.
--IBM ([[Ashwini K Nanda>http://domino.research.ibm.com/comm/research_people.nsf/pages/ashwini.index.html]])
---M. Dubois, J. Jeong and A. K. Nanda, "Shared Cache Architectures for Decision Support Systems," Performance Evaluation, Vol. 49, Sept. 2002, pp 283-298.
---A. K. Nanda, A-T. Nguyen, M. Michael, D. Joseph, “High Throughput Coherence Control and Hardware Messaging in Everest,” IBM Journal of Research and Development, March 2001.
---Maged M. Michael Ashwini K. Nanda,[[Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors>http://www.computer.org/portal/web/csdl/doi/10.1109/HPCA.1999.744354]], The Fifth International Symposium on High Performance Computer Architecture, 1999.
---M. Michael, A.K. Nanda and B.H. Lim, "Coherence Controller Architectures for Scalable Shared Memory Multiprocessors", IEEE Transactions on Computers, pp. 245-255, Feb. '99.
---A.K. Nanda, J. Bondi and S. Dutta, "The Misprediction Recovery Cache," International Journal of Parallel Programming, April 1998.
---U. Ko, P. Balsara and A.K. Nanda, "Power and Performance Optimization for On-Chip Multi Level Cache Hierarchies in Microprocessors", IEEE Transactions on VLSI Systems, pp. 299-308, June 1998.
---A.K. Nanda and L.N. Bhuyan, "Efficient Mapping of Applications onto Cache Coherent Multiprocessors," Journal of Parallel and Distributed Computing, Nov. 1993.
---A.K. Nanda and L.N. Bhuyan, "Design and Analysis of Cache Coherent Multistage Interconnection Networks," IEEE Transactions on Computers, April 1993.
--Israel [[here>http://webee.technion.ac.il/labs/comnet/opnet/]]
--- [[The Power of Priority: NoC based Distributed Cache Coherency>http://www.ee.technion.ac.il/bolotin/papers/power_of_priority.pdf]],2007 (''The paper investigates directory based coherence schemes which are the topic of our work'')
---Radovic, Z. Hagersten, E. , “Efficient Synchronization for
Nonuniform Communication Architectures”, Supercomputing, ACM/IEEE 2002 Conference. (''the paper investigates Cache Snooping'') .
Traditional snooping protocols for cache coherency are not suitable for
implementation over a NoC, and are not scalable with the number of cores
--Synchronization (Bo Hong)
---[[Hardware-based Synchronization Support for Shared Accesses in Multicore Architectures>http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.135.9036&rep=rep1&type=pdf]], Bo Hong, Philadelphia Univ.
*Toward Energy-efficient Computing [#wf08fb58]
-[[Toward enery efficient computing>http://queue.acm.org/detail.cfm?id=1730791]], Queue ACM.
*Specialized and GPU Benchmark Suites [#x7875d89]
Other parallel benchmark suites include MineBench [28]
for data mining applications, MediaBench [20] and ALPBench
[17] for multimedia applications, and BioParallel [14]
for biomedical applications. The motivation for developing
these benchmark suites was to provide a suite of applications
which are representative of those application domains, but not
necessarily to provide a diverse range of behaviors. None of
these suites support GPUs or other accelerators.
The Parboil benchmark suite [33] is an effort to benchmark
GPUs, but its application set is narrower than Rodinia’s and
no diversity characterization has been published. Most of the
benchmarks only consist of single kernels.
----
*Mulithreading (Java, ..) [#pfe72ae1]
- [[Multithreading in Java: Performance and Scalability on Multicore Systems>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2010.232]], November 2011 (vol. 60 no. 11), IEEE Transaction on Computer,
pp. 1521-1534
----
*TOPPERS RTOS [#nf648456]
- TOPPERS: [[TOPPERS-Pro, the First Commercial Real-Time Operating System for Altera Nios II Multiprocessor Designs>http://www.altera.com/corporate/news_room/releases/releases_archive/2007/products/nr-toppersai.html]], 2007.
-[[Real-Time Operating Systems for Multicore Embedded Systems>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=RTOS_Multicore_ES.pdf&refer=Internal%2FMULTICORE]], IEEE 2008.
- Hiroaki Takada, [[Introduction to the TOPPERS Project Open Source RTOS for Embedded systems>http://www.computer.org/portal/web/csdl/abs/proceedings/isorc/2003/1928/00/19280044abs.htm]], Proceedings of the Sixth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'03) , pp. 44 – 45, 2003.
- [[Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device>http://www.design-reuse.com/articles/24254/inter-processor-communication-multi-core-processors-reconfigurable-device.html]].
----
*Multicore DSP [#f26c7fb6]
- "[[Trends in Multi-core DSP Platforms>http://users.ece.utexas.edu/~bevans/papers/2009/multicore/MulticoreDSPsForIEEESPMFinal.pdf]]". IEEE Signal Processing Magazine, Special Issue on Signal Processing on Platforms with Multiple Cores, 2009.
- [[Multiprocessor System-on-Chip (MPSoC)
Technology>http://www.ece.mtu.edu/~zhuofeng/EE5970Spring2011_files/Multiprocessor%20System-on-Chip%20(MPSoC)%20Technology.pdf]], IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008
***Task Hraph [#b29c5da9]
-[[Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2011.153]], IEEE Transaction on Computer, 2012.
***Sorting Algorithm on Multicore [#q3f3d91b]
-[[Efficient Implementation of Sorting on MultiCore SIMD CPU Architecture>http://www.vldb.org/pvldb/1/1454171.pdf]], PVLDB '08, August 23-28, 2008, Auckland, New Zealan.
----
*Miroprocessor [#wb4d7cc7]
-[[Vishwani D. Agrawal Talkss>http://www.eng.auburn.edu/~agrawvd/TALKS/talks.html]]
-[[TOR M. AAMODT, Canada>http://www.ece.ubc.ca/~aamodt/research.html]]
----
*Multicore Resourec allocation/Mapping [#x5945426]
-[[RESOURCE MANAGEMENT IN SINGLE-CHIP MULTIPROCESSORS>http://cva.stanford.edu/publications/2005/thesis_kashaw.pdf]], Ph.D. thesis, 2005.
--[[more publications from Stanford Univ.>http://cva.stanford.edu/publications/]]
*Companies [#l392cb01]
-[[iwaves>http://www.iwavesystems.com/]],iWave Systems is a Technology oriented organization specialized in Embedded Hardware and Software Turnkey Design ...
*People Wokring on Power Reduction [#o4f62966]
-UEC - [[Kondo>http://www.hpc.is.uec.ac.jp/kondo/]]
--[[Kondo all Publications>http://aslweb.u-aizu.ac.jp/benlab/index.php?Kondo-Publications]]
---Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "[[Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4814485&tag=1]]", IEEE Transactions on VLSI, Vol.17 Issue 6, pp. 848-852, June 2009. (Transactions Briefs)
----
-Florida Univ. - [[Roy>http://www.cse.usf.edu/~sroy/]]
--[[Roy all Publications>http://aslweb.u-aizu.ac.jp/benlab/index.php?Roy-publications]]
---[[State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2010.249]], IEEE Transaction on computer, Nov. 2011. [[references>http://aslweb.u-aizu.ac.jp/benlab/index.php?state-retentive-references]]
---S. Roy, N. Ranganathan, S. Katkoori, "A Framework for Power Gating Functional Units in Embedded Microprocessors", IEEE Transactions on Very Large Scale Integrated Systems, Volume 17, Issue 11, November 2009, Page(s):1640-1649
----
University of Virginia
-[[Kevin Skadron >http://www.cs.virginia.edu/~skadron/]]
-[[Distributed Systems>http://net.pku.edu.cn/~course/cs501/2012/schedule.html]]
終了行:
[[Internal/MULTICORE]]
#CONTENTS
#ref(multicore-chips-2010-survey.gif,,20%);
*Reducing Memory Operations [#s748a881]
***Approach 1 [#d92b569d]
-Active Memory Operation
--Seoul National University, Seoul
---[[Active Memory Processor for Network-on-Chip Based Architecture>http://doi.ieeecomputersociety.org/10.1109/TC.2011.66]], IEEE transaction on computer, Preprint. [[References>http://aslweb.u-aizu.ac.jp/benlab/index.php?references-korea]]
*** Approach 2 [#oca0e0d7]
--[[Task allocation with algorithm transformation>http://search.ieice.org/bin/pdf.php?lang=E&year=2010&fname=e93-a_12_2570&abst=]], IEICE transaction, Dec. 2010. [[References>http://aslweb.u-aizu.ac.jp/benlab/index.php?task-allocation-ref]]
----
* Coherence [#ff02f254]
-[[Cache Coherence Mechanism>Cache-Coherence]]
--[[Espana>http://www.gap.upv.es/index.php/home/list-of-publications.html]]
---[[Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks>http://skywalker.inf.um.es/~aros/papers/bcuesta-isca11.pdf]]. In 38th International Symposium on Computer Architecture (ISCA), pages 93-103. San Jose (California) : Association for Computing Machinery (ACM), 2011.
--IBM ([[Ashwini K Nanda>http://domino.research.ibm.com/comm/research_people.nsf/pages/ashwini.index.html]])
---M. Dubois, J. Jeong and A. K. Nanda, "Shared Cache Architectures for Decision Support Systems," Performance Evaluation, Vol. 49, Sept. 2002, pp 283-298.
---A. K. Nanda, A-T. Nguyen, M. Michael, D. Joseph, “High Throughput Coherence Control and Hardware Messaging in Everest,” IBM Journal of Research and Development, March 2001.
---Maged M. Michael Ashwini K. Nanda,[[Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors>http://www.computer.org/portal/web/csdl/doi/10.1109/HPCA.1999.744354]], The Fifth International Symposium on High Performance Computer Architecture, 1999.
---M. Michael, A.K. Nanda and B.H. Lim, "Coherence Controller Architectures for Scalable Shared Memory Multiprocessors", IEEE Transactions on Computers, pp. 245-255, Feb. '99.
---A.K. Nanda, J. Bondi and S. Dutta, "The Misprediction Recovery Cache," International Journal of Parallel Programming, April 1998.
---U. Ko, P. Balsara and A.K. Nanda, "Power and Performance Optimization for On-Chip Multi Level Cache Hierarchies in Microprocessors", IEEE Transactions on VLSI Systems, pp. 299-308, June 1998.
---A.K. Nanda and L.N. Bhuyan, "Efficient Mapping of Applications onto Cache Coherent Multiprocessors," Journal of Parallel and Distributed Computing, Nov. 1993.
---A.K. Nanda and L.N. Bhuyan, "Design and Analysis of Cache Coherent Multistage Interconnection Networks," IEEE Transactions on Computers, April 1993.
--Israel [[here>http://webee.technion.ac.il/labs/comnet/opnet/]]
--- [[The Power of Priority: NoC based Distributed Cache Coherency>http://www.ee.technion.ac.il/bolotin/papers/power_of_priority.pdf]],2007 (''The paper investigates directory based coherence schemes which are the topic of our work'')
---Radovic, Z. Hagersten, E. , “Efficient Synchronization for
Nonuniform Communication Architectures”, Supercomputing, ACM/IEEE 2002 Conference. (''the paper investigates Cache Snooping'') .
Traditional snooping protocols for cache coherency are not suitable for
implementation over a NoC, and are not scalable with the number of cores
--Synchronization (Bo Hong)
---[[Hardware-based Synchronization Support for Shared Accesses in Multicore Architectures>http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.135.9036&rep=rep1&type=pdf]], Bo Hong, Philadelphia Univ.
*Toward Energy-efficient Computing [#wf08fb58]
-[[Toward enery efficient computing>http://queue.acm.org/detail.cfm?id=1730791]], Queue ACM.
*Specialized and GPU Benchmark Suites [#x7875d89]
Other parallel benchmark suites include MineBench [28]
for data mining applications, MediaBench [20] and ALPBench
[17] for multimedia applications, and BioParallel [14]
for biomedical applications. The motivation for developing
these benchmark suites was to provide a suite of applications
which are representative of those application domains, but not
necessarily to provide a diverse range of behaviors. None of
these suites support GPUs or other accelerators.
The Parboil benchmark suite [33] is an effort to benchmark
GPUs, but its application set is narrower than Rodinia’s and
no diversity characterization has been published. Most of the
benchmarks only consist of single kernels.
----
*Mulithreading (Java, ..) [#pfe72ae1]
- [[Multithreading in Java: Performance and Scalability on Multicore Systems>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2010.232]], November 2011 (vol. 60 no. 11), IEEE Transaction on Computer,
pp. 1521-1534
----
*TOPPERS RTOS [#nf648456]
- TOPPERS: [[TOPPERS-Pro, the First Commercial Real-Time Operating System for Altera Nios II Multiprocessor Designs>http://www.altera.com/corporate/news_room/releases/releases_archive/2007/products/nr-toppersai.html]], 2007.
-[[Real-Time Operating Systems for Multicore Embedded Systems>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=RTOS_Multicore_ES.pdf&refer=Internal%2FMULTICORE]], IEEE 2008.
- Hiroaki Takada, [[Introduction to the TOPPERS Project Open Source RTOS for Embedded systems>http://www.computer.org/portal/web/csdl/abs/proceedings/isorc/2003/1928/00/19280044abs.htm]], Proceedings of the Sixth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'03) , pp. 44 – 45, 2003.
- [[Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device>http://www.design-reuse.com/articles/24254/inter-processor-communication-multi-core-processors-reconfigurable-device.html]].
----
*Multicore DSP [#f26c7fb6]
- "[[Trends in Multi-core DSP Platforms>http://users.ece.utexas.edu/~bevans/papers/2009/multicore/MulticoreDSPsForIEEESPMFinal.pdf]]". IEEE Signal Processing Magazine, Special Issue on Signal Processing on Platforms with Multiple Cores, 2009.
- [[Multiprocessor System-on-Chip (MPSoC)
Technology>http://www.ece.mtu.edu/~zhuofeng/EE5970Spring2011_files/Multiprocessor%20System-on-Chip%20(MPSoC)%20Technology.pdf]], IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008
***Task Hraph [#b29c5da9]
-[[Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2011.153]], IEEE Transaction on Computer, 2012.
***Sorting Algorithm on Multicore [#q3f3d91b]
-[[Efficient Implementation of Sorting on MultiCore SIMD CPU Architecture>http://www.vldb.org/pvldb/1/1454171.pdf]], PVLDB '08, August 23-28, 2008, Auckland, New Zealan.
----
*Miroprocessor [#wb4d7cc7]
-[[Vishwani D. Agrawal Talkss>http://www.eng.auburn.edu/~agrawvd/TALKS/talks.html]]
-[[TOR M. AAMODT, Canada>http://www.ece.ubc.ca/~aamodt/research.html]]
----
*Multicore Resourec allocation/Mapping [#x5945426]
-[[RESOURCE MANAGEMENT IN SINGLE-CHIP MULTIPROCESSORS>http://cva.stanford.edu/publications/2005/thesis_kashaw.pdf]], Ph.D. thesis, 2005.
--[[more publications from Stanford Univ.>http://cva.stanford.edu/publications/]]
*Companies [#l392cb01]
-[[iwaves>http://www.iwavesystems.com/]],iWave Systems is a Technology oriented organization specialized in Embedded Hardware and Software Turnkey Design ...
*People Wokring on Power Reduction [#o4f62966]
-UEC - [[Kondo>http://www.hpc.is.uec.ac.jp/kondo/]]
--[[Kondo all Publications>http://aslweb.u-aizu.ac.jp/benlab/index.php?Kondo-Publications]]
---Hiroshi Sasaki, Masaaki Kondo, and Hiroshi Nakamura, "[[Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4814485&tag=1]]", IEEE Transactions on VLSI, Vol.17 Issue 6, pp. 848-852, June 2009. (Transactions Briefs)
----
-Florida Univ. - [[Roy>http://www.cse.usf.edu/~sroy/]]
--[[Roy all Publications>http://aslweb.u-aizu.ac.jp/benlab/index.php?Roy-publications]]
---[[State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores>http://www.computer.org/portal/web/csdl/doi/10.1109/TC.2010.249]], IEEE Transaction on computer, Nov. 2011. [[references>http://aslweb.u-aizu.ac.jp/benlab/index.php?state-retentive-references]]
---S. Roy, N. Ranganathan, S. Katkoori, "A Framework for Power Gating Functional Units in Embedded Microprocessors", IEEE Transactions on Very Large Scale Integrated Systems, Volume 17, Issue 11, November 2009, Page(s):1640-1649
----
University of Virginia
-[[Kevin Skadron >http://www.cs.virginia.edu/~skadron/]]
-[[Distributed Systems>http://net.pku.edu.cn/~course/cs501/2012/schedule.html]]
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