Yuji Murakami
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開始行:
[[Members-Internal]]
CENTER:SIZE(60){COLOR(green){Design of a Light-Weight Control Network for High-Bandwidth Photonic Network-on-Chip Systems}}
*Members [#e7c49bd7]
Leader: B4 Yuji Murakami
*Background [#g8f54de8]
(1) Project Motivation
The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth, and low latency. Also, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems can accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NoC).
(2) Problem Statement
PHENIC system was proposed in our Laboratory and evaluated only in software. Some attempts to design a single control router was also performed. However, no complete hardware for the photonic network or its control network was performed in the past. To understand the real hardware complexity (area) and the performance (speed, power) and the feasibility of photonic NoCs, a complete hardware design of the system is needed.
CENTER:&ref(PHENIC-CONTROL.jpg,,80%);
*Research Goal [#p493636b]
-(1) ''Define the architecture of the control network layer (Refer to Saito's control router (GT 2015))''.
-(2) ''Design a 2x2 control network layer for [[PHENIC System>http://aslweb.u-aizu.ac.jp/aslint/index.php?PHENIC]]''.
-(3) ''Evaluate the complexity (area) and the performance (speed, and power) of a small 2x2 control layer/network to prove the concept''.
*Important References [#a7a457c0]
-Y. Tanaka, [[Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, 2015>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/YukiTanaka-TR2015.pdf]] 高性能の 3D ネットワークオンチップ(3D-NoC は)将来の多くのコアシ
ステムのための実行可能なソリューションとなっている。シリコン貫通ビア...
-Saito, Ken, [[Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/KenSaito-BS-16/KenSaito-BS-16-gt.pdf]], Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016. [[GT2015-Slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/KenSaito-BS-16/KenSaito-BS-16-slides.pdf]],
-[[OASIS 3D Router Design Tutorial with Design Compiler >http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]].
-[[PEHNIC Project>http://adaptive.u-aizu.ac.jp/aslint/index.php?PHENIC]]
終了行:
[[Members-Internal]]
CENTER:SIZE(60){COLOR(green){Design of a Light-Weight Control Network for High-Bandwidth Photonic Network-on-Chip Systems}}
*Members [#e7c49bd7]
Leader: B4 Yuji Murakami
*Background [#g8f54de8]
(1) Project Motivation
The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth, and low latency. Also, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems can accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NoC).
(2) Problem Statement
PHENIC system was proposed in our Laboratory and evaluated only in software. Some attempts to design a single control router was also performed. However, no complete hardware for the photonic network or its control network was performed in the past. To understand the real hardware complexity (area) and the performance (speed, power) and the feasibility of photonic NoCs, a complete hardware design of the system is needed.
CENTER:&ref(PHENIC-CONTROL.jpg,,80%);
*Research Goal [#p493636b]
-(1) ''Define the architecture of the control network layer (Refer to Saito's control router (GT 2015))''.
-(2) ''Design a 2x2 control network layer for [[PHENIC System>http://aslweb.u-aizu.ac.jp/aslint/index.php?PHENIC]]''.
-(3) ''Evaluate the complexity (area) and the performance (speed, and power) of a small 2x2 control layer/network to prove the concept''.
*Important References [#a7a457c0]
-Y. Tanaka, [[Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, 2015>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/YukiTanaka-TR2015.pdf]] 高性能の 3D ネットワークオンチップ(3D-NoC は)将来の多くのコアシ
ステムのための実行可能なソリューションとなっている。シリコン貫通ビア...
-Saito, Ken, [[Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/KenSaito-BS-16/KenSaito-BS-16-gt.pdf]], Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016. [[GT2015-Slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/KenSaito-BS-16/KenSaito-BS-16-slides.pdf]],
-[[OASIS 3D Router Design Tutorial with Design Compiler >http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]].
-[[PEHNIC Project>http://adaptive.u-aizu.ac.jp/aslint/index.php?PHENIC]]
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