Verilog Guideline
をテンプレートにして作成
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開始行:
[[NASH FPGA Prototyping]]
Website to learning writing Verilog source code
- http://www.asic-world.com/
Some problems that should be carefully understand:
[[Verilog tidbits>http://www.asic-world.com/tidbits/index.html]]
- [[Reg vs Wire>http://www.asic-world.com/tidbits/wire_reg.html]]: not all reg variable of Verilog create a real register after synthesis
- [[block vs non-blocking>http://www.asic-world.com/tidbits/blocking.html]]
- [[reset issue>http://www.asic-world.com/tidbits/all_reset.html]]
[[Sunburst design>http://www.sunburst-design.com/papers/]]
- [[reset issue>http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf]]
- [[full and parallel case>http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf]]
Some bugs on EDAS could be found here:
- http://www.deepchip.com/esnug.html
終了行:
[[NASH FPGA Prototyping]]
Website to learning writing Verilog source code
- http://www.asic-world.com/
Some problems that should be carefully understand:
[[Verilog tidbits>http://www.asic-world.com/tidbits/index.html]]
- [[Reg vs Wire>http://www.asic-world.com/tidbits/wire_reg.html]]: not all reg variable of Verilog create a real register after synthesis
- [[block vs non-blocking>http://www.asic-world.com/tidbits/blocking.html]]
- [[reset issue>http://www.asic-world.com/tidbits/all_reset.html]]
[[Sunburst design>http://www.sunburst-design.com/papers/]]
- [[reset issue>http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf]]
- [[full and parallel case>http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf]]
Some bugs on EDAS could be found here:
- http://www.deepchip.com/esnug.html
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