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開始行:
CENTER:SIZE(50){COLOR(green){VDEC & other Tools}}
***CADENCE Design Tutorials [#h5437ce7]
-[[Local VLSI CAD Design Tutorials >http://aslweb.u-aizu.ac.jp/benlab/index.php?CADENCE%20Tutorials]]
- [[RTL Compiler & First Encounter Tutorial >http://cecs.wright.edu/~emmert/tutorials/]]
- [[Digital VLSI Chip Design with Cadence and Synopsys CAD Tools (Book)>http://www.cs.utah.edu/~elb/cadbook/]], [[Zip>http://aslweb.u-aizu.ac.jp/~m5151161/zxw001/Lab_Docs/VLSI_CAD_Book.zip]]
***VDEC - VLSI Design and Education Center ([[Jump to VDEC Web Site>http://www.vdec.u-tokyo.ac.jp/welcome.html]]) [#e4cf5116]
-Go to [[''this site''>http://www.vdec.u-tokyo.ac.jp/PROTcgi/cad_license.cgi]] to download VLSI Design tools. (user name and pass required)
***VDEC Supported OS (Downloaded from VDEC site on Oct. 14, 2011) [#j5d388e2]
|&ref(encounter.gif,,80%);|&ref(f2.gif,,80%);|
-Cadence_Platform_Support_Plan ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/Cadence_Platform_Support_Plan.pdf]])
-Cadence_Support ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/Cadence_Support.pdf]])
-IC61move (IC613移行の注意点) ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/IC61move.pdf]])
-[[Layout Tutorial>http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial2]] Extraction and LVS
--[[Other CAD tutorials>http://www.eda.ncsu.edu/wiki/Tutorial:Contents]]
----
-VDEC VLSI Design tools Literature
--橘, 昌良, [[LSI開発、設計教育、及び、システム技術研究>http://www.google.co.jp/url?sa=t&source=web&cd=5&ved=0CD4QFjAE&url=http%3A%2F%2Fkutarr.lib.kochi-tech.ac.jp%2Fdspace%2Fbitstream%2F10173%2F144%2F1%2F120-124.pdf&ei=GP2UTtKnDYXsmAXjsonxBg&usg=AFQjCNFO3LHRhI71QYn7vPbnzSb1_9QFOA&sig2=QRA-lNj0gE8HZIStr6k-5A]]
//-- [[Designing with VDEC VLSI Tools>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=VDEC.pdf&refer=Internal%2FResources]]
//--[[VLS Course>http://sharif.ir/~hessabi/VLSI/]]
Basic Design Tools:
--Coding - Tool: Verilog HDL
-- Logic Synthesis - Tool:[[Design Compiler>http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/design_compiler/gsdc.html]] (from Synopsys)
-- Timing Siumlation - Tool: Verilog-XL, [[NC-Verilog>http://www.ee.virginia.edu/~mrs8n/soc/sim_tutorial.html]]
-- Place and Route - Tool: [[SoC Encounter>http://www.ee.virginia.edu/~mrs8n/soc/enc_tutorial.html]] (from Cadence).
---Reference: [[placement and routing>http://sharif.ir/~hessabi/VLSI/CHAP7-1.pdf]]; [[Layout,Simulation 1>http://sharif.ir/~hessabi/VLSI/CHAP4-1.pdf]]
-[[HSPICE>http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx]] SPICE simulation is industry-standard for verification of circuit operation at transistor level before manufacturing
--[[Synopsys Power Compiler>http://www.synopsys.com/tools/implementation/rtlsynthesis/pages/powercompiler.aspx]]
---Power Compiler™ automatically minimizes power consumption at the RTL and gate level. Power Compiler performs automatic clock gating to reduce the power consumption. Driven by the design constraints, it performs simultaneous optimization for timing, power and area. With power intent defined by UPF (Unified Power Intent), it automatically inserts power management cells such as isolation, level-shifter, retention registers, power gates and always-on cells as needed. It also supports multi-threshold libraries for optimal leakage power optimization. Power Compiler is seamlessly integrated with the synthesis design flow and shares the same GUI, commands, constraints and libraries with the Design Compiler® and IC Compiler® tools.
-RTqualify from [[HDLab>http://www.hdlab.co.jp/web/x030english/]] for quality checker of the HDL source code.
WWW VLSI Educational services:
-Japan: [[VDEC>http://www.vdec.u-tokyo.ac.jp/welcome.html]]
-U.S.: [[MOSIS>http://www.mosis.com/]]
--[[Cadence Tutorials from the University of Virginia>http://www.ee.virginia.edu/~mrs8n/cadence/Cadencetutorials.html]]
-EC: [[EuroPractice>http://www.europractice-ic.com/]]
-Taiwan: [[CIC>http://www.cic.edu.tw/cic_v13/english/]]
*Matrix computation on CPUs and GPUs libraries [#s62ede65]
-[[Intel Math Kernel Library>http://software.intel.com/en-us/articles/intel-mkl-link-line-advisor/]]
-[[CUDA CUBLAS Library2.0>http://developer.download.nvidia.com/compute/cuda/2_0/docs/CUBLAS_Library_2.0.pdf]]
---
**Simulators [#nff4d163]
-[[M5 multicore simulator>http://www.m5sim.org/Main_Page]]
-- N.L. Binkert et al., “[[The M5 Simulator: Modeling Networked Systems>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1677503&tag=1]],” IEEE Micro, vol. 26, no. 4, pp. 52-60, July/Aug. 2006.
-- [[The GEM5 simulator>http://research.cs.wisc.edu/multifacet/papers/can11_gem5.pdf]]
----
-[[GPGPU-Sim>http://www.ece.ubc.ca/~aamodt/gpgpu-sim/]]
-Off-Chip/On-Chip Network Simulator [[ns-2>http://www.isi.edu/nsnam/ns/]]
- Random Task Graph Generator [[TGFF>http://ziyang.eecs.umich.edu/~dickrp/tgff/]], [[Read Manual>http://ziyang.eecs.umich.edu/~dickrp/tgff/manual.pdf]]
-Super-scalar Microprocessor Simulator [[SimpleScalar>http://www.simplescalar.com/]]
-[[HotSpot>http://lava.cs.virginia.edu/HotSpot/]]
-[[TOP500 Supercomputer Sites webpage>http://www.top500.org/]]
***Cell BE [#wcbaab17]
-Cellsim: [[Cell Simulator>http://swarm.cs.virginia.edu/cellsim/]] (source code available)
--[[UNISIM>http://unisim.org/site/]]
--[[Barcelona Supercomputer Center>http://www.bsc.es/plantillaH.php?cat_id=326]]
--[[Synergistic Processor Unit - Instruction Set Architecture - Version 1.2, 2007>http://www.bsc.es/plantillaH.php?cat_id=326]]
-IBM Blade Server: [[Cell Broadband Engine resource center>http://www.ibm.com/developerworks/power/cell/downloads.html]]
-[[IBM cellsystemsim>http://www.alphaworks.ibm.com/tech/cellsystemsim/download]]
(only executable)
***Libraries [#l1431589]
-QSpace - Queen's University Library
--[[Design and Evaluation of Efficient Collective Communications on Modern Interconnects and Multi-core Clusters>http://qspace.library.queensu.ca/bitstream/1974/5383/1/Qian_Ying_201001_PHD.pdf]],Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2010-01-10.
--[[A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays>http://qspace.library.queensu.ca/bitstream/1974/1516/1/Pau_Ronny_P_200809_MSc.pdf]], Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-24.
*** CPU Design [#b0c99357]
-Floorplan:
-- [[Analyzing and Optimizing the Design Floorplan in Quartus II>http://www.altera.com/literature/hb/qts/qts_qii52006.pdf]]
--[[Design Analysis & Engineering Change Management with Chip Planner >http://www.altera.com/literature/hb/qts/qts_qii53010.pdf]]
***Major FPGA Vendors [#wda2e15f]
-[[Xilinx>http://www.xilinx.com]]
-[[Altera>http://www.altera.com]]
-Mentor Graphics
-Synplicity
-Cadence
These vendors not only provide FPGA
boards but Electronic Design Automation tools so that designers can
make best use of these FPGAs. These tools can be used for designing, simulation,
placement, routing , synthesis and verification. These vendors also
provide libraries of reference designs and Intellectual Properties (IPs).
**Verilog [#b089478b]
-[[Verilog source>http://www.eehomepage.com/query.php?Find=Verilog&sortName=Type]]
**STANDARS [#dfa18701]
-Unified Power Format
--http://www.accellera.org
-- IEEE 1801-2009 – Unified Power Format (UPF)
**List of system-on-a-chip suppliers [#e487f4e0]
-[[SoC List>http://en.wikipedia.org/wiki/List_of_system-on-a-chip_suppliers]]
- Matrix Transpose http://www.programmingsimplified.com/c-program-transpose-matrix
*Fabrication Process [#qf8ddc16]
-VLSI Design Lectures http://www.coe.montana.edu/ee/andyo/EELE414/#JMP_Handouts
*Air Pollution Monitor [#va6b24d5]
*Links [#p651a726]
- http://www.computerhope.com/issues/ch001002.htm
http://aqicn.org/map/
終了行:
CENTER:SIZE(50){COLOR(green){VDEC & other Tools}}
***CADENCE Design Tutorials [#h5437ce7]
-[[Local VLSI CAD Design Tutorials >http://aslweb.u-aizu.ac.jp/benlab/index.php?CADENCE%20Tutorials]]
- [[RTL Compiler & First Encounter Tutorial >http://cecs.wright.edu/~emmert/tutorials/]]
- [[Digital VLSI Chip Design with Cadence and Synopsys CAD Tools (Book)>http://www.cs.utah.edu/~elb/cadbook/]], [[Zip>http://aslweb.u-aizu.ac.jp/~m5151161/zxw001/Lab_Docs/VLSI_CAD_Book.zip]]
***VDEC - VLSI Design and Education Center ([[Jump to VDEC Web Site>http://www.vdec.u-tokyo.ac.jp/welcome.html]]) [#e4cf5116]
-Go to [[''this site''>http://www.vdec.u-tokyo.ac.jp/PROTcgi/cad_license.cgi]] to download VLSI Design tools. (user name and pass required)
***VDEC Supported OS (Downloaded from VDEC site on Oct. 14, 2011) [#j5d388e2]
|&ref(encounter.gif,,80%);|&ref(f2.gif,,80%);|
-Cadence_Platform_Support_Plan ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/Cadence_Platform_Support_Plan.pdf]])
-Cadence_Support ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/Cadence_Support.pdf]])
-IC61move (IC613移行の注意点) ([[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/VDEC/IC61move.pdf]])
-[[Layout Tutorial>http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial2]] Extraction and LVS
--[[Other CAD tutorials>http://www.eda.ncsu.edu/wiki/Tutorial:Contents]]
----
-VDEC VLSI Design tools Literature
--橘, 昌良, [[LSI開発、設計教育、及び、システム技術研究>http://www.google.co.jp/url?sa=t&source=web&cd=5&ved=0CD4QFjAE&url=http%3A%2F%2Fkutarr.lib.kochi-tech.ac.jp%2Fdspace%2Fbitstream%2F10173%2F144%2F1%2F120-124.pdf&ei=GP2UTtKnDYXsmAXjsonxBg&usg=AFQjCNFO3LHRhI71QYn7vPbnzSb1_9QFOA&sig2=QRA-lNj0gE8HZIStr6k-5A]]
//-- [[Designing with VDEC VLSI Tools>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=VDEC.pdf&refer=Internal%2FResources]]
//--[[VLS Course>http://sharif.ir/~hessabi/VLSI/]]
Basic Design Tools:
--Coding - Tool: Verilog HDL
-- Logic Synthesis - Tool:[[Design Compiler>http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/design_compiler/gsdc.html]] (from Synopsys)
-- Timing Siumlation - Tool: Verilog-XL, [[NC-Verilog>http://www.ee.virginia.edu/~mrs8n/soc/sim_tutorial.html]]
-- Place and Route - Tool: [[SoC Encounter>http://www.ee.virginia.edu/~mrs8n/soc/enc_tutorial.html]] (from Cadence).
---Reference: [[placement and routing>http://sharif.ir/~hessabi/VLSI/CHAP7-1.pdf]]; [[Layout,Simulation 1>http://sharif.ir/~hessabi/VLSI/CHAP4-1.pdf]]
-[[HSPICE>http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx]] SPICE simulation is industry-standard for verification of circuit operation at transistor level before manufacturing
--[[Synopsys Power Compiler>http://www.synopsys.com/tools/implementation/rtlsynthesis/pages/powercompiler.aspx]]
---Power Compiler™ automatically minimizes power consumption at the RTL and gate level. Power Compiler performs automatic clock gating to reduce the power consumption. Driven by the design constraints, it performs simultaneous optimization for timing, power and area. With power intent defined by UPF (Unified Power Intent), it automatically inserts power management cells such as isolation, level-shifter, retention registers, power gates and always-on cells as needed. It also supports multi-threshold libraries for optimal leakage power optimization. Power Compiler is seamlessly integrated with the synthesis design flow and shares the same GUI, commands, constraints and libraries with the Design Compiler® and IC Compiler® tools.
-RTqualify from [[HDLab>http://www.hdlab.co.jp/web/x030english/]] for quality checker of the HDL source code.
WWW VLSI Educational services:
-Japan: [[VDEC>http://www.vdec.u-tokyo.ac.jp/welcome.html]]
-U.S.: [[MOSIS>http://www.mosis.com/]]
--[[Cadence Tutorials from the University of Virginia>http://www.ee.virginia.edu/~mrs8n/cadence/Cadencetutorials.html]]
-EC: [[EuroPractice>http://www.europractice-ic.com/]]
-Taiwan: [[CIC>http://www.cic.edu.tw/cic_v13/english/]]
*Matrix computation on CPUs and GPUs libraries [#s62ede65]
-[[Intel Math Kernel Library>http://software.intel.com/en-us/articles/intel-mkl-link-line-advisor/]]
-[[CUDA CUBLAS Library2.0>http://developer.download.nvidia.com/compute/cuda/2_0/docs/CUBLAS_Library_2.0.pdf]]
---
**Simulators [#nff4d163]
-[[M5 multicore simulator>http://www.m5sim.org/Main_Page]]
-- N.L. Binkert et al., “[[The M5 Simulator: Modeling Networked Systems>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1677503&tag=1]],” IEEE Micro, vol. 26, no. 4, pp. 52-60, July/Aug. 2006.
-- [[The GEM5 simulator>http://research.cs.wisc.edu/multifacet/papers/can11_gem5.pdf]]
----
-[[GPGPU-Sim>http://www.ece.ubc.ca/~aamodt/gpgpu-sim/]]
-Off-Chip/On-Chip Network Simulator [[ns-2>http://www.isi.edu/nsnam/ns/]]
- Random Task Graph Generator [[TGFF>http://ziyang.eecs.umich.edu/~dickrp/tgff/]], [[Read Manual>http://ziyang.eecs.umich.edu/~dickrp/tgff/manual.pdf]]
-Super-scalar Microprocessor Simulator [[SimpleScalar>http://www.simplescalar.com/]]
-[[HotSpot>http://lava.cs.virginia.edu/HotSpot/]]
-[[TOP500 Supercomputer Sites webpage>http://www.top500.org/]]
***Cell BE [#wcbaab17]
-Cellsim: [[Cell Simulator>http://swarm.cs.virginia.edu/cellsim/]] (source code available)
--[[UNISIM>http://unisim.org/site/]]
--[[Barcelona Supercomputer Center>http://www.bsc.es/plantillaH.php?cat_id=326]]
--[[Synergistic Processor Unit - Instruction Set Architecture - Version 1.2, 2007>http://www.bsc.es/plantillaH.php?cat_id=326]]
-IBM Blade Server: [[Cell Broadband Engine resource center>http://www.ibm.com/developerworks/power/cell/downloads.html]]
-[[IBM cellsystemsim>http://www.alphaworks.ibm.com/tech/cellsystemsim/download]]
(only executable)
***Libraries [#l1431589]
-QSpace - Queen's University Library
--[[Design and Evaluation of Efficient Collective Communications on Modern Interconnects and Multi-core Clusters>http://qspace.library.queensu.ca/bitstream/1974/5383/1/Qian_Ying_201001_PHD.pdf]],Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2010-01-10.
--[[A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays>http://qspace.library.queensu.ca/bitstream/1974/1516/1/Pau_Ronny_P_200809_MSc.pdf]], Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-24.
*** CPU Design [#b0c99357]
-Floorplan:
-- [[Analyzing and Optimizing the Design Floorplan in Quartus II>http://www.altera.com/literature/hb/qts/qts_qii52006.pdf]]
--[[Design Analysis & Engineering Change Management with Chip Planner >http://www.altera.com/literature/hb/qts/qts_qii53010.pdf]]
***Major FPGA Vendors [#wda2e15f]
-[[Xilinx>http://www.xilinx.com]]
-[[Altera>http://www.altera.com]]
-Mentor Graphics
-Synplicity
-Cadence
These vendors not only provide FPGA
boards but Electronic Design Automation tools so that designers can
make best use of these FPGAs. These tools can be used for designing, simulation,
placement, routing , synthesis and verification. These vendors also
provide libraries of reference designs and Intellectual Properties (IPs).
**Verilog [#b089478b]
-[[Verilog source>http://www.eehomepage.com/query.php?Find=Verilog&sortName=Type]]
**STANDARS [#dfa18701]
-Unified Power Format
--http://www.accellera.org
-- IEEE 1801-2009 – Unified Power Format (UPF)
**List of system-on-a-chip suppliers [#e487f4e0]
-[[SoC List>http://en.wikipedia.org/wiki/List_of_system-on-a-chip_suppliers]]
- Matrix Transpose http://www.programmingsimplified.com/c-program-transpose-matrix
*Fabrication Process [#qf8ddc16]
-VLSI Design Lectures http://www.coe.montana.edu/ee/andyo/EELE414/#JMP_Handouts
*Air Pollution Monitor [#va6b24d5]
*Links [#p651a726]
- http://www.computerhope.com/issues/ch001002.htm
http://aqicn.org/map/
ページ名: