Takaya Hirai
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開始行:
CENTER:SIZE(60){COLOR(green){Design and Evaluation of a Low-Complexity Router for 3D Network-on-Chip Systems}}
// Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV) }}
//CENTER:&ref(pipeline.jpg,,13%);
//CENTER:COLOR(green){Fig. 1 3D-OASIS-NoC system architecture}
-[[Members-Internal]]
--ID: s1200022
*Background (Problem Definition) [#vd19864b]
During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research includes a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://adaptive.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
*Research goal[#mec7d6fe]
The main goals of this research are:
-1. Study OASIS 3D Router Architecture
//-2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)
//-3. Verify the correctness at each step using ModelSim
-2. Evaluate the performance of the final 3D Router (Area, Power, and Speed)
-3. Write a thesis
***Design & Simulation Approach [#ha8f0177]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,50%);
CENTER:COLOR(green){Fig.1 Design & Simulation Approach }
*Research Plan [#ta63de42]
***Step 1 [#o8e20cc0]
-Understand the following:
--Yuuki Tanaka, COLOR(blue){Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System}, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015.
---[[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YukiTanaka_slides_Final.pdf]],
---[[technicalReport.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/YukiTanaka-TR2015.pdf]]
Option:
---What is OASIS NoC? [[Slides 1>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_slides.pdf]]; [[Slides 2>http://web-ext.u-aizu.ac.jp/~benab/classes/aco/lectures/noc-invited/invited_05_6_2014.pdf]]
---[[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YuukiTanaka_Final.pdf]],
***Step 2 [#la297c28]
-Understand [[OASIS 3D-Router Verliog HDL Source Code>http://adaptive.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
- Run on your machine these 2 tutorials (COLOR(blue){IN ORDER}):
--[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.}
-COLOR(blue){How to Login and use VDEC tools on zxp035?} --> [[Go to this page>http://adaptive.u-aizu.ac.jp/aslint/index.php?VLSI-Design#k5253b6c]]
*References[#jec7d6fe]
-[[前論文テーマ (Previous GT)>http://adaptive.u-aizu.ac.jp/aslint/index.php?Theses]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://adaptive.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
----
Updates:
終了行:
CENTER:SIZE(60){COLOR(green){Design and Evaluation of a Low-Complexity Router for 3D Network-on-Chip Systems}}
// Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV) }}
//CENTER:&ref(pipeline.jpg,,13%);
//CENTER:COLOR(green){Fig. 1 3D-OASIS-NoC system architecture}
-[[Members-Internal]]
--ID: s1200022
*Background (Problem Definition) [#vd19864b]
During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research includes a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://adaptive.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
*Research goal[#mec7d6fe]
The main goals of this research are:
-1. Study OASIS 3D Router Architecture
//-2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)
//-3. Verify the correctness at each step using ModelSim
-2. Evaluate the performance of the final 3D Router (Area, Power, and Speed)
-3. Write a thesis
***Design & Simulation Approach [#ha8f0177]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,50%);
CENTER:COLOR(green){Fig.1 Design & Simulation Approach }
*Research Plan [#ta63de42]
***Step 1 [#o8e20cc0]
-Understand the following:
--Yuuki Tanaka, COLOR(blue){Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System}, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015.
---[[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YukiTanaka_slides_Final.pdf]],
---[[technicalReport.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/YukiTanaka-TR2015.pdf]]
Option:
---What is OASIS NoC? [[Slides 1>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_slides.pdf]]; [[Slides 2>http://web-ext.u-aizu.ac.jp/~benab/classes/aco/lectures/noc-invited/invited_05_6_2014.pdf]]
---[[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YuukiTanaka_Final.pdf]],
***Step 2 [#la297c28]
-Understand [[OASIS 3D-Router Verliog HDL Source Code>http://adaptive.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
- Run on your machine these 2 tutorials (COLOR(blue){IN ORDER}):
--[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.}
-COLOR(blue){How to Login and use VDEC tools on zxp035?} --> [[Go to this page>http://adaptive.u-aizu.ac.jp/aslint/index.php?VLSI-Design#k5253b6c]]
*References[#jec7d6fe]
-[[前論文テーマ (Previous GT)>http://adaptive.u-aizu.ac.jp/aslint/index.php?Theses]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://adaptive.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
----
Updates:
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