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開始行:
CENTER:SIZE(40){COLOR(green){SEA: Self-adaptive Architecture}}
1. ''Goal:'' This research is about a novel architecture which provides the flexibility to dynamically synthesize the right hardware composition based on software demands. We are investigating self-adaptive architecture which evaluates its own global behavior and change it when better functionality or performance is possible. A challenge is often to identify how to change specific behaviors to achieve the desired improvement.
CENTER:&ref(SEA.gif,,80%);
CENTER:SEA Design Space
//[[Public Page>http://web-ext.u-aizu.ac.jp/~benab/research/projects/sea/]]
2. ''Members:''
- Maekawa. (Graduated) [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Maekawa-MS-10/m5131144_Maekawa_MS_thesis.pdf]], Feb. 2011.
3. '' Related Publications''
- Mushiq Akanda, A. Ben Abdallah, and M. Sowa, [[Dual-Execution Mode Processor Architecture for Embedded Applications>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super07/ABS_journal2007.pdf]]", Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347-370, 2007.
- Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda, [[Single Instruction Dual-Execution Model Processor Architecture>http://aslweb.u-aizu.ac.jp/~s1130205/Conference/EUC/m5131144_EUC_article.pdf]], IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008
&ref(http://aslweb.u-aizu.ac.jp/~s1130205/Conference/EUC/m5131144_EUC_presen.ppt,,SLIDE);
-Taichi Maekawa, Abderazek Ben Abdallah and Kenichi Kuroda. Single Instruction Dual-Execution Model Processor Architecture, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008.
-Mushfiq Akanda, Abderazek Ben Abdallah, Sowa Masahiro, Dual-Execution Mode Processor Architecture, Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, On the Design of Register-Queue Based Processor Architecture (FaRM-rq), Lecture Notes in Computer Science, Springer-Verlag, vol. 2745, pp. 248-262, July 2003.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq), IPSJ SIG TR, pp. 19-23, June 2003.
-Mushifiq Akanda, Abderazek Ben Abdallah, Masahiro Sowa, Dual-Execution Mode Processor Architecture for Embedded Applications, in Journal of Mobile Multimedia, Vol. 3, No. 4, 2007, pp. 347-370.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Complexity Analysis of a Functional Assignment Register Microprocessor, Proc. of the Int. Workshop on Modern Science and Technology, IWMST02, pp.116-123, Sep. 2002.
-Abderazek Ben Abdallah, Dynamic Instructions Issue Algorithm and a Queue Execution Model Toward the Design of Hybrid Processor Architecture", Ph.D. thesis, Graduate School of Information Systems, the Univ. of Electro-Communications, March 2002.
-Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Mode: On a Practical Queue Execution Model, Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, pp.939-944, July 2001.
-Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors, IEICE transaction on Fundamental of Electronics, Communications and computer Science, Vol.E83-A No.12 pp.2417-2425, Dec, 2001
-Abderazek Ben Abdallah, Kirilka Nikolova Tutomu Yoshinaga, Masahiro Sowa, FARM Queue Mode: On a Practical Queue Execution Model (QEM),TIWSS'2001,October 2001.
-Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Execution Model: Towards an Alternative Computing Paradigm, Proceedings of IPSJ Symposium, Yokohama pp.99-100, March 2000
-Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Acyclic DFG on a Queue Machine, JSPP2000, Tokyo, Japan, pp.119-120, 2000.
-Abderazek Ben Abdallah, Mudra Sarem., Masahiro Sowa, Instruction Scheduling System for Super scalar Processors, JSPP2000, Tokyo, Japan, pp.161, Apr. 2000 .
-Abderazek Ben Abdallah, Masahiro Sowa, DRA: Dynamic Register Allocator Mechanism For FaRM Microprocessor. The 3rd International Workshop on Advanced Parallel Processing Technologies, Chansha, PRC, pp.131-136, Oct., 1999
-Ben Abdallah Abderaezk, FaRM Design philosophy, Technical Report Ref: BAAPHCH1, UEC, IS, 2002.
4. ''Poster''
--English:&ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/m5131144_EnglishPanel_2009.pdf,,PDF);
--Japanese:&ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/m5131144_JapanesePanel_2009.pdf,,PDF);
終了行:
CENTER:SIZE(40){COLOR(green){SEA: Self-adaptive Architecture}}
1. ''Goal:'' This research is about a novel architecture which provides the flexibility to dynamically synthesize the right hardware composition based on software demands. We are investigating self-adaptive architecture which evaluates its own global behavior and change it when better functionality or performance is possible. A challenge is often to identify how to change specific behaviors to achieve the desired improvement.
CENTER:&ref(SEA.gif,,80%);
CENTER:SEA Design Space
//[[Public Page>http://web-ext.u-aizu.ac.jp/~benab/research/projects/sea/]]
2. ''Members:''
- Maekawa. (Graduated) [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Maekawa-MS-10/m5131144_Maekawa_MS_thesis.pdf]], Feb. 2011.
3. '' Related Publications''
- Mushiq Akanda, A. Ben Abdallah, and M. Sowa, [[Dual-Execution Mode Processor Architecture for Embedded Applications>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super07/ABS_journal2007.pdf]]", Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347-370, 2007.
- Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda, [[Single Instruction Dual-Execution Model Processor Architecture>http://aslweb.u-aizu.ac.jp/~s1130205/Conference/EUC/m5131144_EUC_article.pdf]], IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008
&ref(http://aslweb.u-aizu.ac.jp/~s1130205/Conference/EUC/m5131144_EUC_presen.ppt,,SLIDE);
-Taichi Maekawa, Abderazek Ben Abdallah and Kenichi Kuroda. Single Instruction Dual-Execution Model Processor Architecture, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008.
-Mushfiq Akanda, Abderazek Ben Abdallah, Sowa Masahiro, Dual-Execution Mode Processor Architecture, Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, On the Design of Register-Queue Based Processor Architecture (FaRM-rq), Lecture Notes in Computer Science, Springer-Verlag, vol. 2745, pp. 248-262, July 2003.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq), IPSJ SIG TR, pp. 19-23, June 2003.
-Mushifiq Akanda, Abderazek Ben Abdallah, Masahiro Sowa, Dual-Execution Mode Processor Architecture for Embedded Applications, in Journal of Mobile Multimedia, Vol. 3, No. 4, 2007, pp. 347-370.
-Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Complexity Analysis of a Functional Assignment Register Microprocessor, Proc. of the Int. Workshop on Modern Science and Technology, IWMST02, pp.116-123, Sep. 2002.
-Abderazek Ben Abdallah, Dynamic Instructions Issue Algorithm and a Queue Execution Model Toward the Design of Hybrid Processor Architecture", Ph.D. thesis, Graduate School of Information Systems, the Univ. of Electro-Communications, March 2002.
-Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Mode: On a Practical Queue Execution Model, Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, pp.939-944, July 2001.
-Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors, IEICE transaction on Fundamental of Electronics, Communications and computer Science, Vol.E83-A No.12 pp.2417-2425, Dec, 2001
-Abderazek Ben Abdallah, Kirilka Nikolova Tutomu Yoshinaga, Masahiro Sowa, FARM Queue Mode: On a Practical Queue Execution Model (QEM),TIWSS'2001,October 2001.
-Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Execution Model: Towards an Alternative Computing Paradigm, Proceedings of IPSJ Symposium, Yokohama pp.99-100, March 2000
-Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Acyclic DFG on a Queue Machine, JSPP2000, Tokyo, Japan, pp.119-120, 2000.
-Abderazek Ben Abdallah, Mudra Sarem., Masahiro Sowa, Instruction Scheduling System for Super scalar Processors, JSPP2000, Tokyo, Japan, pp.161, Apr. 2000 .
-Abderazek Ben Abdallah, Masahiro Sowa, DRA: Dynamic Register Allocator Mechanism For FaRM Microprocessor. The 3rd International Workshop on Advanced Parallel Processing Technologies, Chansha, PRC, pp.131-136, Oct., 1999
-Ben Abdallah Abderaezk, FaRM Design philosophy, Technical Report Ref: BAAPHCH1, UEC, IS, 2002.
4. ''Poster''
--English:&ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/m5131144_EnglishPanel_2009.pdf,,PDF);
--Japanese:&ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/m5131144_JapanesePanel_2009.pdf,,PDF);
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