Ryunosuke Murakami
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[[Members-Internal]]
CENTER:SIZE(40){COLOR(blue){Implementation and Evaluation of Soft-Error Resilience for OASIS Network-on-Chip}}
----
[[OASIS-VP]]
----
*Overview [#c1ea267d]
This topic is implementation and evaluation of a soft error resilience method for 3D Network-on-Chip.
The architecture is based on 3D Network-on-Chip model which is called as OASIS. Figure 1 depicts an example of 4×2×2 3D Network-on-Chip. The router is connected with its neighbors or local core by wires. There are seven possible connections: local (PE), north, east, south, west, up, and down. For the up and down connections, we use special inter-layer links which are called as Through-Silicon-Vias (TSVs).
CENTER:&ref(3Dtop.png,,60%);
CENTER:Figure 1: 3D Network-on-Chip.
*Research Description [#b54aac9f]
There are two techniques includes in SER-OASIS:
- Error Correcting Code: using SECDED (single error correction, double error detection) code for correctting the flip bit of data.
- SER technique: adding redundant clock cycles to detect then correct the fault in NPC/SA pipeline stage.
*Expected Output [#ha4d05b6]
- Run and performance evaluate and extract the results.
- Understand the soft error resilience method for OASIS Network-on-Chip.
- Simulate error injection and performance of the Soft Error Resilience architecture.
- Compare the performance of the original OASIS and the Soft Error Resilience architecture.
*Research Schedule [#k3603c5b]
-June - September :
Understand algorithms of Error Correction Code(ECC) and OASIS architecture.
-October - January :
Simulation, Evaluation and Writing GT.
-February :
[Early] Submit a draft of GT to the GT supervisor
[Midterm] GT Presentations
*References [#le6f6e2b]
- Main reference: “Soft-Error Resilient 3D Network-on-Chip Router”; Khanh et. al; iCAST2015. [[PDF_file>http://dx.doi.org/10.1109/ICAwST.2015.7314025]]
- Other references:
-- [0] OASIS internal page: http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS
-- [1] “On the Design of a 3D Network-on-Chip for Many-core SoC”; Akram Ben Ahmed; Master Thesis 2012. [[PDF>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[Slide>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-- [2] “Soft-Error Resilient 3D Network-on-Chip Router”; Khanh et. al; iCAST2015. [[PDF>http://dx.doi.org/10.1109/ICAwST.2015.7314025]]
-- [3] “Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”; Khanh et. al; ICICDT2016.
-- [4] “Benchmark suite for OASIS NoC”; [[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]]
-- [5] Source code: soft-ft.zip: soft error router; baseline-hlaft: OASIS router, tb.zip: Testbench files
- Other Documents: [[Link>https://drive.google.com/file/d/0B1g5BRAzi1DaVW1yOGJYVXJ1b2s/view?usp=sharing]], [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
終了行:
[[Members-Internal]]
CENTER:SIZE(40){COLOR(blue){Implementation and Evaluation of Soft-Error Resilience for OASIS Network-on-Chip}}
----
[[OASIS-VP]]
----
*Overview [#c1ea267d]
This topic is implementation and evaluation of a soft error resilience method for 3D Network-on-Chip.
The architecture is based on 3D Network-on-Chip model which is called as OASIS. Figure 1 depicts an example of 4×2×2 3D Network-on-Chip. The router is connected with its neighbors or local core by wires. There are seven possible connections: local (PE), north, east, south, west, up, and down. For the up and down connections, we use special inter-layer links which are called as Through-Silicon-Vias (TSVs).
CENTER:&ref(3Dtop.png,,60%);
CENTER:Figure 1: 3D Network-on-Chip.
*Research Description [#b54aac9f]
There are two techniques includes in SER-OASIS:
- Error Correcting Code: using SECDED (single error correction, double error detection) code for correctting the flip bit of data.
- SER technique: adding redundant clock cycles to detect then correct the fault in NPC/SA pipeline stage.
*Expected Output [#ha4d05b6]
- Run and performance evaluate and extract the results.
- Understand the soft error resilience method for OASIS Network-on-Chip.
- Simulate error injection and performance of the Soft Error Resilience architecture.
- Compare the performance of the original OASIS and the Soft Error Resilience architecture.
*Research Schedule [#k3603c5b]
-June - September :
Understand algorithms of Error Correction Code(ECC) and OASIS architecture.
-October - January :
Simulation, Evaluation and Writing GT.
-February :
[Early] Submit a draft of GT to the GT supervisor
[Midterm] GT Presentations
*References [#le6f6e2b]
- Main reference: “Soft-Error Resilient 3D Network-on-Chip Router”; Khanh et. al; iCAST2015. [[PDF_file>http://dx.doi.org/10.1109/ICAwST.2015.7314025]]
- Other references:
-- [0] OASIS internal page: http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS
-- [1] “On the Design of a 3D Network-on-Chip for Many-core SoC”; Akram Ben Ahmed; Master Thesis 2012. [[PDF>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[Slide>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-- [2] “Soft-Error Resilient 3D Network-on-Chip Router”; Khanh et. al; iCAST2015. [[PDF>http://dx.doi.org/10.1109/ICAwST.2015.7314025]]
-- [3] “Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”; Khanh et. al; ICICDT2016.
-- [4] “Benchmark suite for OASIS NoC”; [[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]]
-- [5] Source code: soft-ft.zip: soft error router; baseline-hlaft: OASIS router, tb.zip: Testbench files
- Other Documents: [[Link>https://drive.google.com/file/d/0B1g5BRAzi1DaVW1yOGJYVXJ1b2s/view?usp=sharing]], [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
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