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開始行:
[[ASL Wiki]]
[[Research]]
#CONTENTS
* Adaptive and Self-Organizing Systems/Systems-on-Chip [#ucd31e2a]
// for IoT and Biomedical Computing [#of1c6ec1]
***Adaptive Neuro-inspired Processor [#ube5191d]
The biological brain implements massively parallel computations using a complex architecture that is different from the conventional Von Neumann computing style. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Our goal in this project is to research and develop an adaptive and reliable neuro-inspired manycore system with on-chip learning and cognitive capabilities targeted for pattern recognition and complex cognitive tasks. Our other goal is to investigate and develop a low-power and low-cost platform for running large-scale simulations of biological brains in real-time targeted for neuroscience applications. Currently, we are investigating the following problems: the communication network for neuro-inspired chips, reconfigurability and adaptability methods, fault-tolerance, and learning circuits. In addition to these two target applications, lessons learned from this project will be also investigated to optimize power & performance of the conventional computing architectures.
CENTER:[[&ref(ANPU.png,,80%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#xc59e614]]
***Reliable Real-time Image Processing Multicore NoC System [#y3cd6bad]
With the advance in microprocessor technology, demands for practical vision systems have been appearing in security, surveillance, and robot applications. Typical vision processing cycle includes:(1)sense → (2) process → (3) analyze → (4) make a decision. Processing vision or object recognition algorithms, such as SIFT, requires huge computing power and data transactions among tasks, especially in applications where high frame-rate is essential. In addition, having a real-time decision also requires low latency from the system, which makes the analysis of the large input data (images or videos) set even more complicated. For this reason, an efficient and reliable Many-core architecture for communication and computation are needed for high-performance vision tasks.
The main goal of this project is to research about a Reliable Many-core architecture for low-level image processing in real-time, which solves several problems found in existing approaches. The novel system is based on our earlier developed reliable Network-on-Chip (OASIS). It will integrate several dedicated PEs for ILP/Data/Thread level parallelism while the 3D-OASIS NoC orchestrates communications between PEs and is used for a large amount of data transactions among tasks.
//COLOR(Green){Related Projects}
//-[[OASIS-VP1>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP]] (internal)
***Dependable Real-Time Multicore System-on-Chip for Elderly Health Monitoring [#pebd3cd2]
Recent technological advances in wireless networking, microelectronics and the Internet allow us to fundamentally change the way elderly health care services are practiced. Traditionally, embedded personal medical monitoring systems have been used only to collect data. Data processing and analysis are performed off-line, making such devices impractical for continual monitoring and early detection of medical disorders. The goal of this project is to research about smart in-body embedded system to monitor elderly health status remotely and in real-time. In particular, we investigate an extreme area in the design space of networked embedded objects: the domain of low energy, and real-time. Issues related to the design, implementation and deployment of such systems are also studied.
|[[&ref(bansmom1.jpeg,,70%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#p9fc9f99]]||[[&ref(bansmom-plat.jpg,,70%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#p9fc9f99]]|
*Fault-tolerant On-chip Interconnects for Adaptive and Self-Organizing Systems/Systems-on-Chip [#i8324fa0]
***Photonic 3D Network-on-Chip [#o731799d]
The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth and low latency. In addition, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems are able to accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NoC). The goal of this project is to study new reliable optical interconnect solutions to improve energy efficiency and bandwidth of on-chip interconnects for embedded and high-performance many-core systems.
|CENTER:[[&ref(PHENIC.gif,,50%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#ja7b74fe]]|
//CENTER:|PHENIC: High-level View of Multi-layers Si-Photonics 3D Network-on-Chip System.|
***Fault-tolerant Network-on-Chip Architecture [#n1e03182]
Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated in a single die area of just a few square millimeters. Such small complex SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low.
Our research effort is about solving several design challenges to enable such new NoC paradigm in many-core systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
|CENTER:[[&ref(oasis.png,,30%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#n1e03182]]|[[&ref(3D-OASIS-NoC.gif,,45%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#t90de557]]|
*Dynamic Programming, Adaptive Algorithms [#y77ff1c9]
***Parallel Programming Development [#m30a73e4]
解くべき問題が望んだ時間内に終わらない場合、よく行うのがアルゴリズムの並列化である。われわれは現在6コアのCPUと1台のGPUをを搭載したPCを高速ネットワークで4台つなげたシステムで、リアルタイム画像処理の開発を行っている。また、画像処理以外にも流体解析、構造解析などのソフトウェアを移植する予定。
上記のテーマはそれぞれ密接に関連している。C.、D.のテーマの画像処理応用に関しては岡研究室での自由視点TV の実時間処理と関連する。
//*** Towards a Desktop Supercomputer (デスクトップ・スーパーコンピュータをめざして) [#n46b51cd]
//理研で開発された宇宙物理学における多体重力問題向け PROGRAPE の応用範囲を拡張し、SPH 法による流体問題へ適用する研究を進めている。また、システムとしてFPGA の進化に併せてシステムをグレードアップするための汎用化技術にも取り組んでいる。
//この研究では、アプリケ=ションのアルゴリズム解析とともに、FPGA ボード, ホストPC, 高速バス(PCI Express, PCI-X)を総合的に構成するため、動的ハードウェアリソース管理についても研究を進めている。
***Matrix Processor [#u8e64ec0]
RapidMatrix という高速に行列演算を実行するプロセッサ実現のため、
*** High-speed Processing System Using GPGPU [#r9673c17]
本来、ゲーム等のグラフィックス処理に用いられてきた GPU をその並列処理性能に着目して高速計算へ利用しようという研究である。真にその潜在能力を発揮させるためには、どの部分を GPU に任せるか、アルゴリズムの解析とプログラムの工夫が必要である。
応用分野としてどのような処理が GPU 処理に向いているかも重要である。
*[[Previous Research Projects>http://aslweb.u-aizu.ac.jp/wiki/index.php?Previous%20Research]] [#g7eec6b3]
終了行:
[[ASL Wiki]]
[[Research]]
#CONTENTS
* Adaptive and Self-Organizing Systems/Systems-on-Chip [#ucd31e2a]
// for IoT and Biomedical Computing [#of1c6ec1]
***Adaptive Neuro-inspired Processor [#ube5191d]
The biological brain implements massively parallel computations using a complex architecture that is different from the conventional Von Neumann computing style. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Our goal in this project is to research and develop an adaptive and reliable neuro-inspired manycore system with on-chip learning and cognitive capabilities targeted for pattern recognition and complex cognitive tasks. Our other goal is to investigate and develop a low-power and low-cost platform for running large-scale simulations of biological brains in real-time targeted for neuroscience applications. Currently, we are investigating the following problems: the communication network for neuro-inspired chips, reconfigurability and adaptability methods, fault-tolerance, and learning circuits. In addition to these two target applications, lessons learned from this project will be also investigated to optimize power & performance of the conventional computing architectures.
CENTER:[[&ref(ANPU.png,,80%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#xc59e614]]
***Reliable Real-time Image Processing Multicore NoC System [#y3cd6bad]
With the advance in microprocessor technology, demands for practical vision systems have been appearing in security, surveillance, and robot applications. Typical vision processing cycle includes:(1)sense → (2) process → (3) analyze → (4) make a decision. Processing vision or object recognition algorithms, such as SIFT, requires huge computing power and data transactions among tasks, especially in applications where high frame-rate is essential. In addition, having a real-time decision also requires low latency from the system, which makes the analysis of the large input data (images or videos) set even more complicated. For this reason, an efficient and reliable Many-core architecture for communication and computation are needed for high-performance vision tasks.
The main goal of this project is to research about a Reliable Many-core architecture for low-level image processing in real-time, which solves several problems found in existing approaches. The novel system is based on our earlier developed reliable Network-on-Chip (OASIS). It will integrate several dedicated PEs for ILP/Data/Thread level parallelism while the 3D-OASIS NoC orchestrates communications between PEs and is used for a large amount of data transactions among tasks.
//COLOR(Green){Related Projects}
//-[[OASIS-VP1>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP]] (internal)
***Dependable Real-Time Multicore System-on-Chip for Elderly Health Monitoring [#pebd3cd2]
Recent technological advances in wireless networking, microelectronics and the Internet allow us to fundamentally change the way elderly health care services are practiced. Traditionally, embedded personal medical monitoring systems have been used only to collect data. Data processing and analysis are performed off-line, making such devices impractical for continual monitoring and early detection of medical disorders. The goal of this project is to research about smart in-body embedded system to monitor elderly health status remotely and in real-time. In particular, we investigate an extreme area in the design space of networked embedded objects: the domain of low energy, and real-time. Issues related to the design, implementation and deployment of such systems are also studied.
|[[&ref(bansmom1.jpeg,,70%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#p9fc9f99]]||[[&ref(bansmom-plat.jpg,,70%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#p9fc9f99]]|
*Fault-tolerant On-chip Interconnects for Adaptive and Self-Organizing Systems/Systems-on-Chip [#i8324fa0]
***Photonic 3D Network-on-Chip [#o731799d]
The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth and low latency. In addition, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems are able to accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NoC). The goal of this project is to study new reliable optical interconnect solutions to improve energy efficiency and bandwidth of on-chip interconnects for embedded and high-performance many-core systems.
|CENTER:[[&ref(PHENIC.gif,,50%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#ja7b74fe]]|
//CENTER:|PHENIC: High-level View of Multi-layers Si-Photonics 3D Network-on-Chip System.|
***Fault-tolerant Network-on-Chip Architecture [#n1e03182]
Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated in a single die area of just a few square millimeters. Such small complex SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low.
Our research effort is about solving several design challenges to enable such new NoC paradigm in many-core systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
|CENTER:[[&ref(oasis.png,,30%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#n1e03182]]|[[&ref(3D-OASIS-NoC.gif,,45%);>http://aslweb.u-aizu.ac.jp/wiki/index.php?Research#t90de557]]|
*Dynamic Programming, Adaptive Algorithms [#y77ff1c9]
***Parallel Programming Development [#m30a73e4]
解くべき問題が望んだ時間内に終わらない場合、よく行うのがアルゴリズムの並列化である。われわれは現在6コアのCPUと1台のGPUをを搭載したPCを高速ネットワークで4台つなげたシステムで、リアルタイム画像処理の開発を行っている。また、画像処理以外にも流体解析、構造解析などのソフトウェアを移植する予定。
上記のテーマはそれぞれ密接に関連している。C.、D.のテーマの画像処理応用に関しては岡研究室での自由視点TV の実時間処理と関連する。
//*** Towards a Desktop Supercomputer (デスクトップ・スーパーコンピュータをめざして) [#n46b51cd]
//理研で開発された宇宙物理学における多体重力問題向け PROGRAPE の応用範囲を拡張し、SPH 法による流体問題へ適用する研究を進めている。また、システムとしてFPGA の進化に併せてシステムをグレードアップするための汎用化技術にも取り組んでいる。
//この研究では、アプリケ=ションのアルゴリズム解析とともに、FPGA ボード, ホストPC, 高速バス(PCI Express, PCI-X)を総合的に構成するため、動的ハードウェアリソース管理についても研究を進めている。
***Matrix Processor [#u8e64ec0]
RapidMatrix という高速に行列演算を実行するプロセッサ実現のため、
*** High-speed Processing System Using GPGPU [#r9673c17]
本来、ゲーム等のグラフィックス処理に用いられてきた GPU をその並列処理性能に着目して高速計算へ利用しようという研究である。真にその潜在能力を発揮させるためには、どの部分を GPU に任せるか、アルゴリズムの解析とプログラムの工夫が必要である。
応用分野としてどのような処理が GPU 処理に向いているかも重要である。
*[[Previous Research Projects>http://aslweb.u-aizu.ac.jp/wiki/index.php?Previous%20Research]] [#g7eec6b3]
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