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開始行:
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CENTER:SIZE(40){COLOR(green){Low-power, High-performance Queue Processor}}
----
1. ''Goal:'' This project focuses on the research about a novel low power and high performance parallel processor processor based on Queue computation model, where Queue programs are generated by traversing a given data flow graph using level order traversal. The Queue processor uses a circular queue-register to manipulates operands and results, and exploits parallelism dynamically with "little efforts" when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of: compiler, assembler, functional and cycle accurate simulator, and hardware design.
CENTER:&ref(qc2.jpg,,130%);
CENTER:QueueCore Processor's circular Queue-register structure
//CENTER:&ref(Qcore.gif,,50%);
[[Public Page>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/]]
2. ''Members:''
- Hirki Hoshino, [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Hoshino-MS-10/m5131139_2010_MS_thesis.pdf]] . Feb. 2011.
-Masuda, [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Masuda-MS-10/m5131145_Masashi_MS_thesis.pdf]], Feb. 2011.
3. ''Group Publications:''
''Journal papers''
-A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda,[[Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super11/manuscript_preprint.pdf]],Journal of Supercomputing, Vol. 57, No. 3, pp. 314-338, Sept. 2011.[DOI]
-A. Ben Aballah, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa,[[The QC-2 Parallel Queue Processor Architecture>http://www.u-aizu.ac.jp/~benab/publications/journals/jpdc08/ad00c112a6a7dfa5312a0cfbf4f91e9e.pdf]], Journal of Parallel and Distributed Computing, Vol. 68, No. 2, (2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Efficient Compilation for Queue Size Constrained Queue Processors", The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Support for Code Size Reduction using a Queue-based Processor", Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
-A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model", Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007.
-A. Ben Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006
''Conference Papers''
-A. Ben Abdallah, M. Arsenji, Soichi Shigeta, Tsutomu Yoshinaga and Masahiro Sowa, [[Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme>http://www2.computer.org/portal/web/csdl/abs/proceedings/hpcasia/2004/2138/00/21380169abs.htm]], IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
-[[並列キュープロセッサの基本設計デザインガイア2002>http://www.u-aizu.ac.jp/~benab/publications/conferences/CPSY2002/PQP_ORG_IDEA.pdf]], 電子情報通信学会技術研究報告 IEICE CPSY2002-60, pp. 55-60, Nov., 2002.
-M. Masuda, A. Ben Abdallah, A. Canedo, “Software and Hardware Design Issues for Low Complexity High-Performance Processor Architecture”, The 38th International Conference on Parallel Processing Workshops, pp. 558-565, 2009
-M. Masuda, A. Canedo, A. Ben Abdallah, "Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture," The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
-H. Hoshino, A. Ben Abdallah, and K. Kuroda, "Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model", IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Quantitative Evaluation of Common Subexpression Elimination on Queue Machines", Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Queue Register File Optimization Algorithm for QueueCore Processor", Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
-A. Canedo,A. Ben Abdallah, and M. Sowa, "An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model", Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Framework for an Embedded 32-bit Queue Processor" , Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.
-A. Ben Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
-M. Sowa, A. Ben Abdallah, and T. Yoshinaga, "Processor Architecture Based on Produced Order Computation Model", Journal of Supercomputing, Vol. 32,No. 3, pp. 217-229, June 2005.
-A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.
-M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa "An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.
-A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, "Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation", Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing", Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
-A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", Proc. IEEE of the 7th High Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
-A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, "Design of Producer-Order Parallel Queue Processor Architecture", Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
-M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "High performance Hybrid Processor Architecture with Efficient Hardware Usability", Proc. of International workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004
-A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, "PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL", Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
-A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Architectural Issues in the Design of a High Performance Parallel Queue Processor", Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.
-A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)", Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
-A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Mode: On a Practical Queue Execution Model", Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.
-A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, "FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)", TIWSS’01, October 2001.
-A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Execution Model: Towards an Alternative Computing Paradigm", Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
-A. Ben Abdallah, M. Sarem., and M. Sowa, "Acyclic DFG on a Queue Machine", Proc. of JSPP, Tokyo, pp.119-120, 2000.
-A. Ben Abdallah, and M. Sowa, "DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor", Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT'99), pp.131-136, Oct.1999.
-Hiroki Hoshino, Abderazek Ben Abdallah and Kenichi Kuroda. Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.16-22, Dec. 2008.
-A. Ben Abdallah, et. all "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005
-A. Ben Abdallah, et. all,"Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
'''Technical Reports:'''
- H. Hoshino, [[QSoC - Queue System on Chip on FPGA>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QSoC/doc/QSoC32_specification.pdf]], Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Jan. 2010.
- T. Omoto, [[Qasm - User Friendly Assembler for Queue Computers>http://web-ext.u-aizu.ac.jp/~benab/research/projects/Qasm/Qasm_technical_report_2010.pdf]], Technixcal Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, 2010.
- H. Hoshino, [[QC-2 Data Path>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/qc2_data_path_v2_08102009.pdf]], Technical Report, ASL Systems architecture Group, School of Computer Science and Engineering, The University of Aizu, Oct. 2009
-A. Ben Abdallah, [[QueueCore - The Strong Wave!>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/QC2_presentationMay07.pdf]], Technical report, Network Computing Laboratory, Graduate School of Information Systems, The University of Electro-communications, May 2007
-A. Ben Abdallah, [[QueueCore Instruction Set Architecture>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/QC2isa.pdf]],Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, January 2003.
-A. Ben Abdallah, [[QC-1 Processing Stages Algorithms>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/design_algorithms_details.pdf]],
Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, 2003.
4. ''Sponsors:''
- UEC, UoA.
5. ''Poster''
--English: &ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/Queue_Poster_2009_en.pdf,,PDF);
--Japanese: &ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/Queue_Poster_2009_jp.pdf,,PDF);
--[[BELT machine>http://millcomputing.com/docs/belt/]]
----
CENTER:&ref(qc3.jpeg,,100%);
CENTER:The complete developed tool-chain is made of compiler (QCom), assembler(Qasm), functional and cycle accurate simulator (QSim), and soft-core hardware processor (QueueCore (QC-1, QC-2, and QC-3)).
終了行:
----
CENTER:SIZE(40){COLOR(green){Low-power, High-performance Queue Processor}}
----
1. ''Goal:'' This project focuses on the research about a novel low power and high performance parallel processor processor based on Queue computation model, where Queue programs are generated by traversing a given data flow graph using level order traversal. The Queue processor uses a circular queue-register to manipulates operands and results, and exploits parallelism dynamically with "little efforts" when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of: compiler, assembler, functional and cycle accurate simulator, and hardware design.
CENTER:&ref(qc2.jpg,,130%);
CENTER:QueueCore Processor's circular Queue-register structure
//CENTER:&ref(Qcore.gif,,50%);
[[Public Page>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/]]
2. ''Members:''
- Hirki Hoshino, [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Hoshino-MS-10/m5131139_2010_MS_thesis.pdf]] . Feb. 2011.
-Masuda, [[MS thesis (.pdf)>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Masuda-MS-10/m5131145_Masashi_MS_thesis.pdf]], Feb. 2011.
3. ''Group Publications:''
''Journal papers''
-A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda,[[Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super11/manuscript_preprint.pdf]],Journal of Supercomputing, Vol. 57, No. 3, pp. 314-338, Sept. 2011.[DOI]
-A. Ben Aballah, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa,[[The QC-2 Parallel Queue Processor Architecture>http://www.u-aizu.ac.jp/~benab/publications/journals/jpdc08/ad00c112a6a7dfa5312a0cfbf4f91e9e.pdf]], Journal of Parallel and Distributed Computing, Vol. 68, No. 2, (2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Efficient Compilation for Queue Size Constrained Queue Processors", The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Support for Code Size Reduction using a Queue-based Processor", Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
-A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model", Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007.
-A. Ben Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006
''Conference Papers''
-A. Ben Abdallah, M. Arsenji, Soichi Shigeta, Tsutomu Yoshinaga and Masahiro Sowa, [[Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme>http://www2.computer.org/portal/web/csdl/abs/proceedings/hpcasia/2004/2138/00/21380169abs.htm]], IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
-[[並列キュープロセッサの基本設計デザインガイア2002>http://www.u-aizu.ac.jp/~benab/publications/conferences/CPSY2002/PQP_ORG_IDEA.pdf]], 電子情報通信学会技術研究報告 IEICE CPSY2002-60, pp. 55-60, Nov., 2002.
-M. Masuda, A. Ben Abdallah, A. Canedo, “Software and Hardware Design Issues for Low Complexity High-Performance Processor Architecture”, The 38th International Conference on Parallel Processing Workshops, pp. 558-565, 2009
-M. Masuda, A. Canedo, A. Ben Abdallah, "Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture," The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
-H. Hoshino, A. Ben Abdallah, and K. Kuroda, "Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model", IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Quantitative Evaluation of Common Subexpression Elimination on Queue Machines", Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Queue Register File Optimization Algorithm for QueueCore Processor", Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
-A. Canedo,A. Ben Abdallah, and M. Sowa, "An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model", Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007
-A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Framework for an Embedded 32-bit Queue Processor" , Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core", Journal of supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.
-A. Ben Abdallah, Sotaro Kawata, and M. Sowa, "Design and Architecture for an Embedded 32-bit QueueCore", Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
-M. Sowa, A. Ben Abdallah, and T. Yoshinaga, "Processor Architecture Based on Produced Order Computation Model", Journal of Supercomputing, Vol. 32,No. 3, pp. 217-229, June 2005.
-A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.
-M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa "An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture", Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.
-A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, "Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation", Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005
-A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing", Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
-A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, "Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", Proc. IEEE of the 7th High Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
-A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, "Design of Producer-Order Parallel Queue Processor Architecture", Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
-M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "High performance Hybrid Processor Architecture with Efficient Hardware Usability", Proc. of International workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004
-A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, "PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL", Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
-A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Architectural Issues in the Design of a High Performance Parallel Queue Processor", Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.
-A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)", Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
-A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Mode: On a Practical Queue Execution Model", Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.
-A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, "FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)", TIWSS’01, October 2001.
-A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Execution Model: Towards an Alternative Computing Paradigm", Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
-A. Ben Abdallah, M. Sarem., and M. Sowa, "Acyclic DFG on a Queue Machine", Proc. of JSPP, Tokyo, pp.119-120, 2000.
-A. Ben Abdallah, and M. Sowa, "DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor", Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT'99), pp.131-136, Oct.1999.
-Hiroki Hoshino, Abderazek Ben Abdallah and Kenichi Kuroda. Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.16-22, Dec. 2008.
-A. Ben Abdallah, et. all "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005
-A. Ben Abdallah, et. all,"Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
'''Technical Reports:'''
- H. Hoshino, [[QSoC - Queue System on Chip on FPGA>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QSoC/doc/QSoC32_specification.pdf]], Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Jan. 2010.
- T. Omoto, [[Qasm - User Friendly Assembler for Queue Computers>http://web-ext.u-aizu.ac.jp/~benab/research/projects/Qasm/Qasm_technical_report_2010.pdf]], Technixcal Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, 2010.
- H. Hoshino, [[QC-2 Data Path>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/qc2_data_path_v2_08102009.pdf]], Technical Report, ASL Systems architecture Group, School of Computer Science and Engineering, The University of Aizu, Oct. 2009
-A. Ben Abdallah, [[QueueCore - The Strong Wave!>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/QC2_presentationMay07.pdf]], Technical report, Network Computing Laboratory, Graduate School of Information Systems, The University of Electro-communications, May 2007
-A. Ben Abdallah, [[QueueCore Instruction Set Architecture>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/QC2isa.pdf]],Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, January 2003.
-A. Ben Abdallah, [[QC-1 Processing Stages Algorithms>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QueueCore/doc/design_algorithms_details.pdf]],
Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, 2003.
4. ''Sponsors:''
- UEC, UoA.
5. ''Poster''
--English: &ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/Queue_Poster_2009_en.pdf,,PDF);
--Japanese: &ref(http://web-ext.u-aizu.ac.jp/~benab/publications/posters/Queue_Poster_2009_jp.pdf,,PDF);
--[[BELT machine>http://millcomputing.com/docs/belt/]]
----
CENTER:&ref(qc3.jpeg,,100%);
CENTER:The complete developed tool-chain is made of compiler (QCom), assembler(Qasm), functional and cycle accurate simulator (QSim), and soft-core hardware processor (QueueCore (QC-1, QC-2, and QC-3)).
ページ名: