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開始行:
[[Other Available Research Topics ]]
*COLOR(gold){PHENIC:Si-Photonics Netwok-on-Chip} COLOR(red){==> Go to [[PHENIC]] Project Page} [#a4468222]
***COLOR(blue){[[1. Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC} COLOR(blue){(電子2D-NoCと光電子2D-NoCの電力・性能比較)>http://aslweb.u-aizu.ac.jp/aslint/index.php?GT%2FMS%20Research]]} [#d314ebda]
--Member: COLOR(red){[[B4 Ryoga Okada(岡田 凌駕)>Ryoga Okada]]}
***[[GT4. PHENICシステムのための光電子ネットワークインターフェースの設計>http://aslweb.u-aizu.ac.jp/aslint/index.php?GT4]] [#v5162faa]
--Member: Open topic.
***COLOR(blue){2. Design and Analysis of Electrical Control Router for PHENIC System} [#ffdefa1b]
--Member: [[B4 Ken Saito(斎藤 拳)>Ken Saito]] (s1200049)
//***COLOR(blue){3. Design of High-speed Optical Router Architecture for PHENIC Many-core Systems} [#x06cf332]
*COLOR(gold){OASIS: Reliable Network-on-Chip} COLOR(red){==>go to [[OASIS]] Project Page} [#j67d2253]
***COLOR(blue){Performance Evalaution of OASIS 3D-Router} [#a76aac73]
Old: Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)
--Member: -[[B4 Takaya Hirai(平井 隆哉)>Takaya Hirai]]
//COLOR(red){B4 Yuki Tanaka}
***COLOR(blue){Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System} [#e2b32ba5]
--Member: COLOR(red){[[B4 Akihito Kajikawa(梶川 聡仁)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akihito%20Kajikawa]]}
//*COLOR(gold){[[OASIS-VP]]:Fault-tolerant Many-core Mobile Vision System [誤り耐性メニーコアモバイル視覚システム]} [#abfc7541]
*COLOR(gold){Processing Cores for Adaptive computing } [#k67b6b31]
** Adaptive Processor [#b6afc9de]
*** COLOR(blue){5. Implementation of task assignment algorithm} [#w0a73c73]
*** Implementation of architecture (Ishikuro) [#a2da2c0f]
** Matrix Processor [#mb97dd63]
*** COLOR(blue){6. Layout design of Matrix-ALU} [#y3c8c57c]
*** Practical interface between host computer/routers (Nakamura) [#of775353]
*** Embedded navigation system as a practical application (Yusuke) [#m0626c81]
*COLOR(gold){Advanced Vision Processing Algorithms} [#r25e7a22]
*** COLOR(green){Architecture exploration of 2DCDP for 3D-chips} [#s0000c92]
*** COLOR(blue){7. Video recognition with TSCDP (Hayamizu)} [#z0ce2a2e]
*COLOR(gold){Real Time Signal Processing} [#sa9ed3d7]
*** Extraction of training efficiency from EEG (Ito) [#c9ceed25]
*** COLOR(blue){8. P300 detection from few electrodes} [#o1a12892]
----
*Previous Topics [前のトピック] [#nd57a4c9]
-[[Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC>Mitsunari Ishii]], COLOR(black){B4 Mitsunari Ishii}
-[[Design and Evaluation of 3D-OASIS-NoC Matrix Processor>http://aslweb.u-aizu.ac.jp/aslint/index.php?Mitsuhiro%20Nakamura]],
//COLOR(red){M1 Mitsuhiro Nakamura}
-COLOR(green){Performance Study and Evaluation of OASIS Network-on-Chip on FPGA)}
-COLOR(green){Hardware and Software Optimization Techniques for OASIS NoC (OASISネットワークオンチップのハード/ソフトウェア最適化技術に関する研究)}
-COLOR(green){Architecture and Design of Core Network Interface for Source Routing (ソースルーティング機能実装にむけてのネットワークインターフェースコア部分のアーキテクチャと設計)}
-COLOR(green){Power investigation of Heterogeneous Multicore System (マルチコア消費電力に関する研究)}
終了行:
[[Other Available Research Topics ]]
*COLOR(gold){PHENIC:Si-Photonics Netwok-on-Chip} COLOR(red){==> Go to [[PHENIC]] Project Page} [#a4468222]
***COLOR(blue){[[1. Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC} COLOR(blue){(電子2D-NoCと光電子2D-NoCの電力・性能比較)>http://aslweb.u-aizu.ac.jp/aslint/index.php?GT%2FMS%20Research]]} [#d314ebda]
--Member: COLOR(red){[[B4 Ryoga Okada(岡田 凌駕)>Ryoga Okada]]}
***[[GT4. PHENICシステムのための光電子ネットワークインターフェースの設計>http://aslweb.u-aizu.ac.jp/aslint/index.php?GT4]] [#v5162faa]
--Member: Open topic.
***COLOR(blue){2. Design and Analysis of Electrical Control Router for PHENIC System} [#ffdefa1b]
--Member: [[B4 Ken Saito(斎藤 拳)>Ken Saito]] (s1200049)
//***COLOR(blue){3. Design of High-speed Optical Router Architecture for PHENIC Many-core Systems} [#x06cf332]
*COLOR(gold){OASIS: Reliable Network-on-Chip} COLOR(red){==>go to [[OASIS]] Project Page} [#j67d2253]
***COLOR(blue){Performance Evalaution of OASIS 3D-Router} [#a76aac73]
Old: Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)
--Member: -[[B4 Takaya Hirai(平井 隆哉)>Takaya Hirai]]
//COLOR(red){B4 Yuki Tanaka}
***COLOR(blue){Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System} [#e2b32ba5]
--Member: COLOR(red){[[B4 Akihito Kajikawa(梶川 聡仁)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akihito%20Kajikawa]]}
//*COLOR(gold){[[OASIS-VP]]:Fault-tolerant Many-core Mobile Vision System [誤り耐性メニーコアモバイル視覚システム]} [#abfc7541]
*COLOR(gold){Processing Cores for Adaptive computing } [#k67b6b31]
** Adaptive Processor [#b6afc9de]
*** COLOR(blue){5. Implementation of task assignment algorithm} [#w0a73c73]
*** Implementation of architecture (Ishikuro) [#a2da2c0f]
** Matrix Processor [#mb97dd63]
*** COLOR(blue){6. Layout design of Matrix-ALU} [#y3c8c57c]
*** Practical interface between host computer/routers (Nakamura) [#of775353]
*** Embedded navigation system as a practical application (Yusuke) [#m0626c81]
*COLOR(gold){Advanced Vision Processing Algorithms} [#r25e7a22]
*** COLOR(green){Architecture exploration of 2DCDP for 3D-chips} [#s0000c92]
*** COLOR(blue){7. Video recognition with TSCDP (Hayamizu)} [#z0ce2a2e]
*COLOR(gold){Real Time Signal Processing} [#sa9ed3d7]
*** Extraction of training efficiency from EEG (Ito) [#c9ceed25]
*** COLOR(blue){8. P300 detection from few electrodes} [#o1a12892]
----
*Previous Topics [前のトピック] [#nd57a4c9]
-[[Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC>Mitsunari Ishii]], COLOR(black){B4 Mitsunari Ishii}
-[[Design and Evaluation of 3D-OASIS-NoC Matrix Processor>http://aslweb.u-aizu.ac.jp/aslint/index.php?Mitsuhiro%20Nakamura]],
//COLOR(red){M1 Mitsuhiro Nakamura}
-COLOR(green){Performance Study and Evaluation of OASIS Network-on-Chip on FPGA)}
-COLOR(green){Hardware and Software Optimization Techniques for OASIS NoC (OASISネットワークオンチップのハード/ソフトウェア最適化技術に関する研究)}
-COLOR(green){Architecture and Design of Core Network Interface for Source Routing (ソースルーティング機能実装にむけてのネットワークインターフェースコア部分のアーキテクチャと設計)}
-COLOR(green){Power investigation of Heterogeneous Multicore System (マルチコア消費電力に関する研究)}
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