OASIS-VP-Topic-3
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CENTER:SIZE(40){COLOR(blue){ Implementation and Evaluation of OpenRISC core.}}
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[[OASIS-VP]]
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*Overview [#of0ac920]
This topic is implementation and evaluation of OpenRISC core. OpenRISC is a project of open source instruction set architecture based on RISC. Figure 1 shows the architecture of OR1200, an implementation of OpenRISC core.
The OpenRISC project has several features:
- Support 32 and 64 bits instruction set; vector, floating point and DSP instruction.
- Support cache coherence, virtual memory support.
- Available in HDL: Verilog and VHDL.
- ASIC and FPGA implementation proof.
- Supported software: 32-bit GNU toolchain, simulators, Operating System (Linux, RTEMS)…
CENTER:&ref(OR1200_CPU.png,,50%);
CENTER:Figure 1: OpenRISC OR1200 architecture.
*Research Description [#sa9adf8b]
As a part of OASIS-VP, this topic investigates the implementation results and performance of OpenRISC on a real platform. The core is firstly simulated and verified its functionalities. Later, it will be implemented on an FPGA board with I/O interfaces such as: mouse, keyboard, VGA. The final system needs to be installed with an OS and perform a test program to illustrate it performance.
// Note: This topic can be extended as an implementation of a full system on FPGA which can interface with mouse, keyboard, VGA and run Linux OS.
*Expected Output [#lfbc15c0]
- Investigate the operation and architecture of OpenRISC.
- Implement the OpenRISC core into an FPGA board.
- Evaluate the performance of OpenRISC core.
*References [#ba027dbf]
- Main references: Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf
- Other Documents: [[Link>https://drive.google.com/file/d/0B1g5BRAzi1DaWVBQaDVvTDYtZ1U/view?usp=sharing]]
-- [1] OpenRISC website: http://opencores.org/or1k/Main_Page
-- [2] Tutorials provided by community: http://openrisc.io/tutorials
-- [3] Source code, tutorial download: https://github.com/openrisc
-- [4] Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf
-- [5] Web-based emulator: https://s-macke.github.io/jor1k/demos/main.html?user=wp5JsnLppl
終了行:
CENTER:SIZE(40){COLOR(blue){ Implementation and Evaluation of OpenRISC core.}}
----
[[OASIS-VP]]
----
*Overview [#of0ac920]
This topic is implementation and evaluation of OpenRISC core. OpenRISC is a project of open source instruction set architecture based on RISC. Figure 1 shows the architecture of OR1200, an implementation of OpenRISC core.
The OpenRISC project has several features:
- Support 32 and 64 bits instruction set; vector, floating point and DSP instruction.
- Support cache coherence, virtual memory support.
- Available in HDL: Verilog and VHDL.
- ASIC and FPGA implementation proof.
- Supported software: 32-bit GNU toolchain, simulators, Operating System (Linux, RTEMS)…
CENTER:&ref(OR1200_CPU.png,,50%);
CENTER:Figure 1: OpenRISC OR1200 architecture.
*Research Description [#sa9adf8b]
As a part of OASIS-VP, this topic investigates the implementation results and performance of OpenRISC on a real platform. The core is firstly simulated and verified its functionalities. Later, it will be implemented on an FPGA board with I/O interfaces such as: mouse, keyboard, VGA. The final system needs to be installed with an OS and perform a test program to illustrate it performance.
// Note: This topic can be extended as an implementation of a full system on FPGA which can interface with mouse, keyboard, VGA and run Linux OS.
*Expected Output [#lfbc15c0]
- Investigate the operation and architecture of OpenRISC.
- Implement the OpenRISC core into an FPGA board.
- Evaluate the performance of OpenRISC core.
*References [#ba027dbf]
- Main references: Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf
- Other Documents: [[Link>https://drive.google.com/file/d/0B1g5BRAzi1DaWVBQaDVvTDYtZ1U/view?usp=sharing]]
-- [1] OpenRISC website: http://opencores.org/or1k/Main_Page
-- [2] Tutorials provided by community: http://openrisc.io/tutorials
-- [3] Source code, tutorial download: https://github.com/openrisc
-- [4] Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf
-- [5] Web-based emulator: https://s-macke.github.io/jor1k/demos/main.html?user=wp5JsnLppl
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