OASIS-VP-Topic-2
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開始行:
CENTER:SIZE(40){COLOR(blue){Implementation and Evaluation of Hard-Error Resilience for OASIS Network-on-Chip}}
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[[OASIS-VP]]
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*Overview [#c1ea267d]
This project is implementation and evaluation of soft error resilience method for 3D Network-on-Chip.
CENTER:&ref(3Dtop.png,,50%);
The architecture is based on 3D Network-on-Chip model which is called as OASIS. Figure 1 depicts an example of 4×2×2 3D Network-on-Chip. The router is connected with its neighbors or local core by wires. There are seven possible connections: local (PE), north, east, south, west, up, and down. For the up and down connections, we use special inter-layer links which are called as Through-Silicon-Vias (TSVs).
*Research Description [#b54aac9f]
CENTER:&ref(RAB.jpg,,40%); CENTER:&ref(BLoD.jpg,,40%);
This project is an extended version of OASIS router with two techniques to handle the hard errors:
- Random Access Buffer (RAB): when a fault occurs in a buffer slot, RAB isolates this faulty buffer slot then maintain the operation of the buffer.
- Bypass-link-on-Demand (BLoD): when a fault occurs in a crossbar link, BLoD replaces the faulty link by a back-up link and maintain the connection.
*Expected Output [#ha4d05b6]
- Read and understand the architecture and operation of OASIS Network-on-Chip.
- Understand the hard error resilience methods for OASIS Network-on-Chip:
-- Random Access Buffer
-- Bypass-link-on-Demand
- Run and performance evaluate and extract the results.
- Compare the performance of the original OASIS and the Hard Error Resilience architecture.
*References [#le6f6e2b]
- Main reference: [[ref 1>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]]; [[ref 2>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/MCSOC14_preprint.pdf]]
- Other Documents:
--[[Introduction>https://drive.google.com/file/d/0B1g5BRAzi1DaSUlncHpzTFA1alE/view?usp=sharing]], [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
-- [0] OASIS internal page: http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS
-- [1] “On the Design of a 3D Network-on-Chip for Many-core SoC”; Akram Ben Ahmed; Master Thesis 2012.[[Link>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]]
-- [2] “Adaptive Error- and Traffic-aware Router Architecture for 3D Network-on-Chip Systems”; Akram Ben Ahmed et. al.; MCSoC-14. [[http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/MCSOC14_preprint.pdf]]
-- [3] “Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems”; Abderazek Ben Abdallah et. al; ISCEAS 2015; [[link>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]];
-- [4] “Benchmark suite for OASIS NoC”; [[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]]
-- [5] Source code: hard-ft.zip: hard error router; baseline-hlaft: OASIS router, tb.zip: Test bench files. [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
終了行:
CENTER:SIZE(40){COLOR(blue){Implementation and Evaluation of Hard-Error Resilience for OASIS Network-on-Chip}}
----
[[OASIS-VP]]
----
*Overview [#c1ea267d]
This project is implementation and evaluation of soft error resilience method for 3D Network-on-Chip.
CENTER:&ref(3Dtop.png,,50%);
The architecture is based on 3D Network-on-Chip model which is called as OASIS. Figure 1 depicts an example of 4×2×2 3D Network-on-Chip. The router is connected with its neighbors or local core by wires. There are seven possible connections: local (PE), north, east, south, west, up, and down. For the up and down connections, we use special inter-layer links which are called as Through-Silicon-Vias (TSVs).
*Research Description [#b54aac9f]
CENTER:&ref(RAB.jpg,,40%); CENTER:&ref(BLoD.jpg,,40%);
This project is an extended version of OASIS router with two techniques to handle the hard errors:
- Random Access Buffer (RAB): when a fault occurs in a buffer slot, RAB isolates this faulty buffer slot then maintain the operation of the buffer.
- Bypass-link-on-Demand (BLoD): when a fault occurs in a crossbar link, BLoD replaces the faulty link by a back-up link and maintain the connection.
*Expected Output [#ha4d05b6]
- Read and understand the architecture and operation of OASIS Network-on-Chip.
- Understand the hard error resilience methods for OASIS Network-on-Chip:
-- Random Access Buffer
-- Bypass-link-on-Demand
- Run and performance evaluate and extract the results.
- Compare the performance of the original OASIS and the Hard Error Resilience architecture.
*References [#le6f6e2b]
- Main reference: [[ref 1>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]]; [[ref 2>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/MCSOC14_preprint.pdf]]
- Other Documents:
--[[Introduction>https://drive.google.com/file/d/0B1g5BRAzi1DaSUlncHpzTFA1alE/view?usp=sharing]], [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
-- [0] OASIS internal page: http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS
-- [1] “On the Design of a 3D Network-on-Chip for Many-core SoC”; Akram Ben Ahmed; Master Thesis 2012.[[Link>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]]
-- [2] “Adaptive Error- and Traffic-aware Router Architecture for 3D Network-on-Chip Systems”; Akram Ben Ahmed et. al.; MCSoC-14. [[http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/MCSOC14_preprint.pdf]]
-- [3] “Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems”; Abderazek Ben Abdallah et. al; ISCEAS 2015; [[link>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]];
-- [4] “Benchmark suite for OASIS NoC”; [[PDF>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]]
-- [5] Source code: hard-ft.zip: hard error router; baseline-hlaft: OASIS router, tb.zip: Test bench files. [[Source code (OASIS)>https://drive.google.com/file/d/0B1g5BRAzi1DaWmdXdk9remh6c1k/view?usp=sharing]]
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