OASIS-VP-Topic 3-2
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開始行:
[[OASIS-VP-Topic-1]]
[[Available Research Topics]]
Design of RISC-V Processor System on Altera FPGA.
(Tentative title)
*Research Overview [#p93d4a3e]
In this research, you part a RISC core processor and peripheral system from Xilinx to Altera FPGA. Design of soft-core is an important to evaluate performance of a system related with speed, power consumption, and price. Though we have two de-fact FPGAs; Xilinx and Altera FPGA, only Xilinx one is provided. On the other hand, There are many Altera users especially for educational propose. The goal of this research is to run RISC-V processor on Altera FPGA device. This will accelerate the research based on Altera devices.
*Research Description [#ob708645]
+ Learn from current design: Run an implementation for Xilinx FPGA; Open low RISC
+ Analyze inside of LowRISC: Investigate source code for processor and connection
+ Learn Qsys tools for altera SoC design: Investigate how to implement lowRISC on Altera FPGA
+ Implementation
*Expected outputs [#j8cb2a39]
You will write four documents
+ How to run RISC-V on Xilinx FPGA
+ Overview of RISC-V processor
+ How to implement RISC-V on Altera FPGA
+ Benchmark result
*Reference [#e4ce9a01]
+ [[RISC-V Web Page>http://www.riscv.org]]
終了行:
[[OASIS-VP-Topic-1]]
[[Available Research Topics]]
Design of RISC-V Processor System on Altera FPGA.
(Tentative title)
*Research Overview [#p93d4a3e]
In this research, you part a RISC core processor and peripheral system from Xilinx to Altera FPGA. Design of soft-core is an important to evaluate performance of a system related with speed, power consumption, and price. Though we have two de-fact FPGAs; Xilinx and Altera FPGA, only Xilinx one is provided. On the other hand, There are many Altera users especially for educational propose. The goal of this research is to run RISC-V processor on Altera FPGA device. This will accelerate the research based on Altera devices.
*Research Description [#ob708645]
+ Learn from current design: Run an implementation for Xilinx FPGA; Open low RISC
+ Analyze inside of LowRISC: Investigate source code for processor and connection
+ Learn Qsys tools for altera SoC design: Investigate how to implement lowRISC on Altera FPGA
+ Implementation
*Expected outputs [#j8cb2a39]
You will write four documents
+ How to run RISC-V on Xilinx FPGA
+ Overview of RISC-V processor
+ How to implement RISC-V on Altera FPGA
+ Benchmark result
*Reference [#e4ce9a01]
+ [[RISC-V Web Page>http://www.riscv.org]]
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