OASIS-VP
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開始行:
CENTER:SIZE(60){COLOR(green){ OASIS-VP: Real-time Multi-core Vision SoC based on OASIS NoC }}
*Project Description: [#jd77432b]
//With the advance in microprocessor technology, demands for practical vision systems have been appearing in security, surveillance, and robot applications. Typical vision processing cycle includes:(1)sense → (2) process → (3) analyze → (4) make a decision. Processing vision or object recognition algorithms, such as SIFT, requires huge computing power and data transactions among tasks, especially in applications where high frame-rate is essential. In addition, having a real-time decision also requires low latency from the system, which makes the analysis of the large input data (images or videos) set even more complicated. For this reason, an efficient and reliable Many-core architecture for communication and computation are needed for high-performance vision tasks. The main goal of this project is to research about a Reliable Many-core architecture for low-level image processing in real-time, which solves several problems found in existing approaches. The novel system is based on our earlier developed reliable Network-on-Chip (OASIS). It will integrate several dedicated PEs for ILP/Data/Thread level parallelism while the 3D-OASIS NoC orchestrates communications between PEs and is used for a large amount of data transactions among tasks. Available research topics in this project are related to both software and hardware research and development.
//The main goal of this project is to research about algorithms and, architecture for a Reliable Many-core 3D-NoC System Targeted for Real-Time Vision Applications (i.e., gesture/motion/object recognition/surveillance). The system is based on our earlier developed reliable Network-on-Chip (OASIS). The system will integrate several dedicated PEs for ILP/Data/Thread level parallelism, while the 3D-OASIS NoC orchestrates communications between PEs and is used for large amount of data transactions among tasks.
マイクロプロセッサの進化によって、実用的な視覚システムへの要求がセキュリ ティ・監 視・ロボット応用においても現れてきています。典型的な視覚処理のサイクルは一般的に (1)感知 → (2) 処理 → (3) 分析→ (4) 決定 から成ります。SIFTのような視覚処理及び物体認 識アルゴリズムはとりわけ高フレームレートが不可欠なアプリケーションにおいて膨大な 計算能力やタスク間のデータのやり取りを必要とします。さらに、リアルタイム決定をす るにはさらに複雑な大きな入力データ(画像または映像)セットの解析を行うシステムに 低レイテンシを要求します。したがって、効率的で信頼性のある通信や計算のためのメニ ーコアアーキテクチャがハイパフォーマンス視覚タスクでは必要とされます。 この計画の主な目標は既存の手法において見られる様々な問題を解決する信頼性のあるリ アルタイム低レベル視覚処理のためのメニーコア3D-NoCアーキテクチャを研究、開発さ せることです。このシステムは我々が以前開発した信頼性のあるネットワークオンチップ (OASIS)に基づきます。このシステムは3D-OASIS NoCがPE間での通信を調整し、タスク 間のデータのやり取りに大量に使用されている一方で、ILP/データ/スレッドレベルでの並 列化のためにいくつか専用のPEを統合します。この計画で利用可能な研
//CENTER:&ref(oasis.png,,30%);
*Members [#oa205888]
-[[M1 Akihito Kajikawa(梶川 聡仁)>http://aslweb.u-aizu.ac.jp/aslint/index.php?M1%20Akihito%20Kajikawa]]
-[[D1 Dang>http://adaptive.u-aizu.ac.jp/?page_id=1218]]
*System Architecture [#p46ceab6]
CENTER:[[&ref(system.png,,70%);>http://aslweb.u-aizu.ac.jp/benlab/index.php?Research#db474e2f]]
OASIS-VP is based on a 2D Network-on-Chip of 4×4 tiles. Each tile consist of a Router (R), a Network-Interface (NI) and a core (C). In this project, we select OpenRISC as the core for OASIS-VP tile. The [[OpenRISC core>https://en.wikipedia.org/wiki/OpenRISC_1200]] uses Wishbone interface to connect with NI, an internal bus for intra-core communications. OpenRISC also includes several extra function modules: debugging, power management, tick timer, internal memory.
- Specification: [[ver 0.1>https://drive.google.com/file/d/0B1g5BRAzi1DaTXNWZWlhT0gxY3c/view?usp=sharing]]; COLOR(red){(Last update: 2016/May/04 18:30)}.
//*Available Research Topics Set I [#n1fe0a09]
//-[[Topic 1: Implementation and Evaluation of Soft-Error Resilience for OASIS Network-on-Chip>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-1]]
//-[[Topic 2: Implementation and Evaluation of Hard-Error Resilience for OASIS Network-on-Chip>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-2]]
//-[[Topic 3: Implementation and Evaluation of OpenRISC core.>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-3]]
//- [[Topic 4: Implementation and Evaluation of Network-Interface (Wishbone-compatible).>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-4]]
//*[[Available Research Topics Set II>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP%20Available%20Topics]] [#t8d7e269]
*Links [#q4c74c14]
-[[OASIS-VP GDoc Spec (editable)>https://docs.google.com/document/d/1PzBDPGNPMFj2-N3tKNtVGwayoeB5BBm3P12hdJzIf-Y/edit?usp=sharing]]
-[[SIFT Lecture (Video)>https://www.youtube.com/watch?v=NPcMS49V5hg]]
-[[SIFT Lecture (Japanese)>https://drive.google.com/file/d/0B1g5BRAzi1DaRDJ4ZjY3S0lKbFU/view?usp=sharing]]
-[[SIFT Demo (Matlab)>https://drive.google.com/file/d/0B1g5BRAzi1Dab2JGVXJPZS1wYlE/view?usp=sharing]]
-[[Tapeout (by Akram)>https://drive.google.com/file/d/0B1g5BRAzi1DacjU1TEd4VDBYSXc/view?usp=sharing]]
終了行:
CENTER:SIZE(60){COLOR(green){ OASIS-VP: Real-time Multi-core Vision SoC based on OASIS NoC }}
*Project Description: [#jd77432b]
//With the advance in microprocessor technology, demands for practical vision systems have been appearing in security, surveillance, and robot applications. Typical vision processing cycle includes:(1)sense → (2) process → (3) analyze → (4) make a decision. Processing vision or object recognition algorithms, such as SIFT, requires huge computing power and data transactions among tasks, especially in applications where high frame-rate is essential. In addition, having a real-time decision also requires low latency from the system, which makes the analysis of the large input data (images or videos) set even more complicated. For this reason, an efficient and reliable Many-core architecture for communication and computation are needed for high-performance vision tasks. The main goal of this project is to research about a Reliable Many-core architecture for low-level image processing in real-time, which solves several problems found in existing approaches. The novel system is based on our earlier developed reliable Network-on-Chip (OASIS). It will integrate several dedicated PEs for ILP/Data/Thread level parallelism while the 3D-OASIS NoC orchestrates communications between PEs and is used for a large amount of data transactions among tasks. Available research topics in this project are related to both software and hardware research and development.
//The main goal of this project is to research about algorithms and, architecture for a Reliable Many-core 3D-NoC System Targeted for Real-Time Vision Applications (i.e., gesture/motion/object recognition/surveillance). The system is based on our earlier developed reliable Network-on-Chip (OASIS). The system will integrate several dedicated PEs for ILP/Data/Thread level parallelism, while the 3D-OASIS NoC orchestrates communications between PEs and is used for large amount of data transactions among tasks.
マイクロプロセッサの進化によって、実用的な視覚システムへの要求がセキュリ ティ・監 視・ロボット応用においても現れてきています。典型的な視覚処理のサイクルは一般的に (1)感知 → (2) 処理 → (3) 分析→ (4) 決定 から成ります。SIFTのような視覚処理及び物体認 識アルゴリズムはとりわけ高フレームレートが不可欠なアプリケーションにおいて膨大な 計算能力やタスク間のデータのやり取りを必要とします。さらに、リアルタイム決定をす るにはさらに複雑な大きな入力データ(画像または映像)セットの解析を行うシステムに 低レイテンシを要求します。したがって、効率的で信頼性のある通信や計算のためのメニ ーコアアーキテクチャがハイパフォーマンス視覚タスクでは必要とされます。 この計画の主な目標は既存の手法において見られる様々な問題を解決する信頼性のあるリ アルタイム低レベル視覚処理のためのメニーコア3D-NoCアーキテクチャを研究、開発さ せることです。このシステムは我々が以前開発した信頼性のあるネットワークオンチップ (OASIS)に基づきます。このシステムは3D-OASIS NoCがPE間での通信を調整し、タスク 間のデータのやり取りに大量に使用されている一方で、ILP/データ/スレッドレベルでの並 列化のためにいくつか専用のPEを統合します。この計画で利用可能な研
//CENTER:&ref(oasis.png,,30%);
*Members [#oa205888]
-[[M1 Akihito Kajikawa(梶川 聡仁)>http://aslweb.u-aizu.ac.jp/aslint/index.php?M1%20Akihito%20Kajikawa]]
-[[D1 Dang>http://adaptive.u-aizu.ac.jp/?page_id=1218]]
*System Architecture [#p46ceab6]
CENTER:[[&ref(system.png,,70%);>http://aslweb.u-aizu.ac.jp/benlab/index.php?Research#db474e2f]]
OASIS-VP is based on a 2D Network-on-Chip of 4×4 tiles. Each tile consist of a Router (R), a Network-Interface (NI) and a core (C). In this project, we select OpenRISC as the core for OASIS-VP tile. The [[OpenRISC core>https://en.wikipedia.org/wiki/OpenRISC_1200]] uses Wishbone interface to connect with NI, an internal bus for intra-core communications. OpenRISC also includes several extra function modules: debugging, power management, tick timer, internal memory.
- Specification: [[ver 0.1>https://drive.google.com/file/d/0B1g5BRAzi1DaTXNWZWlhT0gxY3c/view?usp=sharing]]; COLOR(red){(Last update: 2016/May/04 18:30)}.
//*Available Research Topics Set I [#n1fe0a09]
//-[[Topic 1: Implementation and Evaluation of Soft-Error Resilience for OASIS Network-on-Chip>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-1]]
//-[[Topic 2: Implementation and Evaluation of Hard-Error Resilience for OASIS Network-on-Chip>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-2]]
//-[[Topic 3: Implementation and Evaluation of OpenRISC core.>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-3]]
//- [[Topic 4: Implementation and Evaluation of Network-Interface (Wishbone-compatible).>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP-Topic-4]]
//*[[Available Research Topics Set II>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-VP%20Available%20Topics]] [#t8d7e269]
*Links [#q4c74c14]
-[[OASIS-VP GDoc Spec (editable)>https://docs.google.com/document/d/1PzBDPGNPMFj2-N3tKNtVGwayoeB5BBm3P12hdJzIf-Y/edit?usp=sharing]]
-[[SIFT Lecture (Video)>https://www.youtube.com/watch?v=NPcMS49V5hg]]
-[[SIFT Lecture (Japanese)>https://drive.google.com/file/d/0B1g5BRAzi1DaRDJ4ZjY3S0lKbFU/view?usp=sharing]]
-[[SIFT Demo (Matlab)>https://drive.google.com/file/d/0B1g5BRAzi1Dab2JGVXJPZS1wYlE/view?usp=sharing]]
-[[Tapeout (by Akram)>https://drive.google.com/file/d/0B1g5BRAzi1DacjU1TEd4VDBYSXc/view?usp=sharing]]
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