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開始行:
[[back to OASIS>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]]
*WWW Routers [#x37bbd3d]
- Kumar, A ; Dept. of Electr. Eng., Princeton Univ., Princeton, NJ ; Kundu, P. ; Singhx, A.P. ; Li-Shiuan Peh , [[A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4601881&tag=1]], ICCD 2007. 25th International Conference on Computer Design, 2007.
-http://hellojooyoung.com/res.php
*Blogs [#r1099e0f]
- NoC Blog http://networkonchip.wordpress.com/
*Simulators [#la2fbe14]
*** 1. NoC prototypes: full design data available [#a23a8b01]
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:
-[[CONfigurable NEtwork Creation Tool>http://www.cs.cmu.edu/~mpapamic/projects/connect.html]], Online BlueSpec SystemVerilog generator for NoCs that are “FPGA-friendly”, 2012
-[[NetMaker (University of Cambridge)>http://www-dyn.cl.cam.ac.uk/~rdm34/wiki/index.php?title=Main_Page]] – FPGA, 2009
-[[Open Noc (Linköpings Universitet)>http://www.da.isy.liu.se/research/soc/fpganoc/]] – FPGA, 2007
-[[Mini NoC (Technische Universiteit Eindhoven)>http://www.es.ele.tue.nl/mininoc/]] – FPGA, 2006
***2. NoC prototypes: partial/no/promised design data available [#l9759967]
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:
-[[Atlas>https://corfu.pucrs.br/redmine/projects/atlas]] (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
-[[NoCGen>http://tima-sls.imag.fr/www/research/nocgen]]: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
-[[NoCBench>http://www.tkt.cs.tut.fi/research/nocbench/download.html]], Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.
***3. Router prototypes [#w199112f]
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
-[[Open source NoC router>https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/Router]] (Stanford. A parameterized RTL implementation of a state-of-the-art VC router.) – 2013
* 3D Packaging In Japan [#jf807427]
-IEEE CPMT Society
http://www.cpmt.org/
-IEEE Japan Council
http://www.ieee-jp.org/japancouncil/index_e.htm
-Japan Institute of Electronics Packaging (JIEP)
http://www.e-jisso.jp/
-IMAPS:
http://www.imaps.org/
-Research Committee for 3D Integration by Low-temperature Bonding Technology
http://www.su.t.u-tokyo.ac.jp/~3dwb/committee/index-e.html
*Mis [#w0478a9b]
[[NoC2006 Keynotes>http://async.org.uk/noc2006/]]
- [[Keynote: NoCs: Vision, reality, trends>http://async.org.uk/noc2006/pdf/Luca-Benini.pdf]]
Luca Benini, DEIS - Bologna U, Italy
- [[Standards in NoC: What can we gain?>http://async.org.uk/noc2006/pdf/Luca-Benini.pdf]], Axel Jantsch, KTH Stockholm, Sweden
- [[Networks and Applications: Are Application-Specific Networks Worth the Trouble?>http://async.org.uk/noc2006/pdf/Wayne-Wolf.pdf]], Wayne Wolf, Princeton U, United States
-Advances in On-Chip Interconnects (invited presentations)
Chair: Pol Marchal, IMEC, Belgium
-[[On-Chip Interconnect: The past, present, and future>http://async.org.uk/noc2006/pdf/Eby-Friedman.pdf]]
Eby Friedman, U of Rochester, United States
-[[Potential impact of emerging System-in-Packaging technologies on system design>http://async.org.uk/noc2006/pdf/Eric-Beyne.pdf]] Eric Beyne, IMEC, Belgium
----
[[NOCS 2011: The Fifth ACM/IEEE International Symposium on Networks-on-Chip>http://www.ece.cmu.edu/~sld/nocs2011/wiki/doku.php?id=start]]
Keynotes:
-[[On-Chip Interconnect in a Tile Manycore Processor: When the Rubber Meets the Road>http://www.ece.cmu.edu/~sld/nocs2011/wiki/lib/exe/fetch.php?w=326&media=keynote_anant.pdf]],
Anant Agarwal, Professor of Electrical Engineering and Computer Science, MIT, and Founder and CTO, Tilera Corporation
--this talk is based on an original paper entitled:[[''Remote Store Programming: Reflective Memory for Multicore>http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/F3_1015_Hoffmann_abstract.pdf]]''
-Integrating the Network: Why It Matters
Tryggve Fossum, Director of Microarchitecture Development, Intel
----
-O. Hammami, Ptech.
--http://www.ocpip.org/uploads/documents/IP08-XLOH-v1.pdf
--http://www.ocpip.org/uploads/dynamic_areas/Qi9uLmL6BcgpQjPI4EqT/372/DAC-DSNOC11-XLOH-P1-v2.pdf
--http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4802498 (The emulation platform is the Eve Zebu-UF4
Platform.)
---http://www.eve-team.com/ ([[Zebu-UF4 costs about 60,000$>http://www.eetimes.com/General/PrintView/4060863]])
--http://www.arteris.com/noc_solution (For NoC Generation)
***TSV [#l77a5caa]
1.(2014) [[TSV-to-TSV Inductive Coupling-Aware Coding Scheme for 3D Network-on-Chip>http://newport.eecs.uci.edu/~aeghbal/DFT2014.pdf]], Ashkan Eghbal, Pooria M.Yaghini, Siavash S.Yazdi, and Nader Bagherzadeh
Department of Electrical Engineering and Computer Science, University of California, Irvine.
2. (2013) [[A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network on Chip Links>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4681638&tag=1]], Igor Loi, , Subhasish Mitra,Thomas H. Lee, Shinobu Fujita, and Luca Benini, DEIS, University of Bologna, Bologna, Italy,Stanford University, California, Usa,Toshiba, San Jose, CA, USA (Kawasaki, Kanagawa, Japan)
3. [[Session 8: Emerging Technologies>http://webfs-int.u-aizu.ac.jp/~benab/doc/slides_Session%208%20Emerging%20Technologies.pdf]], Local copy.
----
Last update: Feb. 20, 2014.
終了行:
[[back to OASIS>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]]
*WWW Routers [#x37bbd3d]
- Kumar, A ; Dept. of Electr. Eng., Princeton Univ., Princeton, NJ ; Kundu, P. ; Singhx, A.P. ; Li-Shiuan Peh , [[A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4601881&tag=1]], ICCD 2007. 25th International Conference on Computer Design, 2007.
-http://hellojooyoung.com/res.php
*Blogs [#r1099e0f]
- NoC Blog http://networkonchip.wordpress.com/
*Simulators [#la2fbe14]
*** 1. NoC prototypes: full design data available [#a23a8b01]
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:
-[[CONfigurable NEtwork Creation Tool>http://www.cs.cmu.edu/~mpapamic/projects/connect.html]], Online BlueSpec SystemVerilog generator for NoCs that are “FPGA-friendly”, 2012
-[[NetMaker (University of Cambridge)>http://www-dyn.cl.cam.ac.uk/~rdm34/wiki/index.php?title=Main_Page]] – FPGA, 2009
-[[Open Noc (Linköpings Universitet)>http://www.da.isy.liu.se/research/soc/fpganoc/]] – FPGA, 2007
-[[Mini NoC (Technische Universiteit Eindhoven)>http://www.es.ele.tue.nl/mininoc/]] – FPGA, 2006
***2. NoC prototypes: partial/no/promised design data available [#l9759967]
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:
-[[Atlas>https://corfu.pucrs.br/redmine/projects/atlas]] (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
-[[NoCGen>http://tima-sls.imag.fr/www/research/nocgen]]: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
-[[NoCBench>http://www.tkt.cs.tut.fi/research/nocbench/download.html]], Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.
***3. Router prototypes [#w199112f]
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
-[[Open source NoC router>https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/Router]] (Stanford. A parameterized RTL implementation of a state-of-the-art VC router.) – 2013
* 3D Packaging In Japan [#jf807427]
-IEEE CPMT Society
http://www.cpmt.org/
-IEEE Japan Council
http://www.ieee-jp.org/japancouncil/index_e.htm
-Japan Institute of Electronics Packaging (JIEP)
http://www.e-jisso.jp/
-IMAPS:
http://www.imaps.org/
-Research Committee for 3D Integration by Low-temperature Bonding Technology
http://www.su.t.u-tokyo.ac.jp/~3dwb/committee/index-e.html
*Mis [#w0478a9b]
[[NoC2006 Keynotes>http://async.org.uk/noc2006/]]
- [[Keynote: NoCs: Vision, reality, trends>http://async.org.uk/noc2006/pdf/Luca-Benini.pdf]]
Luca Benini, DEIS - Bologna U, Italy
- [[Standards in NoC: What can we gain?>http://async.org.uk/noc2006/pdf/Luca-Benini.pdf]], Axel Jantsch, KTH Stockholm, Sweden
- [[Networks and Applications: Are Application-Specific Networks Worth the Trouble?>http://async.org.uk/noc2006/pdf/Wayne-Wolf.pdf]], Wayne Wolf, Princeton U, United States
-Advances in On-Chip Interconnects (invited presentations)
Chair: Pol Marchal, IMEC, Belgium
-[[On-Chip Interconnect: The past, present, and future>http://async.org.uk/noc2006/pdf/Eby-Friedman.pdf]]
Eby Friedman, U of Rochester, United States
-[[Potential impact of emerging System-in-Packaging technologies on system design>http://async.org.uk/noc2006/pdf/Eric-Beyne.pdf]] Eric Beyne, IMEC, Belgium
----
[[NOCS 2011: The Fifth ACM/IEEE International Symposium on Networks-on-Chip>http://www.ece.cmu.edu/~sld/nocs2011/wiki/doku.php?id=start]]
Keynotes:
-[[On-Chip Interconnect in a Tile Manycore Processor: When the Rubber Meets the Road>http://www.ece.cmu.edu/~sld/nocs2011/wiki/lib/exe/fetch.php?w=326&media=keynote_anant.pdf]],
Anant Agarwal, Professor of Electrical Engineering and Computer Science, MIT, and Founder and CTO, Tilera Corporation
--this talk is based on an original paper entitled:[[''Remote Store Programming: Reflective Memory for Multicore>http://www.ll.mit.edu/HPEC/agendas/proc09/Day2/F3_1015_Hoffmann_abstract.pdf]]''
-Integrating the Network: Why It Matters
Tryggve Fossum, Director of Microarchitecture Development, Intel
----
-O. Hammami, Ptech.
--http://www.ocpip.org/uploads/documents/IP08-XLOH-v1.pdf
--http://www.ocpip.org/uploads/dynamic_areas/Qi9uLmL6BcgpQjPI4EqT/372/DAC-DSNOC11-XLOH-P1-v2.pdf
--http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4802498 (The emulation platform is the Eve Zebu-UF4
Platform.)
---http://www.eve-team.com/ ([[Zebu-UF4 costs about 60,000$>http://www.eetimes.com/General/PrintView/4060863]])
--http://www.arteris.com/noc_solution (For NoC Generation)
***TSV [#l77a5caa]
1.(2014) [[TSV-to-TSV Inductive Coupling-Aware Coding Scheme for 3D Network-on-Chip>http://newport.eecs.uci.edu/~aeghbal/DFT2014.pdf]], Ashkan Eghbal, Pooria M.Yaghini, Siavash S.Yazdi, and Nader Bagherzadeh
Department of Electrical Engineering and Computer Science, University of California, Irvine.
2. (2013) [[A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network on Chip Links>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4681638&tag=1]], Igor Loi, , Subhasish Mitra,Thomas H. Lee, Shinobu Fujita, and Luca Benini, DEIS, University of Bologna, Bologna, Italy,Stanford University, California, Usa,Toshiba, San Jose, CA, USA (Kawasaki, Kanagawa, Japan)
3. [[Session 8: Emerging Technologies>http://webfs-int.u-aizu.ac.jp/~benab/doc/slides_Session%208%20Emerging%20Technologies.pdf]], Local copy.
----
Last update: Feb. 20, 2014.
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