OASIS-8C System
をテンプレートにして作成
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開始行:
CENTER:SIZE(60){COLOR(gold){OASIS-8C Processor of FPGA}}
*Project Goal [#f1f26636]
- Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
- [[Detailed Design Manual>http://aslweb.u-aizu.ac.jp/aslint/index.php?cmd=read&page=OASIS-8C%20System%20Design%20Manual&refer=OASIS-8C%20System]].
-Target Application: Image Recognition
***Members [#vc808259]
- Prof. Okuyama
-[[D1 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-[[B4 Akihito Kajikawa(梶川 聡仁)>Akihito Kajikawa]] (s1200017)
-[[B3 Ryunosuke Murakami(村上 龍之介)>Ryunosuke Murakami]] (s1210040)
-[[B3 Kaori Yatsu(谷津 香)>Kaori Yatsu]] (s1210103)
-[[B3 Nao Miyamoto(宮本 奈緒)>Nao Miyamoto]] (s1210060)
-[[B3 Hiroki Yomogita(蓬田 大貴)>Hiroki Yomogita]] (s1210042)
-[[B3 Yuji Murakami(村上 侑司)>Yuji Murakami]] (s1210019)
-[[B3 Kota Toyama(外山 幸太)>Kota Toyama]] (s1210201)
-[[B3 Yuga Inoue(井上優雅)>Yuga Inoue]] (s1210087)
*System Architecture [#e31ae400]
- 2x2x2 Network-on-Chip:
CENTER:[[&ref(top-level2.png,,60%);>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]
- Network's PE:
CENTER:[[&ref(tile-diagram.png,,60%);>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]
*Specification [#j83a3824]
- System specifications:
-- OASIS 3D Network-on-Chip [[[Ref.1]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]].
--- Topology: 3D Mesh.
--- Network's Size: 2x2x2.
--- Document & source code: [[[Ref.1]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]]
-- Network Interface: [[[Ref.2]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]].
-- Processing Elements: COLOR(red){(TBD)}
--- CPU: MIPS
--- MEM: On-chip (verilog code), Off-chip (see I/O).
--- I/O: Off-chip Memory, Display (LCD, LED), Inter-connection (UART/USB/PCI).
- Application specifications:COLOR(red){(TBD)}
-- Target CPU: MIPS.
-- Target applications: Image processing (filtering).
- Implementation environment:
-- Language: Verilog HDL.
-- Simulation tool: Modelsim Altera/Cadence Tools.
-- Implementation tool: Altera Quartus II/ASIC.
- Implementation board: Spartan DE II/CMOS 45 nm.
*Hardware Prototyping Tasks [#k85f0a2d]
- Task 01: Processor Implemenation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#z500141b]]
-- Understading the Processor architecture and operation.
-- Implementation of I/O accessing operation.
-- Simulation and implemenation.
- Task 02: Network-Interface Implemenation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#i355dc97]]
-- Establishing an individual network tile: PE(Processing Element) - NI(Network Interface) - R(Router).
-- Implemenation local interfacing.
-- Implementation on FPGA/ASIC.
- Task 03: Network Implementation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#a455cf7c]]
-- Establish a 2D 2x2x2 Network Implementation.
-- Network simulation.
-- Implementation on FPGA/ASIC.
- Task 04: Application Implementation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#abacf8c8]]
-- Establishing the algorithm base on network's architecture.
-- Application demonstration.
*Schedule [#y16f9bb9]
- Detail of schedule
|COLOR(blue){Step}|COLOR(blue){Content}|COLOR(blue){Start Date}|COLOR(blue){Finish Date}|COLOR(blue){Report}|
|1|COLOR(green){Design Preparation}|2015-June-02|2015-June-30|[[this page>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]|
|2|Group first meeting |2015-July-17|2015-July-17||
|3|Group meeting |COLOR(red){2015-Aug-10}|2015-Aug-10||
|4|Group meeting |COLOR(red){2015-Sep-28}|2015-Sep-28||
- Task Assignment (Step 02)
|COLOR(blue){No.}|COLOR(blue){Assignee}|COLOR(blue){Task}|COLOR(blue){Finish Date}|COLOR(blue){Note}|
|1|Khanh|COLOR(green){Prepare the schedule of the Project}|2015-Jun-19|-|
|2.1|H.Yomogita, Y.Inoue|Processor Implemenation|2015-09-28|-|
|2.2|R.Murakami, K.Toyama|Network-Interface Implemenation|2015-09-28|[[[document]>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]]|
|2.3|Y.Murakami |Network Implementation|2015-09-28|-|
|2.4|N.Miyamoto, K.Yatsu|Application Implementation|2015-09-28|-|
*References [#x829e368]
- [Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, [[Internal-link>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]], [[Source-code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]].
- [Ref.2]: Network Inteface, R. Okada, [[Internal-link>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]].
- [Ref.3]: FPGA manual (TBU).
- [Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/OASIS-8C/MIPS_MultiCycle.zip
----
Last Update:
- 2015 June 8th: Update system architecture diagram.
終了行:
CENTER:SIZE(60){COLOR(gold){OASIS-8C Processor of FPGA}}
*Project Goal [#f1f26636]
- Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
- [[Detailed Design Manual>http://aslweb.u-aizu.ac.jp/aslint/index.php?cmd=read&page=OASIS-8C%20System%20Design%20Manual&refer=OASIS-8C%20System]].
-Target Application: Image Recognition
***Members [#vc808259]
- Prof. Okuyama
-[[D1 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-[[B4 Akihito Kajikawa(梶川 聡仁)>Akihito Kajikawa]] (s1200017)
-[[B3 Ryunosuke Murakami(村上 龍之介)>Ryunosuke Murakami]] (s1210040)
-[[B3 Kaori Yatsu(谷津 香)>Kaori Yatsu]] (s1210103)
-[[B3 Nao Miyamoto(宮本 奈緒)>Nao Miyamoto]] (s1210060)
-[[B3 Hiroki Yomogita(蓬田 大貴)>Hiroki Yomogita]] (s1210042)
-[[B3 Yuji Murakami(村上 侑司)>Yuji Murakami]] (s1210019)
-[[B3 Kota Toyama(外山 幸太)>Kota Toyama]] (s1210201)
-[[B3 Yuga Inoue(井上優雅)>Yuga Inoue]] (s1210087)
*System Architecture [#e31ae400]
- 2x2x2 Network-on-Chip:
CENTER:[[&ref(top-level2.png,,60%);>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]
- Network's PE:
CENTER:[[&ref(tile-diagram.png,,60%);>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]
*Specification [#j83a3824]
- System specifications:
-- OASIS 3D Network-on-Chip [[[Ref.1]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]].
--- Topology: 3D Mesh.
--- Network's Size: 2x2x2.
--- Document & source code: [[[Ref.1]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]]
-- Network Interface: [[[Ref.2]>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System#x829e368]].
-- Processing Elements: COLOR(red){(TBD)}
--- CPU: MIPS
--- MEM: On-chip (verilog code), Off-chip (see I/O).
--- I/O: Off-chip Memory, Display (LCD, LED), Inter-connection (UART/USB/PCI).
- Application specifications:COLOR(red){(TBD)}
-- Target CPU: MIPS.
-- Target applications: Image processing (filtering).
- Implementation environment:
-- Language: Verilog HDL.
-- Simulation tool: Modelsim Altera/Cadence Tools.
-- Implementation tool: Altera Quartus II/ASIC.
- Implementation board: Spartan DE II/CMOS 45 nm.
*Hardware Prototyping Tasks [#k85f0a2d]
- Task 01: Processor Implemenation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#z500141b]]
-- Understading the Processor architecture and operation.
-- Implementation of I/O accessing operation.
-- Simulation and implemenation.
- Task 02: Network-Interface Implemenation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#i355dc97]]
-- Establishing an individual network tile: PE(Processing Element) - NI(Network Interface) - R(Router).
-- Implemenation local interfacing.
-- Implementation on FPGA/ASIC.
- Task 03: Network Implementation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#a455cf7c]]
-- Establish a 2D 2x2x2 Network Implementation.
-- Network simulation.
-- Implementation on FPGA/ASIC.
- Task 04: Application Implementation [[(manual)>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System%20Design%20Manual#abacf8c8]]
-- Establishing the algorithm base on network's architecture.
-- Application demonstration.
*Schedule [#y16f9bb9]
- Detail of schedule
|COLOR(blue){Step}|COLOR(blue){Content}|COLOR(blue){Start Date}|COLOR(blue){Finish Date}|COLOR(blue){Report}|
|1|COLOR(green){Design Preparation}|2015-June-02|2015-June-30|[[this page>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-8C%20System]]|
|2|Group first meeting |2015-July-17|2015-July-17||
|3|Group meeting |COLOR(red){2015-Aug-10}|2015-Aug-10||
|4|Group meeting |COLOR(red){2015-Sep-28}|2015-Sep-28||
- Task Assignment (Step 02)
|COLOR(blue){No.}|COLOR(blue){Assignee}|COLOR(blue){Task}|COLOR(blue){Finish Date}|COLOR(blue){Note}|
|1|Khanh|COLOR(green){Prepare the schedule of the Project}|2015-Jun-19|-|
|2.1|H.Yomogita, Y.Inoue|Processor Implemenation|2015-09-28|-|
|2.2|R.Murakami, K.Toyama|Network-Interface Implemenation|2015-09-28|[[[document]>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]]|
|2.3|Y.Murakami |Network Implementation|2015-09-28|-|
|2.4|N.Miyamoto, K.Yatsu|Application Implementation|2015-09-28|-|
*References [#x829e368]
- [Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, [[Internal-link>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]], [[Source-code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]].
- [Ref.2]: Network Inteface, R. Okada, [[Internal-link>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]].
- [Ref.3]: FPGA manual (TBU).
- [Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/OASIS-8C/MIPS_MultiCycle.zip
----
Last Update:
- 2015 June 8th: Update system architecture diagram.
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