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開始行:
[[OASIS]]
-1. COLOR(blue){''Performance Study and Evaluation of OASIS Network-on-Chip on FPGA'' (1名)}
-2. COLOR(blue){Hardware and Software Optimization Techniques for OASIS NoC (OASISネットワークオンチップのハード/ソフトウェア最適化技術に関する研究 : 1名 )}
-3. COLOR(blue){Architecture and Design of Core Network Interface for Source Routing (ソースルーティング機能実装にむけてのネットワークインターフェースコア部分のアーキテクチャと設計: 1名)}
-4. COLOR(blue){Power investigation of Heterogeneous Multicore System (マルチコア消費電力に関する研究 : 1名 )}
//-5. COLOR(blue){Design and Evaluation of Efficient Error Detection and Correction mechanism for OASIS 3D-NoC)}
-5. [[Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC>Mitsunari Ishii]], COLOR(red){B4 Mitsunari Ishii}
-6. [[Design and Evaluation of 3D-OASIS-NoC Matrix Processor>http://aslweb.u-aizu.ac.jp/aslint/index.php?Mitsuhiro%20Nakamura]], COLOR(red){M1 Mitsuhiro Nakamura}
-7. [[Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Yuki-Tanaka]], COLOR(red){B4 Yuki Tanaka}
-8. [[Error Detection & Correction Mechanism Based on Router-to-Router Approach>OASIS-Project]]
-9. [[Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akihito%20Kajikawa]] --> COLOR(green){B4 Akihito Kajikawa(梶川 聡仁)}
終了行:
[[OASIS]]
-1. COLOR(blue){''Performance Study and Evaluation of OASIS Network-on-Chip on FPGA'' (1名)}
-2. COLOR(blue){Hardware and Software Optimization Techniques for OASIS NoC (OASISネットワークオンチップのハード/ソフトウェア最適化技術に関する研究 : 1名 )}
-3. COLOR(blue){Architecture and Design of Core Network Interface for Source Routing (ソースルーティング機能実装にむけてのネットワークインターフェースコア部分のアーキテクチャと設計: 1名)}
-4. COLOR(blue){Power investigation of Heterogeneous Multicore System (マルチコア消費電力に関する研究 : 1名 )}
//-5. COLOR(blue){Design and Evaluation of Efficient Error Detection and Correction mechanism for OASIS 3D-NoC)}
-5. [[Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC>Mitsunari Ishii]], COLOR(red){B4 Mitsunari Ishii}
-6. [[Design and Evaluation of 3D-OASIS-NoC Matrix Processor>http://aslweb.u-aizu.ac.jp/aslint/index.php?Mitsuhiro%20Nakamura]], COLOR(red){M1 Mitsuhiro Nakamura}
-7. [[Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Yuki-Tanaka]], COLOR(red){B4 Yuki Tanaka}
-8. [[Error Detection & Correction Mechanism Based on Router-to-Router Approach>OASIS-Project]]
-9. [[Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akihito%20Kajikawa]] --> COLOR(green){B4 Akihito Kajikawa(梶川 聡仁)}
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