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開始行:
CENTER:[[HIGH-PERFORMANCE RELIABLE INTERCONNECT TECHNOLOGIES FOR NOCS AND COGNITIVE SOCS>https://adaptive.u-aizu.ac.jp/aslwp/wp-admin/post.php?post=564&action=edit]]
CENTER:SIZE(60){COLOR(green){OASIS-2: Reliable Network-on-Chip Project}}
CENTER:[[oasis-bib.tex>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS%20Bib]]
----
#CONTENTS
----
*Project Overview [#x419b03d]
Future embedded and general-purpose processors will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today's nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide high throughput and low latency while keeping area and power consumption low.
Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
CENTER:&ref(oasis.png,,30%);
//***Look ahead Routing Algorithm for Distributed Routing [#f2f55b68]
////[[Look ahead routing>http://aslweb.u-aizu.ac.jp/benlab/index.php?look-//ahead%20routing%20technique]]
*Members [#oa205888]
-Leader: [[D2 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-Members (current and former): [[D3 Akram>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akram%20Ben%20Ahmed]], [[B4 Mitsunari Ishii>Mitsunari Ishii]] (s1190124),
[[B4 Yuki Tanaka>Yuki-Tanaka]] (s1190130), Endou, Uesaka, Mori, Miura
*Group Publications [#x5756510]
-Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran, [[''A Soft-Error Resilient 3D Network-on-Chip Router''>http://dx.doi.org/doi:10.13140/RG.2.1.2952.2403]], COLOR(olive){Proc. of IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), pp. 84 - 90, Sep. 22-24, 2015.}[[[Slides.pdf>http://www.u-aizu.ac.jp/~benab/publications/conferences/ICAST2015/ser-3dr_slide_final.pdf]]]
-Abderazek Ben Abdallah, Mitsuhiro Nakamura, Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, [[''Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems''>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]], COLOR(olive){Proc. of the 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 29-31, 2015, Okinawa, Japan.}
-Akram Ben Ahmed, ''High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems'', Doctoral Thesis Preliminary Presentation, October 20, 2014. [[[slides.pptx>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD/Prelim_Oct202014.pptx]]]
-A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ''Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems'' , COLOR(olive){IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.}
//>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/4305a197.pdf]]
-A. Ben Ahmed, A. Ben Abdallah, [[''OASIS 3D-Router Hardware Physical Design''>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-Akram Ben Ahmed, A. Ben Abdallah, [[''Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures''>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/JPDC14/JPDC-preprint.pdf]], Journal of Parallel and Distributed Computing, 2014. [[[DOI>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]]
- Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, ''Deadlock Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures'', IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp., 2013.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6657906&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6657884%29]]]
-Akram Ben Ahmed, A. Ben Abdallah, [[''Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip''>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super13/super13_preprint.pdf]], The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532.
[[[DOI>http://link.springer.com/article/10.1007%2Fs11227-013-0940-9]]]
-Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ''Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era'', ''' IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.'''
[[[DOI>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6603929]]]
-Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ''Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era'', Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.
//2012
-Akram Ben Ahmed, A. Ben Abdallah, ''Low-overhead Routing Algorithm for 3D Network-on-Chip'', '''IEEE Proc. of the The Third International Conference on Networking and Computing (ICNC'12), pp. 23-32, 2012.'''
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6424540]]]
- Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture'', '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6354695]]]
-Akram Ben Ahmed, A. Ben Abdallah,
''ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications'', '''IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6469623]]
-A. Ben Ahmed, A. Ben Abdallah, K. Kuroda,''Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC'', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award)
([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram-slides.pdf]]), ([[Papers>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram.pdf]])
-K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanced Design Issues for OASIS Network-on-Chip Architecture'', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. ([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori-slides.pdf]]); ([[Paper>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori.pdf]])
-Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, [[''設計空間探索とMCSoCの生成に適しているparameterizable NoC (PNoC)のハードウェア設計と事前評価''>http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/PARTHENON2009/s1140204_PARTHENON2009.pdf]], 第34回パルテノン研究会, pp.105-108. Aug. 2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/PARTHENON2009/s1140204_PARTHENON2009.ppt,,SLIDE);
-Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, [[''PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration''>http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/FAN2009/s1140204_FAN2009.pdf]], The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/FAN2009/s1140204_FAN2009.ppt,,SLIDE);
-Kenichi Mori, Abderazek Ben Abdallah, Kenichi Kuroda, [[''Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA''>http://aslweb.u-aizu.ac.jp/~s1140210/2009/FAN2009/s1140210_FAN2009.pdf]], The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140210/2009/FAN2009/s1140210_fan.pptx,,SLIDE);
-A. Ben Abdallah, T. Yoshinaga and M. Sowa,''Mathematical Model for Multiobjective Synthesis of NoC Architectures'', IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. ([[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/ICPP2007/Ben-Abderazek-NoCSynthesis.pdf]])
-A. Ben Abdallah, Masahiro Sowa, ''Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization'', JASSST2006, Dec. 4-9th, 2006. ([[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/TJASSST2006/TJASSST2006_manuscript.pdf]])
***Theses [#dd9ab7af]
-Kajikawa, Akihito, ''Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016. [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kaikawa-BS-16-gt.pdf]] , [[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kaikawa-BS-16-slides.pdf]],
-A. Ben Ahmed, ''High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems'', PhD Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD-15/AkramBenAhmed_Thesis_2015.pdf]]
-Mitsunari Ishii, ''Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Ishi-BS-2015/GT2015_Ishii_Final_Slide.pdf]], [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Ishi-BS-2015/GT2015_MitsunariIshii_Thesis.pdf]]
-Yuuki Tanaka, ''Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YukiTanaka_slides_Final.pdf]], [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YuukiTanaka_Final.pdf]]
-Shuu Endou, ''Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture'', Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu, Feb. 2013 ([[slides>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Endou-BS-12/s1170180_GT2012_slides.pdf]])
-Ryuya Okada,A. Ben Abdallah,[[''Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011.pdf]], Graduation Thesis, The University of Aizu, Feb. 2012. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011-slides.pdf]], [[Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]]
-Kenichi Mori,A. Ben Abdallah, [[''OASIS Network-on-Chip Prototyping on FPGA''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012.[[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_slides.pdf]], [[technical report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_tr.pdf]]
''
-Ben Ahmed Akram, A. Ben Abdallah,[[''On the Design of a 3D Network-on-Chip for Many-core SoC'' >http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-Shohei Miura,A. Ben Abdallah,[[''Efficient Design Method for NoC using Monitoring Mechanism:Parameterziable Network-on-Chip''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_thesis.pdf]] Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_slides.pdf]], [[technical report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_tr.pdf]]
***Technical Reports and Tutorials [#n31314f3]
-Kajikawa, Akihito, [[Introduction of OASIS NoC Part 1>https://drive.google.com/file/d/0B2HMlO4p7SuwQmdJQlF1MGFPZjg/view?usp=sharing]]; [[Introduction of OASIS NoC Part 2>https://drive.google.com/file/d/0B2HMlO4p7SuwX2ljTnFQNTQ5ZEE/view?usp=sharing]], Guidance Lecture, ASL, June 2016.
-Kajikawa, Akihito, Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System, TR, School of Computer Science and Engineering, The University of Aizu, March 2016. [[Technical Report>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kajikawa-TR-2016.pdf]]
-Akram Ben Ahmed et al. [[''OASIS 3D Fault Tolerant Router Hardware Physical Design with TSVs''>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-3DFTRV1_Design_Tutorial_05282015.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, May 28, 2015.
-Akram Ben Ahmed, [[OASIS 3D-Router Hardware Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-Ben Ahmed Akram, A. Ben Abdallah, [[On the Design of a 3D Network-on-Chip for Many-core SoC>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_TR.pdf]], COLOR(olive){Technical Report, The University of Aizu, Feb. 2012.}
- R. Okada, [[Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]], Technical Report, ASL- Parallel Architecture Group, School of Computer Science and Engineering, The University of Aizu, March 2012.
- T. Uesaka, OASIS NoC Topology Optimization with Short-Path Link, Technical Report, Systems Architecture Group,March 2011.[[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-SPL_Technical_report_2010.pdf]]
- K. Mori, A. Ben Abdallah, OASIS NoC Architecture Design in Verilog HDL, Technical Report,TR-062010-OASIS, Adaptive Systems Laboratory, the University of Aizu, June 2010.
[[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/oasis-noc-design-2010.pdf]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
//--'''[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/OASIS.pdf]]''',
//--'''[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/OASIS.zip]]'''
***Benchmark suite [#c4629d5d]
-[[JPEG; Matrix multiplication; Transpose traffic pattern; Uniform traffic pattern>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]];
-'''[[ppt>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchmarks.ppt]]'''
***Figure [#cab71472]
- Internal link: [[FIGS.ppt>http://aslweb.u-aizu.ac.jp/aslint/index.php?plugin=attach&pcmd=open&file=FT3Drouter_all_figures_source.pptx&refer=OASIS]]
//***References: [#r1e98c17]
//-[[OASIS-LINKS>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-LINKS]]
*Related Projects [#h84a6372]
-[[OASIS-FMS1]]
-[[OASIS-8C System]]
*Available/On-going Research Topics:(現在募集中) [#w0742390]
http://adaptive.u-aizu.ac.jp/aslint/index.php?OASIS%20New%20Topics
*Reliable CPUs/Cores [#nb054597]
-[[LEON3FT>http://www.gaisler.com/index.php/products/processors/leon3ft]]: The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct (SEU) errors in all on-chip RAM memories.
-[[Xilinx space>http://www.xilinx.com/applications/aerospace-and-defense/space.html]]: Xilinx space-grade products are leading the aerospace industry to a new era of re-programmability and performance. The All Programmable portfolio of rad-hard and rad-tolerant re-configurable FPGAs and configuration memories provide unmatched reliability, flexibility, density and system level architectures that enable unparalleled design cycle and cost benefits for space systems.
終了行:
CENTER:[[HIGH-PERFORMANCE RELIABLE INTERCONNECT TECHNOLOGIES FOR NOCS AND COGNITIVE SOCS>https://adaptive.u-aizu.ac.jp/aslwp/wp-admin/post.php?post=564&action=edit]]
CENTER:SIZE(60){COLOR(green){OASIS-2: Reliable Network-on-Chip Project}}
CENTER:[[oasis-bib.tex>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS%20Bib]]
----
#CONTENTS
----
*Project Overview [#x419b03d]
Future embedded and general-purpose processors will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today's nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide high throughput and low latency while keeping area and power consumption low.
Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
CENTER:&ref(oasis.png,,30%);
//***Look ahead Routing Algorithm for Distributed Routing [#f2f55b68]
////[[Look ahead routing>http://aslweb.u-aizu.ac.jp/benlab/index.php?look-//ahead%20routing%20technique]]
*Members [#oa205888]
-Leader: [[D2 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-Members (current and former): [[D3 Akram>http://aslweb.u-aizu.ac.jp/aslint/index.php?Akram%20Ben%20Ahmed]], [[B4 Mitsunari Ishii>Mitsunari Ishii]] (s1190124),
[[B4 Yuki Tanaka>Yuki-Tanaka]] (s1190130), Endou, Uesaka, Mori, Miura
*Group Publications [#x5756510]
-Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran, [[''A Soft-Error Resilient 3D Network-on-Chip Router''>http://dx.doi.org/doi:10.13140/RG.2.1.2952.2403]], COLOR(olive){Proc. of IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), pp. 84 - 90, Sep. 22-24, 2015.}[[[Slides.pdf>http://www.u-aizu.ac.jp/~benab/publications/conferences/ICAST2015/ser-3dr_slide_final.pdf]]]
-Abderazek Ben Abdallah, Mitsuhiro Nakamura, Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, [[''Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems''>http://dx.doi.org/doi:10.13140/RG.2.1.1272.8809]], COLOR(olive){Proc. of the 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 29-31, 2015, Okinawa, Japan.}
-Akram Ben Ahmed, ''High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems'', Doctoral Thesis Preliminary Presentation, October 20, 2014. [[[slides.pptx>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD/Prelim_Oct202014.pptx]]]
-A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ''Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems'' , COLOR(olive){IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.}
//>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/MCSOC2014/4305a197.pdf]]
-A. Ben Ahmed, A. Ben Abdallah, [[''OASIS 3D-Router Hardware Physical Design''>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-Akram Ben Ahmed, A. Ben Abdallah, [[''Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures''>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/JPDC14/JPDC-preprint.pdf]], Journal of Parallel and Distributed Computing, 2014. [[[DOI>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]]
- Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, ''Deadlock Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures'', IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp., 2013.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6657906&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6657884%29]]]
-Akram Ben Ahmed, A. Ben Abdallah, [[''Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip''>http://web-ext.u-aizu.ac.jp/~benab/publications/journals/super13/super13_preprint.pdf]], The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532.
[[[DOI>http://link.springer.com/article/10.1007%2Fs11227-013-0940-9]]]
-Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ''Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era'', ''' IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.'''
[[[DOI>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6603929]]]
-Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ''Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era'', Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.
//2012
-Akram Ben Ahmed, A. Ben Abdallah, ''Low-overhead Routing Algorithm for 3D Network-on-Chip'', '''IEEE Proc. of the The Third International Conference on Networking and Computing (ICNC'12), pp. 23-32, 2012.'''
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6424540]]]
- Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture'', '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6354695]]]
-Akram Ben Ahmed, A. Ben Abdallah,
''ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications'', '''IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6469623]]
-A. Ben Ahmed, A. Ben Abdallah, K. Kuroda,''Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC'', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award)
([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram-slides.pdf]]), ([[Papers>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram.pdf]])
-K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanced Design Issues for OASIS Network-on-Chip Architecture'', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. ([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori-slides.pdf]]); ([[Paper>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori.pdf]])
-Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, [[''設計空間探索とMCSoCの生成に適しているparameterizable NoC (PNoC)のハードウェア設計と事前評価''>http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/PARTHENON2009/s1140204_PARTHENON2009.pdf]], 第34回パルテノン研究会, pp.105-108. Aug. 2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/PARTHENON2009/s1140204_PARTHENON2009.ppt,,SLIDE);
-Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, [[''PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration''>http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/FAN2009/s1140204_FAN2009.pdf]], The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140204/2009/RPS/FAN2009/s1140204_FAN2009.ppt,,SLIDE);
-Kenichi Mori, Abderazek Ben Abdallah, Kenichi Kuroda, [[''Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA''>http://aslweb.u-aizu.ac.jp/~s1140210/2009/FAN2009/s1140210_FAN2009.pdf]], The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.
&ref(http://aslweb.u-aizu.ac.jp/~s1140210/2009/FAN2009/s1140210_fan.pptx,,SLIDE);
-A. Ben Abdallah, T. Yoshinaga and M. Sowa,''Mathematical Model for Multiobjective Synthesis of NoC Architectures'', IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. ([[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/ICPP2007/Ben-Abderazek-NoCSynthesis.pdf]])
-A. Ben Abdallah, Masahiro Sowa, ''Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization'', JASSST2006, Dec. 4-9th, 2006. ([[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/TJASSST2006/TJASSST2006_manuscript.pdf]])
***Theses [#dd9ab7af]
-Kajikawa, Akihito, ''Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016. [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kaikawa-BS-16-gt.pdf]] , [[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kaikawa-BS-16-slides.pdf]],
-A. Ben Ahmed, ''High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems'', PhD Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD-15/AkramBenAhmed_Thesis_2015.pdf]]
-Mitsunari Ishii, ''Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Ishi-BS-2015/GT2015_Ishii_Final_Slide.pdf]], [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Ishi-BS-2015/GT2015_MitsunariIshii_Thesis.pdf]]
-Yuuki Tanaka, ''Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC'', Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [[slides.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YukiTanaka_slides_Final.pdf]], [[Thesis.pdf>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Tanaka-BS-2015/GT2015_YuukiTanaka_Final.pdf]]
-Shuu Endou, ''Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture'', Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu, Feb. 2013 ([[slides>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Endou-BS-12/s1170180_GT2012_slides.pdf]])
-Ryuya Okada,A. Ben Abdallah,[[''Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011.pdf]], Graduation Thesis, The University of Aizu, Feb. 2012. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011-slides.pdf]], [[Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]]
-Kenichi Mori,A. Ben Abdallah, [[''OASIS Network-on-Chip Prototyping on FPGA''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012.[[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_slides.pdf]], [[technical report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_tr.pdf]]
''
-Ben Ahmed Akram, A. Ben Abdallah,[[''On the Design of a 3D Network-on-Chip for Many-core SoC'' >http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-Shohei Miura,A. Ben Abdallah,[[''Efficient Design Method for NoC using Monitoring Mechanism:Parameterziable Network-on-Chip''>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_thesis.pdf]] Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_slides.pdf]], [[technical report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Miura-MS-11/m5141118_2011_MS_tr.pdf]]
***Technical Reports and Tutorials [#n31314f3]
-Kajikawa, Akihito, [[Introduction of OASIS NoC Part 1>https://drive.google.com/file/d/0B2HMlO4p7SuwQmdJQlF1MGFPZjg/view?usp=sharing]]; [[Introduction of OASIS NoC Part 2>https://drive.google.com/file/d/0B2HMlO4p7SuwX2ljTnFQNTQ5ZEE/view?usp=sharing]], Guidance Lecture, ASL, June 2016.
-Kajikawa, Akihito, Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System, TR, School of Computer Science and Engineering, The University of Aizu, March 2016. [[Technical Report>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Kajikawa-BS-16/Kajikawa-TR-2016.pdf]]
-Akram Ben Ahmed et al. [[''OASIS 3D Fault Tolerant Router Hardware Physical Design with TSVs''>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-3DFTRV1_Design_Tutorial_05282015.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, May 28, 2015.
-Akram Ben Ahmed, [[OASIS 3D-Router Hardware Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-Ben Ahmed Akram, A. Ben Abdallah, [[On the Design of a 3D Network-on-Chip for Many-core SoC>http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_TR.pdf]], COLOR(olive){Technical Report, The University of Aizu, Feb. 2012.}
- R. Okada, [[Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]], Technical Report, ASL- Parallel Architecture Group, School of Computer Science and Engineering, The University of Aizu, March 2012.
- T. Uesaka, OASIS NoC Topology Optimization with Short-Path Link, Technical Report, Systems Architecture Group,March 2011.[[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-SPL_Technical_report_2010.pdf]]
- K. Mori, A. Ben Abdallah, OASIS NoC Architecture Design in Verilog HDL, Technical Report,TR-062010-OASIS, Adaptive Systems Laboratory, the University of Aizu, June 2010.
[[PDF>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/oasis-noc-design-2010.pdf]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
//--'''[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/OASIS.pdf]]''',
//--'''[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/OASIS.zip]]'''
***Benchmark suite [#c4629d5d]
-[[JPEG; Matrix multiplication; Transpose traffic pattern; Uniform traffic pattern>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]];
-'''[[ppt>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchmarks.ppt]]'''
***Figure [#cab71472]
- Internal link: [[FIGS.ppt>http://aslweb.u-aizu.ac.jp/aslint/index.php?plugin=attach&pcmd=open&file=FT3Drouter_all_figures_source.pptx&refer=OASIS]]
//***References: [#r1e98c17]
//-[[OASIS-LINKS>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS-LINKS]]
*Related Projects [#h84a6372]
-[[OASIS-FMS1]]
-[[OASIS-8C System]]
*Available/On-going Research Topics:(現在募集中) [#w0742390]
http://adaptive.u-aizu.ac.jp/aslint/index.php?OASIS%20New%20Topics
*Reliable CPUs/Cores [#nb054597]
-[[LEON3FT>http://www.gaisler.com/index.php/products/processors/leon3ft]]: The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct (SEU) errors in all on-chip RAM memories.
-[[Xilinx space>http://www.xilinx.com/applications/aerospace-and-defense/space.html]]: Xilinx space-grade products are leading the aerospace industry to a new era of re-programmability and performance. The All Programmable portfolio of rad-hard and rad-tolerant re-configurable FPGAs and configuration memories provide unmatched reliability, flexibility, density and system level architectures that enable unparalleled design cycle and cost benefits for space systems.
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