Multicore
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開始行:
CENTER:SIZE(50){COLOR(green){The Multicore Platform}}
----
''0. Motivation and Goal: ''
Multicore architectures have recently become focus of many researchers due to the growing interest in thread-level-parallelism. This is a natural response on the diminishing performance improvement in exploiting ILP.
Embedded computing has recently reached high performance levels, becoming more and more present in appliances used in everyday life. A wide variety of applications, from consumer electronics to biomedical systems, requires building up powerful yet cheap embedded devices.
Design of embedded systems must take into account a wide variety of constraints: performance, code size, power consumption, presence of real-time tasks, security and scalability. In this scenario, solutions should be investigated at different levels of abstraction.
A dedicated multicore system can be easily developed and prototyped by putting it on a single FPGA (e.g. Stratix or Cyclone from Altera) for various high performance multimedia applications
The goal of this project is to design a multi‐core system implemented on a single FPGA. The goals of the design are to provide a system that could be easily modified for “What if?” experiments and which could be made available to the academic community for research purposes.
CENTER:&ref(niosii-cyclone3angled.jpg,,70%);
CENTER:&ref(vcam.jpg,,70%);
1.''目的'':
組み込みコンピューティングは近年高性能なレベルに達し、ますます日常生活で使われる機器に使われるようになりました。電子工学から生物医学のような多種多様なアプリケーションは、強力で安い組み込みデバイスを必要としています。
組み込みシステムのデザインはパフォーマンス、コードサイズ、消費電力、リアルタイムタスクの存在、セキュリティとスケーラリビティ等の多種多様な制約を考慮しなければなりません。このシナリオでは、解決策は抽象概念のレベルの違いで調査されるべきです。
専用のマルチコアシステムはシングルFPGA(アルテラ社のStratixやCyclone等)で動作させることによって、容易にいろいろなハイパフォーマンスなマルチメディアアプリケーションの開発や原型を作ることができます。
このプロジェクトのゴールは、シングルFPGA上で実装されるマルチコアシステムを設計することです。デザインのゴールは、"こうしたらどうなるか?"の実験のために容易に修正されることができたり、研究目的のために学界で利用されるようなシステムを提供することです。
//COLOR(#5BFF00):''Please add Japanese translation here''
''2. Members'':
-Junichi Kato, [[Architecture and Design of Shared Memory Multi-QueueCore Processor, GT thesis, Feb. 2011.>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/graduation_thesis_final_edition.pdf]]
-Tomotaka Kasahara, [[ 研究テーマ: Design and Implementation of a Multicore System on a single FPGA>http://aslweb.u-aizu.ac.jp/benlab/index.php?Internal%2FKasahara]].
''3. References for my Research'':
- http://www.design-reuse.com/articles/21583/processor-noc-fpga.html
-Shunichi Kato, [[Shared Memory MultiQueueCore Processor Design>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/graduation_thesis_final_edition.pdf]],Graduation Thesis, The University of Aizu, Feb. 2011. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/s1150059_GT2010.ppt]]
- H. Hoshino, [[QSoC - Queue System on Chip on FPGA>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QSoC/doc/QSoC32_specification.pdf]], Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Jan. 2010.
-[[CUDA training>http://developer.nvidia.com/cuda-training]]
--[[CUDA toolkit>http://developer.nvidia.com/cuda-downloads]]
-[[Understanding the Performance of Multicore system with a Multicore Simulator>http://www.cs.virginia.edu/~cx7m/index%20files/Computer%20Architecture%20Report.pdf]]
-[[Low Power Design>http://aslweb.u-aizu.ac.jp/benlab/index.php?Low-Power-Design]]
-[[WWW-multicore>http://aslweb.u-aizu.ac.jp/benlab/index.php?www-multicore]]
----
*** RENESAS [#j6672796]
-[[Starter Kit in Japanese>http://japan.renesas.com/products/tools/introductory_tools/renesas_starter_kits/rsk_rx62n/index.jsp]]
-[[Starter Kit in English>http://am.renesas.com/products/tools/introductory_evaluation_tools/renesas_starter_kits/rsk_rx62n/]]
-[[Kit tutorial >http://documentation.renesas.com/doc/products/tool/reg10j0005_rskm16c29_tutorial.pdf]]
***uC/OS II on Nios II [#fb0a757c]
-[[Nios II>http://www.altera.com/literature/lit-nio2.jsp?GSA_pos=1&WT.oss_r=1&WT.oss=Nios%20II%20Literature]]
-[[Using MicroC/OS-II RTOS with the Nios II Processor Tutorial>http://www.altera.com/literature/tt/tt_nios2_MicroC_OSII_tutorial.pdf]]
-[[10.MicroC/OS-II Real-Time Operating System>http://www.altera.com/literature/hb/nios2/n2sw_nii52008.pdf]]
----
*** Soft Cores [#b5944234]
-All available commercial Soft cores http://www.1-core.com/library/digital/soft-cpu-cores/
----
***HW/SW Verification Tool [#o98a334b]
CENTER:&ref(Zebu-design-flow.gif,,100%);
CENTER:[[See Data-Sheet>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=zebu-server-ds.zip&refer=Internal%2FMULTICORE]]
--[[48-way Multiprocessor with NOC Using Zibo-Server>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=MP_with_NoC_parisTECH2008_Verification_ZiBo-Server.pdf&refer=Internal%2FMULTICORE]]
---[[See Demo>http://www.eve-team.com/zsosivp/]]
---[[Arteris NoC Company >http://www.arteris.com/]]
--[[Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Chip on Multi-FPGA>http://www.design-reuse.com/articles/27711/ocp-ip-compliant-64-node-butterfly-network-on-chip-on-multi-fpga.html]]
*Simulators [#c45de38f]
-http://code.google.com/p/macsim/ - CPU-GPU sim
--[[GEM5 (M5)>http://gem5.org/Main_Page]]
---[[ read tutorial>http://www.gem5.org/dist/tutorials/isca_pres_2011.pdf]]
---[[GEM5 publications>http://gem5.org/Publications]]
*Mis [#t605a431]
-http://aslweb.u-aizu.ac.jp/aslint/index.php?www-multicore
-[[MCSoC TPC>http://aslweb.u-aizu.ac.jp/aslint/index.php?MCSoC%20TPCs]]
*Courses [#r1307293]
-[[Parallel Systems, DVA336, Autumn 2017>http://www.idt.mdh.se/kurser/dva336/]]
-[[Parallel Systems>http://parallel.vub.ac.be/education/parsys/]]
終了行:
CENTER:SIZE(50){COLOR(green){The Multicore Platform}}
----
''0. Motivation and Goal: ''
Multicore architectures have recently become focus of many researchers due to the growing interest in thread-level-parallelism. This is a natural response on the diminishing performance improvement in exploiting ILP.
Embedded computing has recently reached high performance levels, becoming more and more present in appliances used in everyday life. A wide variety of applications, from consumer electronics to biomedical systems, requires building up powerful yet cheap embedded devices.
Design of embedded systems must take into account a wide variety of constraints: performance, code size, power consumption, presence of real-time tasks, security and scalability. In this scenario, solutions should be investigated at different levels of abstraction.
A dedicated multicore system can be easily developed and prototyped by putting it on a single FPGA (e.g. Stratix or Cyclone from Altera) for various high performance multimedia applications
The goal of this project is to design a multi‐core system implemented on a single FPGA. The goals of the design are to provide a system that could be easily modified for “What if?” experiments and which could be made available to the academic community for research purposes.
CENTER:&ref(niosii-cyclone3angled.jpg,,70%);
CENTER:&ref(vcam.jpg,,70%);
1.''目的'':
組み込みコンピューティングは近年高性能なレベルに達し、ますます日常生活で使われる機器に使われるようになりました。電子工学から生物医学のような多種多様なアプリケーションは、強力で安い組み込みデバイスを必要としています。
組み込みシステムのデザインはパフォーマンス、コードサイズ、消費電力、リアルタイムタスクの存在、セキュリティとスケーラリビティ等の多種多様な制約を考慮しなければなりません。このシナリオでは、解決策は抽象概念のレベルの違いで調査されるべきです。
専用のマルチコアシステムはシングルFPGA(アルテラ社のStratixやCyclone等)で動作させることによって、容易にいろいろなハイパフォーマンスなマルチメディアアプリケーションの開発や原型を作ることができます。
このプロジェクトのゴールは、シングルFPGA上で実装されるマルチコアシステムを設計することです。デザインのゴールは、"こうしたらどうなるか?"の実験のために容易に修正されることができたり、研究目的のために学界で利用されるようなシステムを提供することです。
//COLOR(#5BFF00):''Please add Japanese translation here''
''2. Members'':
-Junichi Kato, [[Architecture and Design of Shared Memory Multi-QueueCore Processor, GT thesis, Feb. 2011.>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/graduation_thesis_final_edition.pdf]]
-Tomotaka Kasahara, [[ 研究テーマ: Design and Implementation of a Multicore System on a single FPGA>http://aslweb.u-aizu.ac.jp/benlab/index.php?Internal%2FKasahara]].
''3. References for my Research'':
- http://www.design-reuse.com/articles/21583/processor-noc-fpga.html
-Shunichi Kato, [[Shared Memory MultiQueueCore Processor Design>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/graduation_thesis_final_edition.pdf]],Graduation Thesis, The University of Aizu, Feb. 2011. [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Kato-BS-10/s1150059_GT2010.ppt]]
- H. Hoshino, [[QSoC - Queue System on Chip on FPGA>http://web-ext.u-aizu.ac.jp/~benab/research/projects/QSoC/doc/QSoC32_specification.pdf]], Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Jan. 2010.
-[[CUDA training>http://developer.nvidia.com/cuda-training]]
--[[CUDA toolkit>http://developer.nvidia.com/cuda-downloads]]
-[[Understanding the Performance of Multicore system with a Multicore Simulator>http://www.cs.virginia.edu/~cx7m/index%20files/Computer%20Architecture%20Report.pdf]]
-[[Low Power Design>http://aslweb.u-aizu.ac.jp/benlab/index.php?Low-Power-Design]]
-[[WWW-multicore>http://aslweb.u-aizu.ac.jp/benlab/index.php?www-multicore]]
----
*** RENESAS [#j6672796]
-[[Starter Kit in Japanese>http://japan.renesas.com/products/tools/introductory_tools/renesas_starter_kits/rsk_rx62n/index.jsp]]
-[[Starter Kit in English>http://am.renesas.com/products/tools/introductory_evaluation_tools/renesas_starter_kits/rsk_rx62n/]]
-[[Kit tutorial >http://documentation.renesas.com/doc/products/tool/reg10j0005_rskm16c29_tutorial.pdf]]
***uC/OS II on Nios II [#fb0a757c]
-[[Nios II>http://www.altera.com/literature/lit-nio2.jsp?GSA_pos=1&WT.oss_r=1&WT.oss=Nios%20II%20Literature]]
-[[Using MicroC/OS-II RTOS with the Nios II Processor Tutorial>http://www.altera.com/literature/tt/tt_nios2_MicroC_OSII_tutorial.pdf]]
-[[10.MicroC/OS-II Real-Time Operating System>http://www.altera.com/literature/hb/nios2/n2sw_nii52008.pdf]]
----
*** Soft Cores [#b5944234]
-All available commercial Soft cores http://www.1-core.com/library/digital/soft-cpu-cores/
----
***HW/SW Verification Tool [#o98a334b]
CENTER:&ref(Zebu-design-flow.gif,,100%);
CENTER:[[See Data-Sheet>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=zebu-server-ds.zip&refer=Internal%2FMULTICORE]]
--[[48-way Multiprocessor with NOC Using Zibo-Server>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=MP_with_NoC_parisTECH2008_Verification_ZiBo-Server.pdf&refer=Internal%2FMULTICORE]]
---[[See Demo>http://www.eve-team.com/zsosivp/]]
---[[Arteris NoC Company >http://www.arteris.com/]]
--[[Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Chip on Multi-FPGA>http://www.design-reuse.com/articles/27711/ocp-ip-compliant-64-node-butterfly-network-on-chip-on-multi-fpga.html]]
*Simulators [#c45de38f]
-http://code.google.com/p/macsim/ - CPU-GPU sim
--[[GEM5 (M5)>http://gem5.org/Main_Page]]
---[[ read tutorial>http://www.gem5.org/dist/tutorials/isca_pres_2011.pdf]]
---[[GEM5 publications>http://gem5.org/Publications]]
*Mis [#t605a431]
-http://aslweb.u-aizu.ac.jp/aslint/index.php?www-multicore
-[[MCSoC TPC>http://aslweb.u-aizu.ac.jp/aslint/index.php?MCSoC%20TPCs]]
*Courses [#r1307293]
-[[Parallel Systems, DVA336, Autumn 2017>http://www.idt.mdh.se/kurser/dva336/]]
-[[Parallel Systems>http://parallel.vub.ac.be/education/parsys/]]
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