Miyuka Nakamura - English
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開始行:
[[Miyuka Nakamura]]
CENTER:SIZE(50){COLOR(green){Efficient Convolution Neural Network Architecture Optimization on FPGA}}
*[[研究の背景>Miyuka Nakamura]] [#ie79e156]
Artificial intelligence is booming today. Although there is a wide variety of artificial intelligence, there are various methods such as genetic algorithm, reinforcement learning and deep learning. Among them, my research focuses on convolutional neural networks in deep learning. CNN is a technology widely used in image recognition, speech recognition and so on. However, CNN has a problem that simulation takes time due to problems such as the inability to execute parallel processing when implemented in software. To solve this problem, I implement CNN in hardware. When implementing with Hardware, you need to be aware of the following.
-Don't make it a complicated implementation.
-Maintain accuracy.
-Time can be reduced.
Based on these, optimize the CNN implementation on Hardware.
*[[研究の目的>Miyuka Nakamura]] [#ybbfc843]
-To optmize CNN with Fixed point implemnetiaon and keep almost the same accuracy.
- Use Xilinx board and Vivado design tool
- Use MINIST data set for evalaution
- Study the power comsuption, thecomplexity, the accuarcy, the execution time
*Research schedule [#pbb70667]
-Read papers, book: April - June
-Describe the CNN architecture and the optimization techniques
-''MS exam ducuemnet preparation (recommenation, research proposal and plan), From June 3 - ''
-GS exam reaharsal
-GS Examination, July 13, 2019.
-Implement own system architecture, ??
-Simulate,??
-Write GT thesis, ??
*References [#g3d35207]
-The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, [[”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”>https://ieeexplore.ieee.org/document/8367135/]], Proc. of the IEEE International Conference on Big Data and Smart Computing (BigComp-2018), pp. 326-332, January 15-18, 2018, Shanghai, China. [paper.pdf], [slides.pdf]
-
終了行:
[[Miyuka Nakamura]]
CENTER:SIZE(50){COLOR(green){Efficient Convolution Neural Network Architecture Optimization on FPGA}}
*[[研究の背景>Miyuka Nakamura]] [#ie79e156]
Artificial intelligence is booming today. Although there is a wide variety of artificial intelligence, there are various methods such as genetic algorithm, reinforcement learning and deep learning. Among them, my research focuses on convolutional neural networks in deep learning. CNN is a technology widely used in image recognition, speech recognition and so on. However, CNN has a problem that simulation takes time due to problems such as the inability to execute parallel processing when implemented in software. To solve this problem, I implement CNN in hardware. When implementing with Hardware, you need to be aware of the following.
-Don't make it a complicated implementation.
-Maintain accuracy.
-Time can be reduced.
Based on these, optimize the CNN implementation on Hardware.
*[[研究の目的>Miyuka Nakamura]] [#ybbfc843]
-To optmize CNN with Fixed point implemnetiaon and keep almost the same accuracy.
- Use Xilinx board and Vivado design tool
- Use MINIST data set for evalaution
- Study the power comsuption, thecomplexity, the accuarcy, the execution time
*Research schedule [#pbb70667]
-Read papers, book: April - June
-Describe the CNN architecture and the optimization techniques
-''MS exam ducuemnet preparation (recommenation, research proposal and plan), From June 3 - ''
-GS exam reaharsal
-GS Examination, July 13, 2019.
-Implement own system architecture, ??
-Simulate,??
-Write GT thesis, ??
*References [#g3d35207]
-The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, [[”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”>https://ieeexplore.ieee.org/document/8367135/]], Proc. of the IEEE International Conference on Big Data and Smart Computing (BigComp-2018), pp. 326-332, January 15-18, 2018, Shanghai, China. [paper.pdf], [slides.pdf]
-
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