Mitsunari Ishii
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[[Members-Internal]]
CENTER:SIZE(50){COLOR(green){Efficient Error Detection Mechanism for OASIS Network-on-Chip System}}
CENTER:&ref(OASIS-3D.jpg,,70%);
CENTER:&ref(3Dpack.jpeg,,70%);
CENTER:COLOR(green){3D-OASIS-NoC flit format}
Contents:
#CONTENTS
**Background [#nec7d6fe]
During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.
**Research goal[#mec7d6fe]
The main goal of this research is to design and implement a fault detction and correction scheme for 3D-Fault-Tolerant-OASIS (3D-FTO). The scheme is based on Error-Detection-Codes (EDC) and Error-Correction-Codes (ECC). It should detect the presence of any kind of errors or malfunction and make the necessary communications with the different modules of 3D-FTO to perform the quick recovery ensuring a graceful performance degradation as less as possible.
**Research plan[#lec7d6fe]
- Investigate about the different approaches for fault detection in NoC systems
- Understand 3D-FTO architecture.
- Modify the flit format to host the additional code portion for fault detection and correction.
- Make the necessary modification for the remaining modules of the router.
- Evaluate the performance of the scheme (Area, power, latency, ...)
//** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References Set I [#x0fe7b0f]
-1.[[CRC_study_in_Hardware_In_Japanese.pdf(巡回冗長検査 CRC32 のハード/ソフト最適分割の検討)>http://web-ext.u-aizu.ac.jp/~benab//research/references/error-correction/5.pdf]]
-2.[[A CRC Verilog description module for a hard real time communication protocols in a control distributed systems.pdf>http://web-ext.u-aizu.ac.jp/~benab//research/references/error-correction/1.pdf]]
-3.OKADA Network Interface: http://aslweb.u-aizu.ac.jp/aslint/index.php?Theses#sf0a04d4
-4.COLOR(red){Run this Tutorial on your machine.} [[OASIS 3D-Router Hardware Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-5. [[Analysis of Error Recovery Schemes for Networks-on-Chips>https://drive.google.com/file/d/0B2HMlO4p7SuwTGJodnYwc1puZDg/view?usp=sharing]]
//**References Set II [#ec63a302]
** Benchmark suite [#c4629d5d]
-[[PDF>http://web-ext.u-aizu.ac.jp/~benab/research/benchmarks/benchmarks-1.pdf]]
-[[ppt>http://web-ext.u-aizu.ac.jp/~benab/research/benchmarks/benchmarks-1.ppt]]
終了行:
[[Members-Internal]]
CENTER:SIZE(50){COLOR(green){Efficient Error Detection Mechanism for OASIS Network-on-Chip System}}
CENTER:&ref(OASIS-3D.jpg,,70%);
CENTER:&ref(3Dpack.jpeg,,70%);
CENTER:COLOR(green){3D-OASIS-NoC flit format}
Contents:
#CONTENTS
**Background [#nec7d6fe]
During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.
**Research goal[#mec7d6fe]
The main goal of this research is to design and implement a fault detction and correction scheme for 3D-Fault-Tolerant-OASIS (3D-FTO). The scheme is based on Error-Detection-Codes (EDC) and Error-Correction-Codes (ECC). It should detect the presence of any kind of errors or malfunction and make the necessary communications with the different modules of 3D-FTO to perform the quick recovery ensuring a graceful performance degradation as less as possible.
**Research plan[#lec7d6fe]
- Investigate about the different approaches for fault detection in NoC systems
- Understand 3D-FTO architecture.
- Modify the flit format to host the additional code portion for fault detection and correction.
- Make the necessary modification for the remaining modules of the router.
- Evaluate the performance of the scheme (Area, power, latency, ...)
//** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References Set I [#x0fe7b0f]
-1.[[CRC_study_in_Hardware_In_Japanese.pdf(巡回冗長検査 CRC32 のハード/ソフト最適分割の検討)>http://web-ext.u-aizu.ac.jp/~benab//research/references/error-correction/5.pdf]]
-2.[[A CRC Verilog description module for a hard real time communication protocols in a control distributed systems.pdf>http://web-ext.u-aizu.ac.jp/~benab//research/references/error-correction/1.pdf]]
-3.OKADA Network Interface: http://aslweb.u-aizu.ac.jp/aslint/index.php?Theses#sf0a04d4
-4.COLOR(red){Run this Tutorial on your machine.} [[OASIS 3D-Router Hardware Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, July 8, 2014.
-5. [[Analysis of Error Recovery Schemes for Networks-on-Chips>https://drive.google.com/file/d/0B2HMlO4p7SuwTGJodnYwc1puZDg/view?usp=sharing]]
//**References Set II [#ec63a302]
** Benchmark suite [#c4629d5d]
-[[PDF>http://web-ext.u-aizu.ac.jp/~benab/research/benchmarks/benchmarks-1.pdf]]
-[[ppt>http://web-ext.u-aizu.ac.jp/~benab/research/benchmarks/benchmarks-1.ppt]]
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