Kota Toyama
をテンプレートにして作成
[
トップ
] [
新規
|
一覧
|
単語検索
|
最終更新
|
ヘルプ
|
ログイン
]
開始行:
[[Members-Internal]]
CENTER:SIZE(40){COLOR(blue){GT1-S1: Study of Character Recognition with Feed-Forward Neural Network}}
*''Motivation'' [#p1d2a15e]
Feed Forward Neural Networks (FFNN). For each neuron of FFNN within the hidden layers, a non-linear function computation is required to determine the activation value
of the neuron. Without efficient, dedicated FP hardware, such computations can create difficulties for the whole system performance of the system, hence making the design difficult to be used in critical applications like real-time systems.
*''Goal'' [#lc9dcf47]
The goal of this research is to implement a Feed Forward Neural Networks (FFNN) on FPGA. A real application, such as character recognition, should be demonstrated. The FFNN should be trained in Matlab environment and the Nios II/f (co cache) should be used for Altera FPGA prototyping. The Nios II ISA should be extended to have a Floating Point ALU.
*References [#me106b6a]
-[[Ref1>https://drive.google.com/file/d/0B2HMlO4p7SuwUDhRNVpUV0tib28/view?usp=sharing]]
-[[Ref.2>https://drive.google.com/file/d/0B2HMlO4p7SuwZTRadm54ekg3ZG8/view?usp=sharing]]
*Schedule [#cab83355]
-Poster 10/10 - 10/13
--Please upload your poster here by 9/29
*RPS/RPS [#dcf655d5]
-??/?? rps1.pptx
-9/6 rps2.pptx
-9/29 rps3.pptx
終了行:
[[Members-Internal]]
CENTER:SIZE(40){COLOR(blue){GT1-S1: Study of Character Recognition with Feed-Forward Neural Network}}
*''Motivation'' [#p1d2a15e]
Feed Forward Neural Networks (FFNN). For each neuron of FFNN within the hidden layers, a non-linear function computation is required to determine the activation value
of the neuron. Without efficient, dedicated FP hardware, such computations can create difficulties for the whole system performance of the system, hence making the design difficult to be used in critical applications like real-time systems.
*''Goal'' [#lc9dcf47]
The goal of this research is to implement a Feed Forward Neural Networks (FFNN) on FPGA. A real application, such as character recognition, should be demonstrated. The FFNN should be trained in Matlab environment and the Nios II/f (co cache) should be used for Altera FPGA prototyping. The Nios II ISA should be extended to have a Floating Point ALU.
*References [#me106b6a]
-[[Ref1>https://drive.google.com/file/d/0B2HMlO4p7SuwUDhRNVpUV0tib28/view?usp=sharing]]
-[[Ref.2>https://drive.google.com/file/d/0B2HMlO4p7SuwZTRadm54ekg3ZG8/view?usp=sharing]]
*Schedule [#cab83355]
-Poster 10/10 - 10/13
--Please upload your poster here by 9/29
*RPS/RPS [#dcf655d5]
-??/?? rps1.pptx
-9/6 rps2.pptx
-9/29 rps3.pptx
ページ名: