Ken Saito
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開始行:
CENTER:SIZE(40){COLOR(blue){Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System}}
-[[Members-Internal]]
*Background (Problem Definition) [#x8959e48]
The huge computing power of many-core multi-processor systems will require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the optical interconnects, which promise significant advantages over their electronic counterparts. In particular, optical on-chip interconnect (ONoC)) offers a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In addition, when combined with 3D integration technology, ONoC offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint.
Current [[PHENIC>http://aslweb.u-aizu.ac.jp/aslint/index.php?PHENIC]] and also conventional Photonic NoC Systems lack an efficient control router.
*Research Goal [#t85a4382]
Hardware design and evaluation of Electrical Control Router for Photonic Network-on-Chip Systems.
*Research Schedule [#k3603c5b]
***Step 0 (Mentor: D3 Achraf), COLOR(red){Completion Date: 7/24} [#sf5618b7]
-Take the Guidance Lectures: http://aslweb.u-aizu.ac.jp/aslint/index.php?Guidance%20Lectures#gb3fdf90
***Step 1 COLOR(red){Completion Date: %%July 30%%, August 10, 2015.} [#ba4339d7]
Read these references:
-[["Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems">http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/WCITCA2015/WCITCA2015_CameraReady.pdf]], June 11-13, 2015
-[[Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/ICISCE2015/ICISCE2015_CR_final.pdf]], 04/2015.
***Step 2 COLOR(red){Completion Date: September 20, 2015.} [#v728046f]
Run these 2 tutorials on your machine:
-[[OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-3DFTRV1_Design_Tutorial_05282015.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, May 28, 2015.
-[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.}
***Step 3 COLOR(red){Due date: October 30, 2015.} [#pf0be82d]
CR Design
***Step 4 COLOR(red){Due date: November 30,2015.} [#jbcfc45e]
CR Evaluation
***Step 5 [#y00b6e77]
Thesis writing
*References[#jec7d6fe]
-[[前論文テーマ (Previous GT)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Theses]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
終了行:
CENTER:SIZE(40){COLOR(blue){Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System}}
-[[Members-Internal]]
*Background (Problem Definition) [#x8959e48]
The huge computing power of many-core multi-processor systems will require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the optical interconnects, which promise significant advantages over their electronic counterparts. In particular, optical on-chip interconnect (ONoC)) offers a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In addition, when combined with 3D integration technology, ONoC offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint.
Current [[PHENIC>http://aslweb.u-aizu.ac.jp/aslint/index.php?PHENIC]] and also conventional Photonic NoC Systems lack an efficient control router.
*Research Goal [#t85a4382]
Hardware design and evaluation of Electrical Control Router for Photonic Network-on-Chip Systems.
*Research Schedule [#k3603c5b]
***Step 0 (Mentor: D3 Achraf), COLOR(red){Completion Date: 7/24} [#sf5618b7]
-Take the Guidance Lectures: http://aslweb.u-aizu.ac.jp/aslint/index.php?Guidance%20Lectures#gb3fdf90
***Step 1 COLOR(red){Completion Date: %%July 30%%, August 10, 2015.} [#ba4339d7]
Read these references:
-[["Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems">http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/WCITCA2015/WCITCA2015_CameraReady.pdf]], June 11-13, 2015
-[[Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/ICISCE2015/ICISCE2015_CR_final.pdf]], 04/2015.
***Step 2 COLOR(red){Completion Date: September 20, 2015.} [#v728046f]
Run these 2 tutorials on your machine:
-[[OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-3DFTRV1_Design_Tutorial_05282015.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, May 28, 2015.
-[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], COLOR(olive){Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.}
***Step 3 COLOR(red){Due date: October 30, 2015.} [#pf0be82d]
CR Design
***Step 4 COLOR(red){Due date: November 30,2015.} [#jbcfc45e]
CR Evaluation
***Step 5 [#y00b6e77]
Thesis writing
*References[#jec7d6fe]
-[[前論文テーマ (Previous GT)>http://aslweb.u-aizu.ac.jp/aslint/index.php?Theses]]
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
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