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[[Michael Meyer]]
CENTER:SIZE(30){COLOR(blue){Fault-tolerant Photonic Mesh-Based Network-on-Chip for Reliable Many-core Systems-on-Chip (tentative)}}
*Schedule [#qd04e3be]
|Section|Completion Date|Draft|
|Abstract |July 22, 10 AM|[[Abstract.pdf]]|
|Introduction|July 27, 10 AM|[[Introduction>https://drive.google.com/file/d/0B7t099YAMQw3TFVZWHVRUVE1d0k/view?usp=sharing]]|
|Related Work|August 3, 6 PM|[[Related Work.pdf>https://drive.google.com/file/d/0B7t099YAMQw3WVJrTVB2RG1Ib28/view?usp=sharing]]|
|System Architecture|August 10, 10 AM|[[System Architecture_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3SXFXSzlxeUdjMjA/view?usp=sharing]]|
|Routing Algorithm|August 11, 10 AM|[[Routing Algorithm_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3SXFXSzlxeUdjMjA/view?usp=sharing]]|
|Design Space Exploration|August 19, 10 AM|[[Design Space Exploration_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3bmtpNGtIVWN6Mnc/view?usp=sharing]]|
|Evaluation|August 31 %%August 27%%, 10 AM|[[Evaluation+v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3a2hUZkJuVWdSem8/view?usp=sharing]]|
|Conclusion and Future Work|Sept 7, 10 AM|[[Conclusion and Future Work.pdf>https://drive.google.com/file/d/0B7t099YAMQw3eDNUQnZGeWNCRE0/view?usp=sharing]]|
|Revision 2|Sept %%21%% 19, 10 AM|[[Revision 1>https://drive.google.com/file/d/0B7t099YAMQw3cXMtbGNjaXQzYWM/view?usp=sharing]]|
----
***0. Abstract [#v112563c]
- Summary of background info
- Summary of problem
- Summary of results
- Summary of benefits
***1. Introduction [#dae52410]
-Explain the problem which we have solved
-Explain why the problem is not already solved or other solutions are ineffective in one or more important ways
-Explain why our solution is worth considering and why is it effective in some way that others are not
-Write how the rest of the paper is structured
***2. Related work [#z107f75f]
- Briefly talk about Mesh
- Briefly Talk about Oasis
- Details about Photonic NoCs
- Details about Fault Tolerance
--Redundancy
--Rerouting
***3. System Implementation [#fd9fb312]
-3.1 Router Micro-architecture (FT Switch + Control)
-- You need to have FT routers with different ports(5, 4, 3).
-- Explanation of the selection of redundant MRs
Notes:
--Reduction of Crossing in your router means lower insertion loss and lower crosstalk [see Ref. 1 and 2 bellow].
--Reduction of the number of MRRs in your router can offer the benefits in terms of device area and power consumption [see Ref. 1 and 2 bellow].
-3.2 FT Routing Algorithm
***4. FT Router design Space Exploration [#w4f44e24]
-Investigate the Latency, area and optical power trade-offs in designing your PHENIC System while varying micro-architectures parameters.
-COLOR(red){Analysis of Cross-talk}. Refer to the following references:
--Yiyuan Xie, Weihua Xu, Weilun Zhao, Yexiong Huang, Tingting Song, and Min Guo, [[Performance Optimization and Evaluation for Torus-Based Optical Networks-on-Chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7160661]], Journal of Lightwave Technology, 2015.
---Y. Xie, M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and W. Liu, [[Formal worst-case analysis of crosstalk noise in mesh-based optical networks-on-chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6352932]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 10, pp. 1823–1836, Oct. 2013.
---M. Nikdast, J. Xu, X. Wu, Z. Wang, X. Wang, and Z. Wang,[[Fat-tree-based optical interconnection networks under crosstalk noise constraint>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6744606]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 156–169, Feb. 2014.
---M. Nikdast, J. Xu, L. H. K. Duong, X. Wu, X. Wang, Z. Wang, Z. Wang, P. Yang, Y. Ye, and Q. Hao,[[Crosstalk noise in WDM-based optical networks-on-chip: a formal study and comparison>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6977983]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published.
---M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and Z. Wang, [[Systematic analysis of crosstalk noise in folded-torus-based optical networks-on-chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6740052]],¡É IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33, no. 3, pp. 437–450, Mar. 2014.
-Analysis o Insertion Loss
***5. Evaluation [#u484357f]
-5.1 Methodology
-- How you evaluated your system
-- Performance metrics
-- Performance parameters
-5.2 Results
--A. Performance Evaluation
---Throughput
---ETE latency
--B. Complexity Evaluation
---Area (Erouter and ORouter)
---Total Power
---Total Energy
--C. Scalability and Reliability Evaluation
---Optical Signal to noise ratio (OSNR)
---Bit-Error-Rate
Ref. 1 [[Crosstalk noise and bit error rate analysis for optical network-on-chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5523371&tag=1]]
COLOR(red){Similar to Ref. 1, Develop your won Mathematical Model and calculate these values (cross-talk, SNR, BER). Do not use CLAP tool.}
COLOR(red){IMPORTANT NOTES}
-1. For each of these three evaluations, compare with well known works , such as Corona, Firefly, Phastlane, Firefly, EMesh/ENoC.
-2. Large and Realistic Benchmarks are needed
***5. Conclusions and Future Work [#t72a0ccf]
- Explain the problem which you have solved
- Explain your solution to the problem
- Explain why your solution is good: give some numbers
- Explain why the reader should be impressed by your work
- Give summary of results
- Give some future works
***References [#t0c66dfb]
- Use a .bib file from the start
-[1] L. P. Carloni, P. Pande, and Y. Xie, ¡ÈNetworks-on-chip in emerging
interconnect paradigms: Advantages and challenges,¡É in Proceedings of
the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
IEEE Computer Society, 2009, pp. 93–102.
-[2] F. N. Sibai, ¡ÈA two-dimensional low-diameter scalable on-chip network
for interconnecting thousands of cores,¡É Parallel and Distributed Systems,
IEEE Transactions on, vol. 23, no. 2, pp. 193–201, 2012.
-[3] A. B. Abdallah and M. Sowa, ¡ÈBasic Network-on-Chip Interconnection
for Future Gigascale MCSoCs Applications: Communication and Computation
Orthogonalization,¡É in JASSST2006, 2006.
-[4] A. Ben Ahmed, A. Ben Abdallah, and K. Kuroda, ¡ÈArchitecture and
design of ecient 3D network-on-chip (3D NoC) for custom multicore
SoC,¡É in Broadband, Wireless Computing, Communication and Applications
(BWCCA), 2010 International Conference on. IEEE, 2010, pp.
67–73.
-[5] G. Leary and K. S. Chatha, ¡ÈDesign of noc for soc with multiple
use cases requiring guaranteed performance,¡É in VLSI Design, 2010.
VLSID¡Ç10. 23rd International Conference on. IEEE, 2010, pp. 200–
205.
-[6] L. Benini and G. De Micheli, ¡ÈNetworks on chips: a new soc paradigm,¡É
Computer, vol. 35, no. 1, pp. 70–78, 2002.
-[7] ¡ÈITRS Report Interconnect,¡É http://www.itrs.net/ITRS%201999-2014%
20Mtgs,%20Presentations%20&%20Links/2011ITRS/2011Chapters/
2011Interconnect.pdf/, 2011, [Online; accessed 1-July-2015].
-[8] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante,
C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis
et al., ¡ÈThree-dimensional silicon integration,¡É IBM Journal of Research
and Development, vol. 52, no. 6, pp. 553–569, 2008.
-[9] S. Fujita, K. Nomura, K. Abe, and T. H. Lee, ¡È3d on-chip networking
technology based on post-silicon devices for future networks-on-chip,¡É
in 2006 1st International Conference on Nano-Networks and Workshops,
2006.
-[10] Y.-L. Jeang, T.-s. Wey, H.-Y. Wang, and C.-W. Hung, ¡ÈMesh-tree architecture
for network-on-chip design,¡É in Innovative Computing, Information
and Control, 2007. ICICIC¡Ç07. Second International Conference
on. IEEE, 2007, pp. 262–262.
-[11] ¡ÈReplacing Silicon with Carbon Nanotubes: Why its Still Worth Considering,¡É
http://www.eeweb.com/blog/aaronfranklin, 2012, [Online; accessed
1-April-2015].
-[12] J. Wolfe, ¡È Why IBM and Intel Are Chasing the 100B Dollar Opportunity
in Nanophotonics,¡É 2012, online; accessed 1-July-2015. [Online].
Available: nurlfhttp://www.forbes.com/sites/joshwolfe/2012/12/13/
why-ibm-and-intel-are-chasing-the-100b-opportunity-in-nanophotonics/
g
-[13] D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi,
M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn,
¡ÈCorona: System implications of emerging nanophotonic technology,¡É
in ACM SIGARCH Computer Architecture News, vol. 36, no. 3. IEEE
Computer Society, 2008, pp. 153–164.
-[14] R. Kumar, V. Zyuban, and D. M. Tullsen, ¡ÈInterconnections in multi-core
architectures: Understanding mechanisms, overheads and scaling,¡É in
Computer Architecture, 2005. ISCA¡Ç05. Proceedings. 32nd International
Symposium on. IEEE, 2005, pp. 408–419.
-[15] R. Kappeler, ¡ÈRadiation testing of micro photonic components,¡É stagiaire
Project Report. ESA/ESTEC. September 29, 2004. Ref. No.: EWP 2263.
-[16] Y. Yang, ¡ÈIssues of esd protection in nano-scale cmos,¡É Ph.D. dissertation,
George Mason University, 2010.
-[17] J. Keane and C. H. Kim, ¡ÈAn odomoeter for cpus,¡É Spectrum, IEEE,
vol. 48, no. 5, pp. 28–33, 2011.
-[18] S. Luryi, J. Xu, and A. Zaslavsky, Future trends in microelectronics: up
the nano creek. John Wiley & Sons, 2007.
-[19] Z.-S. Hu, F.-Y. Hung, K.-J. Chen, S.-J. Chang, W.-K. Hsieh, and T.-
Y. Liao, ¡ÈImprovement in thermal degradation of zno photodetector
by embedding silver oxide nanoparticles,¡É Functional Materials Letters,
vol. 6, no. 01, p. 1350001, 2013.
-[20] Z. Tu, Z. Zhou, and X. Wang, ¡ÈReliability considerations of high speed
germanium waveguide photodetectors,¡É in SPIE OPTO. International
Society for Optics and Photonics, 2014, pp. 89 820W–89 820W.
-[21] M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, ¡ÈCircuit failure prediction
and its application to transistor aging,¡É in VLSI Test Symposium,
2007. 25th IEEE. IEEE, 2007, pp. 277–286.
-[22] J. Keane, T.-H. Kim, and C. H. Kim, ¡ÈAn on-chip nbti sensor for measuring
pmos threshold voltage degradation,¡É Very Large Scale Integration
(VLSI) Systems, IEEE Transactions on, vol. 18, no. 6, pp. 947–956,
2010.
-[23] E. Mintarno, J. Skaf, R. Zheng, J. B. Velamala, Y. Cao, S. Boyd,
R. W. Dutton, and S. Mitra, ¡ÈSelf-tuning for maximized lifetime energye
ciency in the presence of circuit aging,¡É Computer-Aided Design of
Integrated Circuits and Systems, IEEE Transactions on, vol. 30, no. 5,
pp. 760–773, 2011.
-[24] M. Radetzki, C. Feng, X. Zhao, and A. Jantsch, ¡ÈMethods for fault tolerance
in networks-on-chip,¡É ACM Computing Surveys (CSUR), vol. 46,
no. 1, p. 8, 2013.
-[25] K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W.-k. Shih,
S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki, ¡ÈManaging
process variation in intel¡Çs 45nm cmos technology.¡É Intel Technology
Journal, vol. 12, no. 2, 2008.
-[26] S. K. Saha, ¡ÈModeling process variability in scaled cmos technology,¡É
IEEE Design & Test of Computers, no. 2, pp. 8–16, 2010.
-[27] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. O¡¯ berg,
K. Tiensyrj¡¯a, and A. Hemani, ¡ÈA network on chip architecture and design
methodology,¡É in VLSI, 2002. Proceedings. IEEE Computer Society
Annual Symposium on. IEEE, 2002, pp. 105–112.
-[28] M. Mohamed, ¡ÈSilicon nanophotonics for many-core on-chip networks,¡É
Ph.D. dissertation, University of Colorado, 2013.
-[29] A. B. Ahmed and A. B. Abdallah, ¡ÈArchitecture and design of highthroughput,
low-latency, and fault-tolerant routing algorithm for 3Dnetwork-
on-chip (3D-NoC),¡É The Journal of Supercomputing, vol. 66,
no. 3, pp. 1507–1532, 2013.
-[30] Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary,
¡ÈFirefly: illuminating future network-on-chip with nanophotonics,¡É in
ACM SIGARCH Computer Architecture News, vol. 37, no. 3. ACM,
2009, pp. 429–440.
-[31] A. Ben Ahmed and A. Ben Abdallah, ¡ÈGraceful deadlock-free
fault-tolerant routing algorithm for 3D Network-on-Chip architectures,¡É
Journal of Parallel and Distributed Computing, vol. 74, no. 4,
pp. 2229–2240, 2014. [Online]. Available: http://web-ext.u-aizu.ac.jp/
benab/publications/journals/JPDC14/JPDC-preprint.pdf
-[32] A. B. Abdallah, Multicore Systems On-chip: Practical
Software/hardware Design. Springer, 2013, vol. 2.
-[33] A. B. Abdallah, M. Nakamura, A. B. Ahmed, M. Meyer, and
Y. Okuyama, ¡ÈFault-tolerant router for highly-reliable many-core 3d-noc
systems.¡É
-[34] A. Shacham, K. Bergman, and L. P. Carloni, ¡ÈPhotonic networks-onchip
for future generations of chip multiprocessors,¡É Computers, IEEE
Transactions on, vol. 57, no. 9, pp. 1246–1260, 2008.
-[35] G. Ramesh and S. SundaraVadivelu, ¡ÈA reliable and fault tolerant routing
for optical wdm networks,¡É arXiv preprint arXiv:0912.0602, 2009.
-[36] P. K. Loh and W.-J. Hsu, ¡ÈDesign of a viable fault-tolerant routing
strategy for optical-based grids,¡É in Parallel and Distributed Processing
and Applications. Springer, 2003, pp. 112–126.
-[37] Q. Xingyun, F. Quanyou, C. Yongran, D. Qiang, and D.Wenhua, ¡ÈA fault
tolerant buerless optical interconnection network,¡É in Computer and
Information Science, 2009. ICIS 2009. Eighth IEEE/ACIS International
Conference on. IEEE, 2009, pp. 249–254.
-[38]D. Xiang, Y. Zhang, S. Shan, and Y. Xu, ¡ÈA fault-tolerant routing
algorithm design for on-chip optical networks,¡É in Reliable Distributed
Systems (SRDS), 2013 IEEE 32nd International Symposium on. IEEE,
2013, pp. 1–9.
-[39] M. McLaren, N. L. Binkert, A. L. Davis, and M. Florentino, ¡ÈEnergye
cient and fault-tolerant resonator-based modulation and wavelength
division multiplexing systems,¡É Apr. 22 2014, uS Patent 8,705,972.
-[40] L. Sahasrabuddhe, S. Ramamurthy, and B. Mukherjee, ¡ÈFault management
in ip-over-wdm networks: Wdm protection versus ip restoration,¡É
Selected Areas in Communications, IEEE Journal on, vol. 20, no. 1, pp.
21–33, 2002.
-[41] J. Zhang and B. Mukheriee, ¡ÈA review of fault management in wdm
mesh networks: basic concepts and research challenges,¡É Network, IEEE,
vol. 18, no. 2, pp. 41–48, 2004.
-[42] B. Ahmed and A. B. Abdallah, ¡ÈPHENIC: Towards Photonic 3DNetwork-
on-Chip Architecture for High-throughput Many-core Systemson-
Chip,¡É in IEEE Proc. of the 14th Int. Conf. on Sciences and
Techniques of Automatic Control and Computer Eng, 2013.
-[43] A. K. Todimala, Fault-tolerance using shared path protection in wavelength
division multiplexing optical transport networks. University of
Nebraska at Lincoln, 2006.
-[44] M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang,
and Z. Wang, ¡ÈSystematic analysis of crosstalk noise in folded-torusbased
optical networks-on-chip,¡É Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on, vol. 33, no. 3, pp. 437–450,
2014.
-[45] R. Kumar, D. M. Tullsen, and N. P. Jouppi, ¡ÈCore architecture optimization
for heterogeneous chip multiprocessors,¡É in Proceedings of the
15th international conference on Parallel architectures and compilation
techniques. ACM, 2006, pp. 23–32.
-[46] M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi, ¡ÈPhastlane: a
rapid transit optical routing network,¡É in ACM SIGARCH Computer
Architecture News, vol. 37, no. 3. ACM, 2009, pp. 441–450.
½ªÎ»¹Ô:
[[Michael Meyer]]
CENTER:SIZE(30){COLOR(blue){Fault-tolerant Photonic Mesh-Based Network-on-Chip for Reliable Many-core Systems-on-Chip (tentative)}}
*Schedule [#qd04e3be]
|Section|Completion Date|Draft|
|Abstract |July 22, 10 AM|[[Abstract.pdf]]|
|Introduction|July 27, 10 AM|[[Introduction>https://drive.google.com/file/d/0B7t099YAMQw3TFVZWHVRUVE1d0k/view?usp=sharing]]|
|Related Work|August 3, 6 PM|[[Related Work.pdf>https://drive.google.com/file/d/0B7t099YAMQw3WVJrTVB2RG1Ib28/view?usp=sharing]]|
|System Architecture|August 10, 10 AM|[[System Architecture_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3SXFXSzlxeUdjMjA/view?usp=sharing]]|
|Routing Algorithm|August 11, 10 AM|[[Routing Algorithm_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3SXFXSzlxeUdjMjA/view?usp=sharing]]|
|Design Space Exploration|August 19, 10 AM|[[Design Space Exploration_v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3bmtpNGtIVWN6Mnc/view?usp=sharing]]|
|Evaluation|August 31 %%August 27%%, 10 AM|[[Evaluation+v1.pdf>https://drive.google.com/file/d/0B7t099YAMQw3a2hUZkJuVWdSem8/view?usp=sharing]]|
|Conclusion and Future Work|Sept 7, 10 AM|[[Conclusion and Future Work.pdf>https://drive.google.com/file/d/0B7t099YAMQw3eDNUQnZGeWNCRE0/view?usp=sharing]]|
|Revision 2|Sept %%21%% 19, 10 AM|[[Revision 1>https://drive.google.com/file/d/0B7t099YAMQw3cXMtbGNjaXQzYWM/view?usp=sharing]]|
----
***0. Abstract [#v112563c]
- Summary of background info
- Summary of problem
- Summary of results
- Summary of benefits
***1. Introduction [#dae52410]
-Explain the problem which we have solved
-Explain why the problem is not already solved or other solutions are ineffective in one or more important ways
-Explain why our solution is worth considering and why is it effective in some way that others are not
-Write how the rest of the paper is structured
***2. Related work [#z107f75f]
- Briefly talk about Mesh
- Briefly Talk about Oasis
- Details about Photonic NoCs
- Details about Fault Tolerance
--Redundancy
--Rerouting
***3. System Implementation [#fd9fb312]
-3.1 Router Micro-architecture (FT Switch + Control)
-- You need to have FT routers with different ports(5, 4, 3).
-- Explanation of the selection of redundant MRs
Notes:
--Reduction of Crossing in your router means lower insertion loss and lower crosstalk [see Ref. 1 and 2 bellow].
--Reduction of the number of MRRs in your router can offer the benefits in terms of device area and power consumption [see Ref. 1 and 2 bellow].
-3.2 FT Routing Algorithm
***4. FT Router design Space Exploration [#w4f44e24]
-Investigate the Latency, area and optical power trade-offs in designing your PHENIC System while varying micro-architectures parameters.
-COLOR(red){Analysis of Cross-talk}. Refer to the following references:
--Yiyuan Xie, Weihua Xu, Weilun Zhao, Yexiong Huang, Tingting Song, and Min Guo, [[Performance Optimization and Evaluation for Torus-Based Optical Networks-on-Chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7160661]], Journal of Lightwave Technology, 2015.
---Y. Xie, M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and W. Liu, [[Formal worst-case analysis of crosstalk noise in mesh-based optical networks-on-chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6352932]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 10, pp. 1823–1836, Oct. 2013.
---M. Nikdast, J. Xu, X. Wu, Z. Wang, X. Wang, and Z. Wang,[[Fat-tree-based optical interconnection networks under crosstalk noise constraint>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6744606]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 156–169, Feb. 2014.
---M. Nikdast, J. Xu, L. H. K. Duong, X. Wu, X. Wang, Z. Wang, Z. Wang, P. Yang, Y. Ye, and Q. Hao,[[Crosstalk noise in WDM-based optical networks-on-chip: a formal study and comparison>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6977983]],¡É IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published.
---M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and Z. Wang, [[Systematic analysis of crosstalk noise in folded-torus-based optical networks-on-chip>http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6740052]],¡É IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33, no. 3, pp. 437–450, Mar. 2014.
-Analysis o Insertion Loss
***5. Evaluation [#u484357f]
-5.1 Methodology
-- How you evaluated your system
-- Performance metrics
-- Performance parameters
-5.2 Results
--A. Performance Evaluation
---Throughput
---ETE latency
--B. Complexity Evaluation
---Area (Erouter and ORouter)
---Total Power
---Total Energy
--C. Scalability and Reliability Evaluation
---Optical Signal to noise ratio (OSNR)
---Bit-Error-Rate
Ref. 1 [[Crosstalk noise and bit error rate analysis for optical network-on-chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5523371&tag=1]]
COLOR(red){Similar to Ref. 1, Develop your won Mathematical Model and calculate these values (cross-talk, SNR, BER). Do not use CLAP tool.}
COLOR(red){IMPORTANT NOTES}
-1. For each of these three evaluations, compare with well known works , such as Corona, Firefly, Phastlane, Firefly, EMesh/ENoC.
-2. Large and Realistic Benchmarks are needed
***5. Conclusions and Future Work [#t72a0ccf]
- Explain the problem which you have solved
- Explain your solution to the problem
- Explain why your solution is good: give some numbers
- Explain why the reader should be impressed by your work
- Give summary of results
- Give some future works
***References [#t0c66dfb]
- Use a .bib file from the start
-[1] L. P. Carloni, P. Pande, and Y. Xie, ¡ÈNetworks-on-chip in emerging
interconnect paradigms: Advantages and challenges,¡É in Proceedings of
the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
IEEE Computer Society, 2009, pp. 93–102.
-[2] F. N. Sibai, ¡ÈA two-dimensional low-diameter scalable on-chip network
for interconnecting thousands of cores,¡É Parallel and Distributed Systems,
IEEE Transactions on, vol. 23, no. 2, pp. 193–201, 2012.
-[3] A. B. Abdallah and M. Sowa, ¡ÈBasic Network-on-Chip Interconnection
for Future Gigascale MCSoCs Applications: Communication and Computation
Orthogonalization,¡É in JASSST2006, 2006.
-[4] A. Ben Ahmed, A. Ben Abdallah, and K. Kuroda, ¡ÈArchitecture and
design of ecient 3D network-on-chip (3D NoC) for custom multicore
SoC,¡É in Broadband, Wireless Computing, Communication and Applications
(BWCCA), 2010 International Conference on. IEEE, 2010, pp.
67–73.
-[5] G. Leary and K. S. Chatha, ¡ÈDesign of noc for soc with multiple
use cases requiring guaranteed performance,¡É in VLSI Design, 2010.
VLSID¡Ç10. 23rd International Conference on. IEEE, 2010, pp. 200–
205.
-[6] L. Benini and G. De Micheli, ¡ÈNetworks on chips: a new soc paradigm,¡É
Computer, vol. 35, no. 1, pp. 70–78, 2002.
-[7] ¡ÈITRS Report Interconnect,¡É http://www.itrs.net/ITRS%201999-2014%
20Mtgs,%20Presentations%20&%20Links/2011ITRS/2011Chapters/
2011Interconnect.pdf/, 2011, [Online; accessed 1-July-2015].
-[8] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante,
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