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開始行:
[[AY 2017 GT Topic Assignments]]
#CONTENTS
*Design of a Multicast Router [#oe05f4af]
''Motivation''
Future many-core architectures with dozens to hundreds of nodes will require scalable and efficient on-chip communication
solutions . This has motivated substantial research into network-on-chip designs. Recent proposals [ASL] have successfully driven down interconnect delay to approach that of pure wire delay. However, one of the
implicit assumptions in the evaluation of these proposals is that the vast majority of traffic is of a one-to-one (unicast)
nature. Unfortunately, current router architectures are extremely inefficient at handling multicast and broadcast traffic.
In this work, we leverage several popular research innovations to demonstrate that the assumption of predominantly
unicast traffic is not a valid one for on-chip networks and motivate the design of our multicast router, Virtual Circuit
Tree Multicasting (VCTM).
The inability of current router architectures to efficiently handle multicast communication can
also have performance ramifications for unicast communications. Unicast communications occurring at the same time as a
multicast communication are likely to be delayed by the burst of communication.
State-of-the-art packet-switched routers can of course utilize multiple unicast messages to achieve multicast functionality.
Decomposing a multicast into several unicasts can consume additional cycles and cause a bottleneck at the injection port as multiple messages try to access the network in the same cycle. In the baseline router, this injection bottleneck can add several cycles to the average network latency.
''Gola:'' The goal of this research is to devise a new fault-tolenat multicast routing algorithm for NASH system.
[[Reference>https://drive.google.com/file/d/0B2HMlO4p7SuwU01XUkVJLXdjdEU/view?usp=sharing]]
*GT: COLOR(){ Aizuwakanatsu Taxi Demand Prediction System Using Neural Network} [#xa94d9bf]
''Motivation:'' Taxi services are important transportation method in almost any cities. The Taxi business is rapidly using IT technology to minimize vacant driving time and where to find passengers.
Predicting where to find passengers is a challenging problem which can be solved by neural networks.
''Goal'': The goal of this project is to design an NN model to estimate taxi demand and trained with historical taxi ride date for Aizuwakamatsu city.
*GT/MS: ON-LINE LEARNING ALGORITHM FOR SPIKING NEURO-CHIP SYSTEM [#jc9aea98]
''Motivation'':
The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died.
Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network.
SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse.
Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.
''Goal:'' The goal of this research is to design an on-line learning algorithm for Neuro-inpired systems.
References
*GT: Design of A Cognitive Network-on-Chip [#x52e634f]
''Motivation:'' The number of cores in a manycore chip has been increasing in the past decade. The rate of increase
will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important
design consideration.
''Goal:'' Design a new design method for implementing a cognitive OASIS network-on-chip that has the ability to recognize changes in the environment and to
learn new ways to adapt to the changes. This learning method should provide the network to manage itself to achieve low network latency, higher reliability, power efficiency,
and adaptability. Fault-tolerant routing should be considered.
*GT: Brain-inspired Smart System for Handicapped People [#e0a0b4ad]
''Motivation:''One of the goals in implantable BMI (brain machine interface) systems is to record and interpret neural signals from the motor cortex and use it to control artificial actuators. This will help handicapped people to control artificial limbs with their thoughts. Current solutions transmit all data to an off-chip device for processing. This results in a large data rate and latency which affect the scalability and performance of the system.
''Gola:''The goal of this project is to develop a neural network on-chip to directly process and interpret these brain signals on-chip leading to a scalable and fast system.
*Neumercail Findinsg [#db14a331]
-On-chip networks consume a significant fraction of total on-chip power [5], [42]; up to 30% for Intel’s 80-core teraflops network [15] and 36% for the RAW [39] on-chip network.
--[5]S. Borkar, “Networks for multi-core chips: A contrarian view,” Special Session at ISLPED 2007.
--[15] Intel, “From a few cores to many: A Terascale computing research overview,” 2006. [Online]. Available: http://download.intel.com/research/platform/terascale/ terascale
overview paper.pdf
--[39]M. B. Taylor et. al, “Scalar operand networks: On-chip interconnect for
ILP in partitioned architectures,” in HPCA, 2003.
--[42]H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, “Orion: A powerperformance simulator for interconnection networks,” in MICRO-35, 2002
終了行:
[[AY 2017 GT Topic Assignments]]
#CONTENTS
*Design of a Multicast Router [#oe05f4af]
''Motivation''
Future many-core architectures with dozens to hundreds of nodes will require scalable and efficient on-chip communication
solutions . This has motivated substantial research into network-on-chip designs. Recent proposals [ASL] have successfully driven down interconnect delay to approach that of pure wire delay. However, one of the
implicit assumptions in the evaluation of these proposals is that the vast majority of traffic is of a one-to-one (unicast)
nature. Unfortunately, current router architectures are extremely inefficient at handling multicast and broadcast traffic.
In this work, we leverage several popular research innovations to demonstrate that the assumption of predominantly
unicast traffic is not a valid one for on-chip networks and motivate the design of our multicast router, Virtual Circuit
Tree Multicasting (VCTM).
The inability of current router architectures to efficiently handle multicast communication can
also have performance ramifications for unicast communications. Unicast communications occurring at the same time as a
multicast communication are likely to be delayed by the burst of communication.
State-of-the-art packet-switched routers can of course utilize multiple unicast messages to achieve multicast functionality.
Decomposing a multicast into several unicasts can consume additional cycles and cause a bottleneck at the injection port as multiple messages try to access the network in the same cycle. In the baseline router, this injection bottleneck can add several cycles to the average network latency.
''Gola:'' The goal of this research is to devise a new fault-tolenat multicast routing algorithm for NASH system.
[[Reference>https://drive.google.com/file/d/0B2HMlO4p7SuwU01XUkVJLXdjdEU/view?usp=sharing]]
*GT: COLOR(){ Aizuwakanatsu Taxi Demand Prediction System Using Neural Network} [#xa94d9bf]
''Motivation:'' Taxi services are important transportation method in almost any cities. The Taxi business is rapidly using IT technology to minimize vacant driving time and where to find passengers.
Predicting where to find passengers is a challenging problem which can be solved by neural networks.
''Goal'': The goal of this project is to design an NN model to estimate taxi demand and trained with historical taxi ride date for Aizuwakamatsu city.
*GT/MS: ON-LINE LEARNING ALGORITHM FOR SPIKING NEURO-CHIP SYSTEM [#jc9aea98]
''Motivation'':
The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died.
Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network.
SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse.
Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.
''Goal:'' The goal of this research is to design an on-line learning algorithm for Neuro-inpired systems.
References
*GT: Design of A Cognitive Network-on-Chip [#x52e634f]
''Motivation:'' The number of cores in a manycore chip has been increasing in the past decade. The rate of increase
will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important
design consideration.
''Goal:'' Design a new design method for implementing a cognitive OASIS network-on-chip that has the ability to recognize changes in the environment and to
learn new ways to adapt to the changes. This learning method should provide the network to manage itself to achieve low network latency, higher reliability, power efficiency,
and adaptability. Fault-tolerant routing should be considered.
*GT: Brain-inspired Smart System for Handicapped People [#e0a0b4ad]
''Motivation:''One of the goals in implantable BMI (brain machine interface) systems is to record and interpret neural signals from the motor cortex and use it to control artificial actuators. This will help handicapped people to control artificial limbs with their thoughts. Current solutions transmit all data to an off-chip device for processing. This results in a large data rate and latency which affect the scalability and performance of the system.
''Gola:''The goal of this project is to develop a neural network on-chip to directly process and interpret these brain signals on-chip leading to a scalable and fast system.
*Neumercail Findinsg [#db14a331]
-On-chip networks consume a significant fraction of total on-chip power [5], [42]; up to 30% for Intel’s 80-core teraflops network [15] and 36% for the RAW [39] on-chip network.
--[5]S. Borkar, “Networks for multi-core chips: A contrarian view,” Special Session at ISLPED 2007.
--[15] Intel, “From a few cores to many: A Terascale computing research overview,” 2006. [Online]. Available: http://download.intel.com/research/platform/terascale/ terascale
overview paper.pdf
--[39]M. B. Taylor et. al, “Scalar operand networks: On-chip interconnect for
ILP in partitioned architectures,” in HPCA, 2003.
--[42]H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, “Orion: A powerperformance simulator for interconnection networks,” in MICRO-35, 2002
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