Akram Ben Ahmed/Fault-Tolerant-NoC-References
をテンプレートにして作成
[
トップ
] [
新規
|
一覧
|
単語検索
|
最終更新
|
ヘルプ
|
ログイン
]
開始行:
[[Akram Ben Ahmed]]
#CONTENTS
*2014 [#ee613dc9]
- M. Ebrahimi. Reliable and Adaptive Routing Algorithms for 2D and 3D
Networks-on-Chip. Routing Algorithms in Networks-on-Chip, Springer, 2014.
*2013 [#ee653dc9]
- M. Ebrahimi, M. Daneshtalab, J. Plosila, and F. Mehdipour, MD: Minimal
path-based Fault-Tolerant Routing in On-Chip Networks. In Proc. of 18th
Asia and South Pacific Design Automation Conference, pages 35-40, January
2013.
- M. Ebrahimi, M. Daneshtalab, and J. Plosila. Fault-Tolerant Routing Algo-
rithm for 3D NoC Using Hamiltonian Path Strategy. In Proc. of Design, Au-
tomation & Test in Europe Conference & Exhibition (DATE), pages 1601-1604,
March 2013.
- M. Radetzki , Ch. Feng , X. Zhao , and A. Jantsch, Methods for Fault Tol-
erance in Networks-on-Chip, ACM Computing Surveys (CSUR), v.46 n.1, pp
1-38, October 2013
- P. Poluri and A. Louri In Proceedings of the 25th International Symposium
on Computer Architecture and High Performance Computing (SBAC-PAD) ,
pp. 49-56, October 23-26, 2013
*2012 [#ee453dc9]
- M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, MAFA: Adap-
tive Fault-Tolerant Routing Algorithm for Networks-on-Chip. In Proc. of 15th
Euromicro Conference on Digital System Design, pages 201-207, September
2012.
- A. -M. Rahmani, K. R. Vaddina, K. Latif, P. Liljeberg, J. Plosila and H. Tenhunen. Design and Management of High-performance, Reliable and Thermal-
aware 3D Networks-on-Chip. IET Circuits, Devices & Systems, 6(5):308-321,
September 2012.
- S. Akbari, A. Shaffeey, M. Fathy and R. Berangi. AFRA: A Low Cost High
Performance Reliable Routing for 3D Mesh NoCs. Design, Automation & Test
in Europe Conference & Exhibition, pages 332-337, March 2012.
- A. DeOrio, D. Fick, V. Bertacco, D. Sylvester, D. Blaauw, J. Hu, and G. Chen. A Reliable Routing Architecture and Algorithm for NoCs. IEEE Transactions on CAD of Integrated Circuits and Systems, 31(5):726-739, May 2012.
*2011 [#ee653dc0]
- C. Liu, L. Zhang, Y. Han, and X. Li, A resilient on-chip router design through data path salvaging, in Proc. ASPDAC, Jan. 2011, pp. 437-442.
- S. Pasricha and Y. Zou. A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip. The 12th International Symposium on Quality Electronic Design, pages 1-8, March 2011.
*2010 [#ee653dc3]
- S. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F.
Silla, and J. Duato, Addressing manufacturing challenges with costecient
fault tolerant routing, in Proc. NoCs, May 2010, pp. 25-32.
- Ch. Feng, Z. Lu, A. Jantsch, J. Li and M. Zhang. A Recongurable Fault-tolerant Deection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip. The 3rd International Workshop on Network on Chip Architectures, pages 11-16, December 2010.
*2009 [#ee653dc2]
- A. Kohler and M. Radetzki, Fault-tolerant architecture and deection routing for degradable NoC switches, in Proc. NoCs, May 2009, pp. 22-31.
- W. Song, D. Edwards, J. Nunez-Yanez, and S. Dasgupta, Adaptive stochastic routing in fault-tolerant on-chip networks, in Proc. NoCs, May 2009, pp. 32-37.
- S. Pasricha. Exploring serial vertical interconnects for 3D ICs. In DAC 09:
Proceedings of the 46th Annual Design Automation Conference, pages 581586,
2009. ACM.
- D. Xiang, Y. Zhang and Y. Pan. Practical Deadlock-Free Fault-Tolerant Routing Based on the Planar Network Fault Model. IEEE Transactions on Computers, 58(5):620-633, May 2009.
*2008 [#ee653dc4]
- Z. Zhang, A. Greiner, and S. Taktak, A recongurable routing algorithm for
fault-tolerant 2-D-mesh network-on-chip, in Proc. DAC, Jun. 2008, pp. 441-446.
- I. Loi, S.h Mitra, Th. H. Lee, Sh. Fujita, and L. Benini. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. In ICCAD 08:
Proceedings ofthe 2008 IEEE/ACM International Conference on Computer-
Aided Design, pages 598602, 2008.
- Z. Jiang, J. Wu and D. Wang. A New Fault Information Model for Fault-
Tolerant Adaptive and Minimal Routing in 3-D Meshes. IEEE Transactions
on Reliability, 57(1):149-162, March 2008.
*2007 [#ee653dc5]
- P. Bogdan, T. Dumitras, and R. Marculescu, Stochastic communication: A
new paradigm for fault-tolerant networks-on-chip, VLSI Des., vol. 2007, no.
95348, p. 17, 2007.
- T. Lehtonen, P. Liljeberg and J. Plosila. Online Reconfigurable Self-timed links for Fault Tolerant NoC. VLSI Design, (2007):1-13, 2007.
*2006 [#ee653dc6]
- F. L. Kastensmidt, Luigi Carro, and Ricardo Reis. Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing). Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2006.
- K. Constantinides et.al, BulletProof: A defect-tolerant CMP switch ar-
chitecture, in Proceedings of the 12th International Symposium on High-
Performance Computer Architecture (HPCA), pp. 5-16, 2006.
- J. Kim, et.al A Gracefully Degrading and Energy-Ecient Modular Router
Architecture for On-Chip Networks, in Proceedings of the 33rd International
Symposium on Computer Architecture (ISCA), 2006.
*2005 [#ee653dc7]
- M. Nicolaidis. Design for soft error mitigation. IEEE Trans. Device and Matl.Reliability, 5(3):405418, 2005.
- Y. Li, Shietung Peng, and Wanming Chu. Adaptive box-based ecient fault- tolerant routing in 3D torus. In Proceedings of the 11th International Conference on Parallel and Distributed Systems, pages 71-77, 2005.
*2004 [#ee653dc8]
-M. E. Gomez, J. Duato, J. Flich, P. Lopez, A. Robles, N. A. Nordbotten, O.
Lysne, and T. Skeie, An ecient fault-tolerant routing methodology for meshes
and tori, IEEE Comput. Architecture Lett., vol. 3, no. 1, p. 3, Jan.Dec. 2004.
- N.A. Nordbotten, M.E. Gmez, J. Flich, P. Lopez, A. Robles, T. Skeie, O.
Lysne, and J. Duato. A Fully Adaptive Fault-Tolerant Routing Methodology
Based on Intermediate Nodes. In Proc. IFIP Int'l Conf. Network and Parallel
Computing, pages 341-356, Oct. 2004.
*2003 [#he2b1ba9]
- M.-J. Tsai, Fault-tolerant routing in wormhole meshes, J. Interconnection
Netw., vol. 4, no. 4, pp. 463-495, 2003.
- J. Wu, "A simple fault-tolerant adaptive and minimal routing approach in 3-d meshes", Journal of Computer Science and Technology, vol: 18-1, pp. 1-13,
2003.
*2000 [#z0d36683]
- W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos, The
reliable router: A reliable and high-performance communication substrate for
parallel computers, in Proc. PCRCW, 1994, pp. 241-255.
- P.-H. Sui and S.-D. Wang, Fault-tolerant wormhole routing algorithms for
mesh networks, IEEE Comput. Digit. Tech., vol. 147, no. 1, p. 9, Jan. 2000.
- J. Wu. A Fault-tolerant Adaptive and Minimal Routing Approach in 3-D
Meshes. The 7th International Conference on Parallel and Distributed Sys-
tems, pages 149-159, July 2000.
- J. Wu. Fault-tolerant Adaptive and Minimal Routing in Mesh-connected Multicomputer Using Extended Safety Levels. IEEE Transactions on Parallel and
Distributed Systems, 11(2):149-159, February 2000.
*Before 2000 [#se2575a6]
- J. Duato, A theory of fault-tolerant routing in wormhole networks, IEEE
Trans. Parallel Distributed Syst., vol. 8, no. 8, pp. 790802, Aug. 1997.
- S.-P. Kim and T. Han, Fault-tolerant wormhole routing in mesh with over-
lapped solid fault regions, Parallel Comput., vol. 23, no. 13, pp. 1937-1962, Dec. 1997.
-A. A. Chien and J. H. Kim. Planar-adaptive Routing: Low-cost Adaptive
Networks for Multiprocessors. The 19th Annual International Symposium on
Computer Architecture, pages 268-277, 1992.
----
*Fault-Tolerant NoC Journal papers from [[IEEE Journal Xpolre>http://ieeexplore.ieee.org/search/searchresult.jsp?refinements%3D4291944246%26searchField%3DSearch_All%26queryText%3DFault-Tolerant+Network-on-Chip&addRange=2012_2012_Publication_Year&pageNumber=1&resultAction=REFINE]] [#ob9dd85f]
*3D Topologies and TSVs [#u8d7cbff]
-V. F. Pavlidis, E. G. Friedman, [[''3-D topologies for networks-on-chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4303130'']], IEEE Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090, Oct. 2007.
*Tools [#zfdc7e84]
Some of the simulators and NoC evaluation platforms built by the NoC research community to study various NoC designs are discussed. Some of the significant features of each of the implementations are also highlighted [[[referece2012>http://www.tr.ietejournals.org/article.asp?issn=0256-4602;year=2012;volume=29;issue=4;spage=318;epage=335;aulast=Kumar#ref75]]].
-''Orion''
-- A power and area model of on-chip interconnection networks that helps in quick explorations of different NoC designs [see bellow ref] . The motivation behind building such a framework is to estimate the power and area of the interconnect early in the design phase, as they are crucial for an optimized design. As a feature, this framework automatically updates itself as and when a new technology library becomes available. The simulator models all the router components and also the links that form the interconnection network.
---H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proceedings. 35th Annual IEEE/ACM International Symposium on Microarchitecture, p. 294-305, 2002
-''Hotspot''
-- HotSpot [see ref. bellow] is an accurate and fast thermal model suitable for use in architectural studies. It is based on an equivalent circuit of thermal resistances and capacitances that correspond to micro-architecture blocks and essential aspects of the thermal package. The model has been validated using finite element simulation. HotSpot has a simple set of interfaces and hence can be integrated with most power-performance simulators like Wattch [see ref bellow] . The chief advantage of HotSpot is that it is compatible with the kinds of power/performance models used by the computer-architecture community, requiring no detailed design or synthesis description. HotSpot makes it possible to study thermal evolution over long periods of real, full-length applications.
---K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proceedings. 30th Annual International Sympo- sium on Computer Architecture, p. 2-13, June 2003
---D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proceedings of the 27th annual international symposium on Computer architecture, p. 83-94, 2000.
-''HSpice''
-- HSpice [see ref. bellow] is the industry's standard for accurate and comprehensive circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms.
---"70nm PTM Technology Model." [Online]. Available from: http://www.eas.asu.edu/ptm [Last accessed on 2011 July 31].
-''DevEdit''
-- DevEdit, a product of Silvaco, Inc., is a tool that can be used to either create a device from scratch or to edit an existing device. DevEdit creates standard Silvaco structures that are easily integrated into Silvaco 2-D or 3-D simulators and other support tools.
終了行:
[[Akram Ben Ahmed]]
#CONTENTS
*2014 [#ee613dc9]
- M. Ebrahimi. Reliable and Adaptive Routing Algorithms for 2D and 3D
Networks-on-Chip. Routing Algorithms in Networks-on-Chip, Springer, 2014.
*2013 [#ee653dc9]
- M. Ebrahimi, M. Daneshtalab, J. Plosila, and F. Mehdipour, MD: Minimal
path-based Fault-Tolerant Routing in On-Chip Networks. In Proc. of 18th
Asia and South Pacific Design Automation Conference, pages 35-40, January
2013.
- M. Ebrahimi, M. Daneshtalab, and J. Plosila. Fault-Tolerant Routing Algo-
rithm for 3D NoC Using Hamiltonian Path Strategy. In Proc. of Design, Au-
tomation & Test in Europe Conference & Exhibition (DATE), pages 1601-1604,
March 2013.
- M. Radetzki , Ch. Feng , X. Zhao , and A. Jantsch, Methods for Fault Tol-
erance in Networks-on-Chip, ACM Computing Surveys (CSUR), v.46 n.1, pp
1-38, October 2013
- P. Poluri and A. Louri In Proceedings of the 25th International Symposium
on Computer Architecture and High Performance Computing (SBAC-PAD) ,
pp. 49-56, October 23-26, 2013
*2012 [#ee453dc9]
- M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, MAFA: Adap-
tive Fault-Tolerant Routing Algorithm for Networks-on-Chip. In Proc. of 15th
Euromicro Conference on Digital System Design, pages 201-207, September
2012.
- A. -M. Rahmani, K. R. Vaddina, K. Latif, P. Liljeberg, J. Plosila and H. Tenhunen. Design and Management of High-performance, Reliable and Thermal-
aware 3D Networks-on-Chip. IET Circuits, Devices & Systems, 6(5):308-321,
September 2012.
- S. Akbari, A. Shaffeey, M. Fathy and R. Berangi. AFRA: A Low Cost High
Performance Reliable Routing for 3D Mesh NoCs. Design, Automation & Test
in Europe Conference & Exhibition, pages 332-337, March 2012.
- A. DeOrio, D. Fick, V. Bertacco, D. Sylvester, D. Blaauw, J. Hu, and G. Chen. A Reliable Routing Architecture and Algorithm for NoCs. IEEE Transactions on CAD of Integrated Circuits and Systems, 31(5):726-739, May 2012.
*2011 [#ee653dc0]
- C. Liu, L. Zhang, Y. Han, and X. Li, A resilient on-chip router design through data path salvaging, in Proc. ASPDAC, Jan. 2011, pp. 437-442.
- S. Pasricha and Y. Zou. A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip. The 12th International Symposium on Quality Electronic Design, pages 1-8, March 2011.
*2010 [#ee653dc3]
- S. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F.
Silla, and J. Duato, Addressing manufacturing challenges with costecient
fault tolerant routing, in Proc. NoCs, May 2010, pp. 25-32.
- Ch. Feng, Z. Lu, A. Jantsch, J. Li and M. Zhang. A Recongurable Fault-tolerant Deection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip. The 3rd International Workshop on Network on Chip Architectures, pages 11-16, December 2010.
*2009 [#ee653dc2]
- A. Kohler and M. Radetzki, Fault-tolerant architecture and deection routing for degradable NoC switches, in Proc. NoCs, May 2009, pp. 22-31.
- W. Song, D. Edwards, J. Nunez-Yanez, and S. Dasgupta, Adaptive stochastic routing in fault-tolerant on-chip networks, in Proc. NoCs, May 2009, pp. 32-37.
- S. Pasricha. Exploring serial vertical interconnects for 3D ICs. In DAC 09:
Proceedings of the 46th Annual Design Automation Conference, pages 581586,
2009. ACM.
- D. Xiang, Y. Zhang and Y. Pan. Practical Deadlock-Free Fault-Tolerant Routing Based on the Planar Network Fault Model. IEEE Transactions on Computers, 58(5):620-633, May 2009.
*2008 [#ee653dc4]
- Z. Zhang, A. Greiner, and S. Taktak, A recongurable routing algorithm for
fault-tolerant 2-D-mesh network-on-chip, in Proc. DAC, Jun. 2008, pp. 441-446.
- I. Loi, S.h Mitra, Th. H. Lee, Sh. Fujita, and L. Benini. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. In ICCAD 08:
Proceedings ofthe 2008 IEEE/ACM International Conference on Computer-
Aided Design, pages 598602, 2008.
- Z. Jiang, J. Wu and D. Wang. A New Fault Information Model for Fault-
Tolerant Adaptive and Minimal Routing in 3-D Meshes. IEEE Transactions
on Reliability, 57(1):149-162, March 2008.
*2007 [#ee653dc5]
- P. Bogdan, T. Dumitras, and R. Marculescu, Stochastic communication: A
new paradigm for fault-tolerant networks-on-chip, VLSI Des., vol. 2007, no.
95348, p. 17, 2007.
- T. Lehtonen, P. Liljeberg and J. Plosila. Online Reconfigurable Self-timed links for Fault Tolerant NoC. VLSI Design, (2007):1-13, 2007.
*2006 [#ee653dc6]
- F. L. Kastensmidt, Luigi Carro, and Ricardo Reis. Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing). Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2006.
- K. Constantinides et.al, BulletProof: A defect-tolerant CMP switch ar-
chitecture, in Proceedings of the 12th International Symposium on High-
Performance Computer Architecture (HPCA), pp. 5-16, 2006.
- J. Kim, et.al A Gracefully Degrading and Energy-Ecient Modular Router
Architecture for On-Chip Networks, in Proceedings of the 33rd International
Symposium on Computer Architecture (ISCA), 2006.
*2005 [#ee653dc7]
- M. Nicolaidis. Design for soft error mitigation. IEEE Trans. Device and Matl.Reliability, 5(3):405418, 2005.
- Y. Li, Shietung Peng, and Wanming Chu. Adaptive box-based ecient fault- tolerant routing in 3D torus. In Proceedings of the 11th International Conference on Parallel and Distributed Systems, pages 71-77, 2005.
*2004 [#ee653dc8]
-M. E. Gomez, J. Duato, J. Flich, P. Lopez, A. Robles, N. A. Nordbotten, O.
Lysne, and T. Skeie, An ecient fault-tolerant routing methodology for meshes
and tori, IEEE Comput. Architecture Lett., vol. 3, no. 1, p. 3, Jan.Dec. 2004.
- N.A. Nordbotten, M.E. Gmez, J. Flich, P. Lopez, A. Robles, T. Skeie, O.
Lysne, and J. Duato. A Fully Adaptive Fault-Tolerant Routing Methodology
Based on Intermediate Nodes. In Proc. IFIP Int'l Conf. Network and Parallel
Computing, pages 341-356, Oct. 2004.
*2003 [#he2b1ba9]
- M.-J. Tsai, Fault-tolerant routing in wormhole meshes, J. Interconnection
Netw., vol. 4, no. 4, pp. 463-495, 2003.
- J. Wu, "A simple fault-tolerant adaptive and minimal routing approach in 3-d meshes", Journal of Computer Science and Technology, vol: 18-1, pp. 1-13,
2003.
*2000 [#z0d36683]
- W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos, The
reliable router: A reliable and high-performance communication substrate for
parallel computers, in Proc. PCRCW, 1994, pp. 241-255.
- P.-H. Sui and S.-D. Wang, Fault-tolerant wormhole routing algorithms for
mesh networks, IEEE Comput. Digit. Tech., vol. 147, no. 1, p. 9, Jan. 2000.
- J. Wu. A Fault-tolerant Adaptive and Minimal Routing Approach in 3-D
Meshes. The 7th International Conference on Parallel and Distributed Sys-
tems, pages 149-159, July 2000.
- J. Wu. Fault-tolerant Adaptive and Minimal Routing in Mesh-connected Multicomputer Using Extended Safety Levels. IEEE Transactions on Parallel and
Distributed Systems, 11(2):149-159, February 2000.
*Before 2000 [#se2575a6]
- J. Duato, A theory of fault-tolerant routing in wormhole networks, IEEE
Trans. Parallel Distributed Syst., vol. 8, no. 8, pp. 790802, Aug. 1997.
- S.-P. Kim and T. Han, Fault-tolerant wormhole routing in mesh with over-
lapped solid fault regions, Parallel Comput., vol. 23, no. 13, pp. 1937-1962, Dec. 1997.
-A. A. Chien and J. H. Kim. Planar-adaptive Routing: Low-cost Adaptive
Networks for Multiprocessors. The 19th Annual International Symposium on
Computer Architecture, pages 268-277, 1992.
----
*Fault-Tolerant NoC Journal papers from [[IEEE Journal Xpolre>http://ieeexplore.ieee.org/search/searchresult.jsp?refinements%3D4291944246%26searchField%3DSearch_All%26queryText%3DFault-Tolerant+Network-on-Chip&addRange=2012_2012_Publication_Year&pageNumber=1&resultAction=REFINE]] [#ob9dd85f]
*3D Topologies and TSVs [#u8d7cbff]
-V. F. Pavlidis, E. G. Friedman, [[''3-D topologies for networks-on-chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4303130'']], IEEE Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090, Oct. 2007.
*Tools [#zfdc7e84]
Some of the simulators and NoC evaluation platforms built by the NoC research community to study various NoC designs are discussed. Some of the significant features of each of the implementations are also highlighted [[[referece2012>http://www.tr.ietejournals.org/article.asp?issn=0256-4602;year=2012;volume=29;issue=4;spage=318;epage=335;aulast=Kumar#ref75]]].
-''Orion''
-- A power and area model of on-chip interconnection networks that helps in quick explorations of different NoC designs [see bellow ref] . The motivation behind building such a framework is to estimate the power and area of the interconnect early in the design phase, as they are crucial for an optimized design. As a feature, this framework automatically updates itself as and when a new technology library becomes available. The simulator models all the router components and also the links that form the interconnection network.
---H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proceedings. 35th Annual IEEE/ACM International Symposium on Microarchitecture, p. 294-305, 2002
-''Hotspot''
-- HotSpot [see ref. bellow] is an accurate and fast thermal model suitable for use in architectural studies. It is based on an equivalent circuit of thermal resistances and capacitances that correspond to micro-architecture blocks and essential aspects of the thermal package. The model has been validated using finite element simulation. HotSpot has a simple set of interfaces and hence can be integrated with most power-performance simulators like Wattch [see ref bellow] . The chief advantage of HotSpot is that it is compatible with the kinds of power/performance models used by the computer-architecture community, requiring no detailed design or synthesis description. HotSpot makes it possible to study thermal evolution over long periods of real, full-length applications.
---K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proceedings. 30th Annual International Sympo- sium on Computer Architecture, p. 2-13, June 2003
---D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proceedings of the 27th annual international symposium on Computer architecture, p. 83-94, 2000.
-''HSpice''
-- HSpice [see ref. bellow] is the industry's standard for accurate and comprehensive circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms.
---"70nm PTM Technology Model." [Online]. Available from: http://www.eas.asu.edu/ptm [Last accessed on 2011 July 31].
-''DevEdit''
-- DevEdit, a product of Silvaco, Inc., is a tool that can be used to either create a device from scratch or to edit an existing device. DevEdit creates standard Silvaco structures that are easily integrated into Silvaco 2-D or 3-D simulators and other support tools.
ページ名: