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開始行:
[[Akram Ben Ahmed]]
*References For my Research [#s5a6979d]
***IEEE Micro [#nc963d0d]
- IEEE Micro, Volume: 27 , Issue: 5 , 2007:
--On-Chip Interconnects for Multicores http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=4378774
**Thermal Power [#k1976b1b]
-[[Traffic- and Thermal-Aware Run-Time Thermal Management>http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0CFsQFjAE&url=http%3A%2F%2Fwww.minatec.org%2Fnocs2010%2FPresentations%2FNOCS2010%2520-%2520NA8%2520-%252004%2520-%2520Chihhao%2520Chao%2520-%2520Traffic%2520and%2520Thermal%2520Aware%2520Run%2520Time.pdf&ei=_bbnT5uTOsucmQXA0ZyfCw&usg=AFQjCNGfBJhkQ1kUXX-mluQ0G8dNnFy_ZQ&sig2=yAhWJ5Runya1D1v-Oi4uNw]], Presentation for NOCS2010 in Grenoble, France May 6, 2010, 
--[[paper>http://access.ee.ntu.edu.tw/Publications/Conference/LCA28_2011.pdf]]
--Power Model [[A 5-GHz Mesh Interconnect for A Teraflops Processor>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4378783]],Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, ,IEEE MICRO, vol. 27, pp. 51-61, 2007.
**Miss [#heb25cca]
-[[LaztZ>http://www.computer.org/plugins/dl/pdf/proceedings/pdp/2012/4633/00/4633a507.pdf?template=1&loginState=2&userData=TRIAL%2B%257E%2BUniversity%2Bof%2BAizu%253ATRIAL%2B%257E%2BUniversity%2Bof%2BAizu%253AAddress%253A%2B163.143.95.126%252C%2B%255B172.16.161.5%252C%2B163.143.95.126%252C%2B23.3.104.158%255D&download=true]]
-S. F. AlSarawi, D. Abbott, and P. D. Franzon,  [["A review of 3-D packaging technology">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=659500&tag=1]],  IEEE Trans. Compon. Packag. Manufact. Technol. Part B\―Adv. Packag.,  vol. 21,  pp.2 -14 1998.
-12. BookSim [[Website>https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/BookSim]]
-- [[Evaluating Bufferless Flow Control for On-Chip Networks>http://csl.stanford.edu/~christos/publications/2010.bufferlesseval.nocs.pdf]] using BookSim
- 11. [[A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking>http://www.cse.psu.edu/~tzz106/doc/3DIC10.pdf]], 2010.
- 10. [[A Framework for Designing Deadlock-Free Wormhole Routing Algorithms>http://www.cs.pitt.edu/~melhem/courses/3410p/papers_p/deadlock.pdf]], IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 7, NO. 2, FEBRUARY 1996. 
- 9. http://www.design-reuse.com/articles/21583/processor-noc-fpga.html
-- http://www.eve-team.com/pdf/D_Sessions_Session4_S47.pdf
-- http://www.arteris.com/flexnoc
- 8. [[Introduction to JPEG>http://en.wikipedia.org/wiki/JPEG]] 
&ref(http://aslweb.u-aizu.ac.jp/~m5141153/2011/RPR/JPEG.pptx,,"Slides, July 25th ");
-6. [[Design of new pipeline router for-NoC>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=13.Design-of-new-pipeline-router-for-NoC.pdf&refer=Akram]], Proceedings of the 2005 Workshop on Consumer Electronics and Signal Processing  ( WCEsp 2005 )
-5. [[Design-of-a-Distributed-JPEG-Encoder-on-a-Scalable-NoC-Platform>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=Design-of-a-Distributed-JPEG-Encoder-on-a-Scalable-NoC-Platform.pdf&refer=Akram]], IEEE 2008.
-4.[[PDF>http://vader.ece.ucsb.edu/plogicpci/pdf/JRthesis.pdf]] JPEG Image Compression Using an FPGA, MS thesis, 2008.
-3. [[PDF>http://portal.acm.org/ft_gateway.cfm?id=1973021&ftid=953222&dwn=1&CFID=33394554&CFTOKEN=10078141]] Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip, ACM 2011. 
&ref(http://aslweb.u-aizu.ac.jp/~m5141153/2011/RPR/MOEA.pptx,,"Slides, August 25th "); 
-2. [[Thermal-aware mapping and placement for 3-D NoC designs>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1554447&tag=1]]
--K. Banerjee, S. J. Souri, P. Kapur, and K.C. Saraswat, "[[3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration>http://www.google.co.jp/url?sa=t&rct=j&q=3-d%20ics%3A%20a%20novel%20chip%20design%20for%20improving%20deep%20submicrometer%20interconnect%20performance%20and%20systems-on-chip%20integration&source=web&cd=2&ved=0CC4QFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.22.2773%26rep%3Drep1%26type%3Dpdf&ei=1Jq8TputLYnKmAX8lYDABA&usg=AFQjCNEw_JiJ0Y2fucNpqP6etTu9S8O52A]]," in Proc. of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001.  
--J. Cong, J. Wei, and Y. Zhang," [[A Thermal-Driven Floorplanning Algorithm for 3D ICs>http://www.google.co.jp/url?sa=t&rct=j&q=a%20thermal-driven%20floorplanning%20algorithm%20for%203d%20ics&source=web&cd=1&ved=0CCEQFjAA&url=http%3A%2F%2Fcadlab.cs.ucla.edu%2F~cong%2Fpapers%2F3dfp.pdf&ei=pJq8TqrTKIjnmAW40oWMBA&usg=AFQjCNHmREJIoV74wxAYeXGYvP4D2mAjhQ]]," Proceedings of ICCAD, November 2004.  
-1. [[Exploring 3D NoC Architectures->http://www.mpsoc-forum.org/2008/slides/2-3%20Narayanan.pdf]], MPSoC 2008.
**Parallel Computation [#bf274003]
[[Models and languages for parallel computation>http://dl.acm.org/ft_gateway.cfm?id=280278&type=pdf&CFID=100549208&CFTOKEN=68288737]], 1998 ACM. 
**Others [#j5e43dd3]
-JSPS-2012 Application file '''[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/JSPS-2012.pdf]]''', '''[[DOC>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/JSPS-2012.doc]]'''
-''Thesis'', Proceedings of the International Systemon-
Chip Conference, pp. 25–28 (2005)
-[[Characterizing and Visualizing Contours in Regular 3D Mesh Topologies>http://etd.ohiolink.edu/send-pdf.cgi/Subedi%20Sanchita.pdf?akron1306866702]], MS thesis, 2011. ''Note'': This author referenced to your 3D work.
**[[Thermal on 3D-NoC>thermal]] [#uafb1d72]
**People working on 3D [#k752b081]
-[[Associate Prof. Yuan Xie>http://www.cse.psu.edu/~yuanxie/3d.html]], Pennsylvania State University.
-[[Prof. William J. Dally>http://cva.stanford.edu/billd_webpage_new.html]], Stanford University.
-http://www.mpsoc-forum.org/previous/2011/agenda.html#Session2
**Short-path-link [#v0509681]
-[[Design tradeoffs for tiled CMP on-chip networks>http://dl.acm.org/citation.cfm?id=1183430]], James Balfour, William J. Dally Stanford University,  Proceeding
ICS '06 Proceedings of the 20th annual international conference on Supercomputing
ACM New York, NY, USA ©2006
**NoC Simulators [#maad569f]
-http://research.cs.tamu.edu/codesign/nocsim/
**Virtual Channel [#r38fcc57]
-Original Idea: [[Deadlock-Free Message Routing in Multiprocessor Interconnection Networks >http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1676939]], IEEE Transactions on Computers, 
May 1987.
--Dally: [[Virtual Channel Flow-Control,ally's Virtual Cahnnel>http://www.cs.berkeley.edu/~kubitron/cs258/handouts/papers/dally-virtual.pdf]], IEEE transaction, 1992.
--[[Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing>http://dl.acm.org/citation.cfm?id=1531658]], 
GLSVLSI '09 Proceedings of the 19th ACM Great Lakes symposium on VLSI
Pages 511-516 ACM New York, NY, USA, 2009.
**BENCHMARKS [#c9d88026]
JPEG Decoder
-[[JPEG Decoder report>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=jepg_decoder.pdf&refer=Akram]]; [[JPEG Decoder presentation>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=jepg_decoderPresentation.pdf&refer=Akram]] 
**Fault Tolerant NoC[#q3c5b1f5]
-[[3D Fault Tolerant algorithm]]
-[[A Fault-Tolerant NoC Scheme Using Bidirectional Channel>http://aslweb.u-aizu.ac.jp/~m5141153/2012/RPR/RPR_07_25.pdf]]
**QoS NoC [#l715445f]
-QNoC: QoS architecture and design process  for 
Network on Chip: 
http://webee.technion.ac.il/matrics/papers/QNoC-Dec2003.pdf. COLOR(red){Please read and upload slides here by January 5, 2013.}
-----
*Optical NoC [#o2fd62af]
-http://www.ece.ust.hk/~eexu/index_files/bibliography.htm
''Last Update''
December 13th, 2012, ABA
終了行:
[[Akram Ben Ahmed]]
*References For my Research [#s5a6979d]
***IEEE Micro [#nc963d0d]
- IEEE Micro, Volume: 27 , Issue: 5 , 2007:
--On-Chip Interconnects for Multicores http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=4378774
**Thermal Power [#k1976b1b]
-[[Traffic- and Thermal-Aware Run-Time Thermal Management>http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0CFsQFjAE&url=http%3A%2F%2Fwww.minatec.org%2Fnocs2010%2FPresentations%2FNOCS2010%2520-%2520NA8%2520-%252004%2520-%2520Chihhao%2520Chao%2520-%2520Traffic%2520and%2520Thermal%2520Aware%2520Run%2520Time.pdf&ei=_bbnT5uTOsucmQXA0ZyfCw&usg=AFQjCNGfBJhkQ1kUXX-mluQ0G8dNnFy_ZQ&sig2=yAhWJ5Runya1D1v-Oi4uNw]], Presentation for NOCS2010 in Grenoble, France May 6, 2010, 
--[[paper>http://access.ee.ntu.edu.tw/Publications/Conference/LCA28_2011.pdf]]
--Power Model [[A 5-GHz Mesh Interconnect for A Teraflops Processor>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4378783]],Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, ,IEEE MICRO, vol. 27, pp. 51-61, 2007.
**Miss [#heb25cca]
-[[LaztZ>http://www.computer.org/plugins/dl/pdf/proceedings/pdp/2012/4633/00/4633a507.pdf?template=1&loginState=2&userData=TRIAL%2B%257E%2BUniversity%2Bof%2BAizu%253ATRIAL%2B%257E%2BUniversity%2Bof%2BAizu%253AAddress%253A%2B163.143.95.126%252C%2B%255B172.16.161.5%252C%2B163.143.95.126%252C%2B23.3.104.158%255D&download=true]]
-S. F. AlSarawi, D. Abbott, and P. D. Franzon,  [["A review of 3-D packaging technology">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=659500&tag=1]],  IEEE Trans. Compon. Packag. Manufact. Technol. Part B\―Adv. Packag.,  vol. 21,  pp.2 -14 1998.
-12. BookSim [[Website>https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/BookSim]]
-- [[Evaluating Bufferless Flow Control for On-Chip Networks>http://csl.stanford.edu/~christos/publications/2010.bufferlesseval.nocs.pdf]] using BookSim
- 11. [[A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking>http://www.cse.psu.edu/~tzz106/doc/3DIC10.pdf]], 2010.
- 10. [[A Framework for Designing Deadlock-Free Wormhole Routing Algorithms>http://www.cs.pitt.edu/~melhem/courses/3410p/papers_p/deadlock.pdf]], IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 7, NO. 2, FEBRUARY 1996. 
- 9. http://www.design-reuse.com/articles/21583/processor-noc-fpga.html
-- http://www.eve-team.com/pdf/D_Sessions_Session4_S47.pdf
-- http://www.arteris.com/flexnoc
- 8. [[Introduction to JPEG>http://en.wikipedia.org/wiki/JPEG]] 
&ref(http://aslweb.u-aizu.ac.jp/~m5141153/2011/RPR/JPEG.pptx,,"Slides, July 25th ");
-6. [[Design of new pipeline router for-NoC>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=13.Design-of-new-pipeline-router-for-NoC.pdf&refer=Akram]], Proceedings of the 2005 Workshop on Consumer Electronics and Signal Processing  ( WCEsp 2005 )
-5. [[Design-of-a-Distributed-JPEG-Encoder-on-a-Scalable-NoC-Platform>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=Design-of-a-Distributed-JPEG-Encoder-on-a-Scalable-NoC-Platform.pdf&refer=Akram]], IEEE 2008.
-4.[[PDF>http://vader.ece.ucsb.edu/plogicpci/pdf/JRthesis.pdf]] JPEG Image Compression Using an FPGA, MS thesis, 2008.
-3. [[PDF>http://portal.acm.org/ft_gateway.cfm?id=1973021&ftid=953222&dwn=1&CFID=33394554&CFTOKEN=10078141]] Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip, ACM 2011. 
&ref(http://aslweb.u-aizu.ac.jp/~m5141153/2011/RPR/MOEA.pptx,,"Slides, August 25th "); 
-2. [[Thermal-aware mapping and placement for 3-D NoC designs>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1554447&tag=1]]
--K. Banerjee, S. J. Souri, P. Kapur, and K.C. Saraswat, "[[3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration>http://www.google.co.jp/url?sa=t&rct=j&q=3-d%20ics%3A%20a%20novel%20chip%20design%20for%20improving%20deep%20submicrometer%20interconnect%20performance%20and%20systems-on-chip%20integration&source=web&cd=2&ved=0CC4QFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.22.2773%26rep%3Drep1%26type%3Dpdf&ei=1Jq8TputLYnKmAX8lYDABA&usg=AFQjCNEw_JiJ0Y2fucNpqP6etTu9S8O52A]]," in Proc. of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001.  
--J. Cong, J. Wei, and Y. Zhang," [[A Thermal-Driven Floorplanning Algorithm for 3D ICs>http://www.google.co.jp/url?sa=t&rct=j&q=a%20thermal-driven%20floorplanning%20algorithm%20for%203d%20ics&source=web&cd=1&ved=0CCEQFjAA&url=http%3A%2F%2Fcadlab.cs.ucla.edu%2F~cong%2Fpapers%2F3dfp.pdf&ei=pJq8TqrTKIjnmAW40oWMBA&usg=AFQjCNHmREJIoV74wxAYeXGYvP4D2mAjhQ]]," Proceedings of ICCAD, November 2004.  
-1. [[Exploring 3D NoC Architectures->http://www.mpsoc-forum.org/2008/slides/2-3%20Narayanan.pdf]], MPSoC 2008.
**Parallel Computation [#bf274003]
[[Models and languages for parallel computation>http://dl.acm.org/ft_gateway.cfm?id=280278&type=pdf&CFID=100549208&CFTOKEN=68288737]], 1998 ACM. 
**Others [#j5e43dd3]
-JSPS-2012 Application file '''[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/JSPS-2012.pdf]]''', '''[[DOC>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/JSPS-2012.doc]]'''
-''Thesis'', Proceedings of the International Systemon-
Chip Conference, pp. 25–28 (2005)
-[[Characterizing and Visualizing Contours in Regular 3D Mesh Topologies>http://etd.ohiolink.edu/send-pdf.cgi/Subedi%20Sanchita.pdf?akron1306866702]], MS thesis, 2011. ''Note'': This author referenced to your 3D work.
**[[Thermal on 3D-NoC>thermal]] [#uafb1d72]
**People working on 3D [#k752b081]
-[[Associate Prof. Yuan Xie>http://www.cse.psu.edu/~yuanxie/3d.html]], Pennsylvania State University.
-[[Prof. William J. Dally>http://cva.stanford.edu/billd_webpage_new.html]], Stanford University.
-http://www.mpsoc-forum.org/previous/2011/agenda.html#Session2
**Short-path-link [#v0509681]
-[[Design tradeoffs for tiled CMP on-chip networks>http://dl.acm.org/citation.cfm?id=1183430]], James Balfour, William J. Dally Stanford University,  Proceeding
ICS '06 Proceedings of the 20th annual international conference on Supercomputing
ACM New York, NY, USA ©2006
**NoC Simulators [#maad569f]
-http://research.cs.tamu.edu/codesign/nocsim/
**Virtual Channel [#r38fcc57]
-Original Idea: [[Deadlock-Free Message Routing in Multiprocessor Interconnection Networks >http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1676939]], IEEE Transactions on Computers, 
May 1987.
--Dally: [[Virtual Channel Flow-Control,ally's Virtual Cahnnel>http://www.cs.berkeley.edu/~kubitron/cs258/handouts/papers/dally-virtual.pdf]], IEEE transaction, 1992.
--[[Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing>http://dl.acm.org/citation.cfm?id=1531658]], 
GLSVLSI '09 Proceedings of the 19th ACM Great Lakes symposium on VLSI
Pages 511-516 ACM New York, NY, USA, 2009.
**BENCHMARKS [#c9d88026]
JPEG Decoder
-[[JPEG Decoder report>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=jepg_decoder.pdf&refer=Akram]]; [[JPEG Decoder presentation>http://aslweb.u-aizu.ac.jp/benlab/index.php?plugin=attach&pcmd=open&file=jepg_decoderPresentation.pdf&refer=Akram]] 
**Fault Tolerant NoC[#q3c5b1f5]
-[[3D Fault Tolerant algorithm]]
-[[A Fault-Tolerant NoC Scheme Using Bidirectional Channel>http://aslweb.u-aizu.ac.jp/~m5141153/2012/RPR/RPR_07_25.pdf]]
**QoS NoC [#l715445f]
-QNoC: QoS architecture and design process  for 
Network on Chip: 
http://webee.technion.ac.il/matrics/papers/QNoC-Dec2003.pdf. COLOR(red){Please read and upload slides here by January 5, 2013.}
-----
*Optical NoC [#o2fd62af]
-http://www.ece.ust.hk/~eexu/index_files/bibliography.htm
''Last Update''
December 13th, 2012, ABA
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