Akram Ben Ahmed
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開始行:
CENTER:SIZE(40){COLOR(#990199){High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems}}
CENTER:&ref(3Dtop.png,,40%);
----
Contents:
#CONTENTS
----
**Research Motivation [#of982f98]
Global interconnects are becoming the principal performance bottleneck for high performance Systems-on-Chips (SoCs). Since the main purpose for these systems is to shrink the size of the chip as smaller as possible while seeking at the same time for more scalability, higher bandwidth, and lower latency. Conventional bus-based-systems are no longer reliable architecture for SoCs due to the lack of scalability and parallelism integration, high latency and power dissipation, and low throughput. During this last decade, Network-on-Chip (NoC) interconnect has been proposed as a promising solution for future SoC designs. It offers more scalability than the shared-bus based interconnection and allows more processors to operate concurrently. Despite the higher scalability and parallelism integration offered by NoC over traditional shared-bus based systems, it is still not an ideal solution for future large scale SoCs. This is due to some limitations such as high power consumption, high cost communication, and low throughput. Recently, merging NoC to the third dimension (3D-NoCs) has been proposed to deal with those problems, as it was a solution offering lower power consumption and higher speed.
As 3D-NoC architectures started to show their outperformance and energy efficiency against 2D-NoC systems, questions about their reliability to sustain their performance growth begun to arise. This is mainly due to challenges inherited from both 3D-ICs and NoCs: On one side, the complex nature of 3D-IC fabrics and the continuing shrinkage of semiconductor components. Furthermore, the significant heterogeneity in 3D chips which are likely to mix logic layers with memory layers and even more complex technologies increases the fault's probability in a system. On the other side, the single-point-failure nature of NoC introduces a big concern to their reliability as they are the sole communication medium.
As a result, 3D-NoC systems are becoming susceptible to a variety of faults caused by cross-talk, electromagnetic interference, impact of radiations, oxide breakdown, and so on. A simple failure in a single transistor caused by one of these factors may compromise the entire system reliability where the failure can be illustrated in corrupted message delivery, time requirements unsatisfactory, or even sometimes the entire system collapse.
----
**Research Goal [#j5e43d03]
In this research we propose 3D-Fault-Tolerant-OASIS (3D-FTO), a robust fault-tolerant 3D-NoC router architecture endorsed with reliable and graceful routing algorithms. The proposed design handles a large number of faults in the input-buffer, crossbar, and links (which are the most susceptible components to faults in 3D-NoC systems) leveraging the inherent structural redundancy in the architecture to work around errors. Contrary to previous works, the proposed system tolerates multiple faults in a single crossbar with no considerable performance degradation. In addition, the used algorithms are always minimal (as long as there exist one minimal path) and with the aid of Random-Access-Buffer (RAB) mechanism, deadlock-freedom is ensured with no significant area nor power overhead.
----
**Research Plan [#e2a06435]
***Step 1 COLOR(blue){(Completed)} [#cf888fe4]
1- Survey about fault-tolerant routing algorithms in 3D-NoC systems.
2- Proposed and implement Look-Ahead-Fault-Tolerant (LAFT) to solve link failure.
3- Evaluate the performance of LAFT with Matrix, Transpose, and Uniform applications
***Step 2 COLOR(blue){(Completed)} [#ob382801]
1- Propose Random-Access-Buffer mechanism (RAB) to solve the deadlock in LAFT algorithm
2- Proposed Hybrid-Look-Ahead-Fault-Tolerant (HLAFT) routing algorithm that solves the drawbacks of LAFT by combining both look-ahead and local routing.
3- Implement and evaluate the performance of LAFT with JPEG, with Matrix, Transpose, and Uniform applications.
4- Compare the performance of HLAFT and LAFT
***Step 3 COLOR(blue){(Completed)} [#h591d782]
1- Optimize RAB to be able to recover from transient and permanent fault in the input-buffer.
2- Integrate Traffic-Prediction-Unit (TPU) with RAB to alleviate the congestion in faulty input-buffers
***Step 4 COLOR(blue){(Completed)} [#d325f669]
1- Implement Bypass-Link-on-Demand (BLoD) to tackle failures in the crossbar.
2- Evaluate the performance of BLoD when increasing the number of faults in the crossbar links
***Step 5 COLOR(blue){(Completed)} [#f9cc18e0]
1- Synthesize the entire reliable router including LAFT, RAB, TPU, and BLoD using Synopsys Design Compiler and obtain its hardware complexity.
2- Evaluate the latency/flit and throughput of the proposed router under different fault-rates
***Step 6 COLOR(blue){(Completed)} [#ye662169]
1- Write the first draft of the thesis. COLOR(blue){(Completed on October 10, 2014)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.rar]]]
2- Make the Doctoral Dissertation preliminary review COLOR(blue){(Presented on October 20, 2014)}
-- High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems.
[[[slides.pptx>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD/Prelim_Oct202014.pptx]]]
***Step 7 COLOR(blue){(Completed)} [#p80e8b77]
1- Write the second draft of the thesis for the final review. COLOR(blue){(Completed on January 07, 2015)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.rar]]]
2- Make the Doctoral Dissertation final review COLOR(blue){(Presented on January 14, 2015)}
-- High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems.
[[[slides.pptx>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.pptx]]]
***Step 8 COLOR(blue){(Completed)} [#p80e8177]
1- Design Through-Silicon-Vias and integrate it with the reliable router
2- Evaluate the complete router's hardware complexity (Area, power, clock frequency)
***Step 9 COLOR(blue){(Completed)} [#p80e8077]
1- Write the final draft of the thesis. COLOR(blue){(Completed on February 27, 2015)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Public/Public.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Public/Public.rar]]]
***Step 10 COLOR(red){(To be completed by March 27th)} [#p80e8077]
1- Make a detailed tutorial about the TSV implementation with 3D-OASIS-NoC router
**Achievement (Jnl/Conference Publications, Technical Reports, Students Guidance, Public presentations) [#wb31ce60]
CENTER:COLOR(red){UPCOMING CONFERENCES: http://aslweb.u-aizu.ac.jp/aslint/index.php?Conferences}
***COLOR(blue){Journal papers Under Review} [#md4217fb]
- 1 A. Ben Ahmed, A. Ben Abdallah, [[Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC systems>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC.pdf]], submitted to the ([[Journal of Parallel and Distributed Computing>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]) on February 10th, 2014.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC.rar]]).
-- Conditionally accepted on February 4th 2015
-- Revised manuscript submitted on February 22nd 2015 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC-14-26R1.pdf]])
***COLOR(blue){Conference papers Under Review} [#pb478a2e]
//- Akram Ben Ahmed, Nam Khanh Dang, Yuichi Okuyama, Abderazek Ben Abdallah, [[Architecture and Design of the Reliable Router for 3D-Network-on-Chips>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/2015/COMPSAC/COMPSAC]]. Submitted to ([[The 39th Annual International Computers, Software & Applications Conference>http://www.computer.org/web/compsac]]) January 27th 2015
//([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/2015/COMPSAC/COMPSAC.rar]])
***COLOR(blue){Published Journal Papers} [#u735ac7e]
- 2. A. Ben Ahmed, A. Ben Abdallah, [[Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC-preprint.pdf]]. To be published in the ([[Journal of Parallel and Distributed Computing>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]) in 2014
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC-preprint.rar]]), ([[Final>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC.pdf]])
- 1. A. Ben Ahmed, A. Ben Abdallah, [[Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC-preprint.pdf]], published in the ([[Journal of Supercomputing>http://www.springer.com/computer/swe/journal/11227]]). [[DOI>http://link.springer.com/article/10.1007%2Fs11227-013-0940-9]]: 10.1007/s11227-013-0940-9.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC-preprint.rar]]), ([[Final>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC.pdf]])
***COLOR(blue){Public Presentation @ Conferences } [#o56f8d37]
- 7 A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, [[Adaptive Error- and Traffic-aware Router Architecture for Electrical 3D Network-on-Chip Systems>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14.pdf]], the [[IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-14)>http://www.mcsoc-forum.org/]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14.rar]].
[[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14-slides.pdf]].
- 6. Ak. Ben Ahmed, Ach. Ben Ahmed, A. Ben Abdallah, [[Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6657906]]. IEEE 7th International Symposium on Embedded Multicore SoCs, National Institute of Informatics ([[MCSoC13>http://www.mcsoc-forum.org]]), Tokyo, Japan, September 26-28, 2013; ([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSOC13.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/13/MCSOC13-slides.pdf]]).
- 5. A. Ben Ahmed, Takayuki Ochi, Shohei Miura, A. Ben Abdallah, [[Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6603929]]''', The 6th International Workshop on Engineering Parallel and Multicore Systems ([[ePaMuS2013>http://www.lsi.upc.edu/~fatos/ePaMuS2013/index.html]]) July 2013. (''[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/EPAMUS.rar]]''),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/EPAMUS2013-slides.pdf]])
-4. A. Ben Ahmed, A. Ben Abdallah, [[Low-overhead Routing Algorithm for 3D Network-on-Chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6424540]], The Third International Conference on Networking and Computing ([[ICNC-12>http://www.ic-nc.org/]]) Dec. 2012. [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICNC12.rar]]
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICNC12-slides.pdf]])
- 3. A. Ben Ahmed, A. Ben Abdallah, [[LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6354695]], The IEEE 6th International Symposium on Embedded Multicore SoCs ([[MCSoC-12>http://www.ieee-mcsoc.org//]]) Sep. 2012. 
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC2012.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/12/MCSoC2012-slides.pdf]])
- 2. A. Ben Ahmed, K. Mori, A. Ben Abdallah, [[ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6469623]], The 4th International Conference on Awareness Science and Technology ([[iCAST-2012>http://icast2012.korea.ac.kr/]]) Aug. 2012.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICAST2012.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICAST2012-slides.pdf]])
- 1. A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, [[Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5633768]]''', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications ([[BWCCA-2010>http://www.lsi.upc.edu/~net4all/BWCCA-2010/]]), Nov. 2010. ([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/BWCCA2010.rar]]),
([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram-slides.pdf]])
***COLOR(blue){Theses and Technical Reports} [#u73fac7e]
- Akram Ben Ahmed, [[On the Design of a 3D Network-on-Chip for Many-core SoC >http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
- Akram Ben Ahmed, A. Ben Abdallah, On the Design of 3D Network-on-Chip, Technical Report, Adaptive System Laboratory, School of Computer Science and Engineering, The University of Aizu, March 2012, Ref. 14AKA-TR12.
([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/m5141153_TR.pdf]])
***[[Research and Publications Schedules >Akram Ben Ahmed/coming-journal-paper-schedule]] [#t0c78e2f]
**Related References [#hfcd540b]
*** References Related to Fault Tolerant NoC [#w3159bcf]
- Please refer to the following [[page>Akram Ben Ahmed/Fault-Tolerant-NoC-References]] for more information.
***OASIS 3D-Router [#b78ed7d4]
-Verilog Source Code
--[[3D-OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
-Physical Design
--[[OASIS 3D-Router Physical Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], July 2014.
-[[VLSI@ASL>http://aslweb.u-aizu.ac.jp/aslint/index.php?VLSI-Design]]
***3D/2D NoC References [#ma887ee7]
- [[Miscellaneous 3D-NoC References>http://aslweb.u-aizu.ac.jp/benlab/index.php?3D-NoC-References]]
-[[Fabrication of TSVs>http://aslweb.u-aizu.ac.jp/aslint/index.php?TSV]] [#rc8be140]
*[[Doctoral Dissertation>Akram-Thesis]] [#rc8be140]
[[Akram Ben Ahmed]]
CENTER:SIZE(50){COLOR(#990199){Thesis schedule}}
* Official thesis submission schedule from the [[University website>http://www.u-aizu.ac.jp/e-campus/e-calendar.html]] [#s814395d]
|BGCOLOR(#87CEFA):|BGCOLOR(#87CvFA):|c
|Procedure|Date|Note|
//////////////////////////////////////////////
/////////////// Preliminary Review////////////
//////////////////////////////////////////////
|Inquiry regarding thesis title and establishment of the Thesis Review Committee|Friday, July 31|SAD-> Chief Referee|
|Submission of "Report on the Determination of Doctoral Thesis Title" and "Recommendation of Candidates for a Doctoral Thesis Review Committee"|Wednesday, August 26|Student, Chief Referee-> SAD|
|GSAAC meeting (Deliberation on thesis title and establishment of Thesis Review Committee)|Wednesday, September 2|GSAAC|
|GSFA meeting (Deliberation/decision on thesis title and establishment of Thesis Review Committee)|Wednesday, September 9|GSFA|
|Inquiry regarding Preliminary Review schedule|Friday, September 25|SAD-> Chief Referee|
|Response regarding Preliminary Review schedule|Wednesday, October 7|Chief Referee-> SAD|
|GSAAC meeting (Approval of the implementation (schedule) of Preliminary Reviews)|Wednesday, October 14|GSAAC|
|GSFA meeting (Report on the implementation (schedule) of Preliminary Reviews)|Wednesday, October 21|GSFA|
|Submission of the documents for Preliminary Review|Monday, October 26|Student-> SAD|
|Preliminary Review|Tuesday, November 5-Friday, November 8||
|Submission of "Report on Results Regarding Doctoral Thesis Preliminary Review"|Monday, November 9|Thesis Review Committee->Dean|
|GSAAC meeting (Deliberation on the results from Preliminary Reviews)|Wednesday, November 11|GSAAC|
|GSFA meeting (Report on deliberation on the results from Preliminary Reviews)|Wednesday, November 18|GSFA|
|Notification of the results of deliberation|Friday, November 20|GSAAC -> Chief Referee-> Student|
//////////////////////////////////////////////
///////////////////// Final Review////////////
//////////////////////////////////////////////
|Inquiry regarding Final Review Schedule|Friday, November 20|SAD-> Chief Referee|
|Response regarding Final Review Schedule|Friday, November 27|Chief Referee-> SAD|
|GSAAC meeting (Approval of the implementation (schedule) of Final Reviews)|Friday, December 9|GSAAC|
|GSFA meeting (Report on the implementation (schedule) of Final Reviews)|Wednesday, December 16|GSFA|
|Submission of the documents for Final Review|Wednesday, January 6|Student-> SAD, Referees|
|Final Review|Tuesday, January 14- Thursday, January 16||
|Submission of "Report on Results Regarding The Final Doctoral Thesis Review"|Saturday, January 23|Thesis Review Committee->Dean|
|GSAAC meeting (Deliberation on the results from Final Review)|Friday, January 29|GSAAC|
|GSFA meeting (Report on deliberation on the results from Final Review)|Friday, February 5|GSFA|
|Notification of results of deliberation|Sunday, February 7|GSFA-> Chief Referee-> Student|
|Submission of the final thesis (including abstract) and "Application for the Academic Degree"|Wednesday, February 24|Student-> Dean, President|
|Submission of "Summary of the Doctoral Thesis Review Results"|Wednesday, February 24|Chief Referee-> Dean|
|GSAAC meeting (Deliberation on conferment of Academic Degree)|Wednesday, February 24|GSAAC|
|GSFA meeting (Authorization for conferment of Academic Degree)|Wednesday, March 2|GSFA|
|Submission of the materials for Thesis Presentation|Wednesday, March 2|Student-> SAD|
|Thesis Presentation|Tuesday, March 15||
|Degree Conferment Ceremony|Friday, March 18||
- Official detailed Schedule (tentative) can be found &ref(Doctor-schedule.pdf,,here);
----
* Graduation thesis contents [#x60vv334]
- Title: COLOR(red){High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems}
- Organization:
-- Abstract
-- Chapter 1: Introduction
-- Chapter 2: Network-on-Chip overview and Fault analysis
-- Chapter 3: Related work
-- Chapter 4: Fault-tolerant routing algorithms
-- Chapter 5: System Architecture
-- Chapter 6: Evaluation
-- Chapter 7: Conclusion & Future work
----
* Thesis Schedule [#x6024334]
|BGCOLOR(#87CEFA):|BGCOLOR(#87CEFA):|BGCOLOR(#87CEFA):|c
|Procedure|Completion deadline| Notes|
|Abstract|June 16th||
|Chapter 1: Introduction|June 23rd||
|Chapter 2: NoC overview adn Fault analysis|June 27th||
|Chapter 3: Related work|July 4th||
|Chapter 4: Routing algorithms|July 11th||
|Chapter 5: Router architecture|July 7th||
|Chapter 6: Evaluation|July 22nd||
|Chapter 7: Conclusion|July 22nd||
|Complete initial draft|July 23rd||
----
* [[Detailed thesis contents>Thesis-Content]] [#of2565e8]
----
* Thesis drafts [#of25g5e8]
** First draft: Completed on July 22, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-1st.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-1st.rar]]) [#hf15efd5]
** Second draft: Completed on October 10, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.rar]]) [#hf15eff5]
** Third draft: Completed on December 29, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-3rd.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-3rd.rar]]) [#hf15eff5]
** Fourth draft: Completed on January 7th, 2015 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-4th.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-4th.rar]]) [#hf15eff5]
----
Last update: Friday, October 10, 2015.
終了行:
CENTER:SIZE(40){COLOR(#990199){High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems}}
CENTER:&ref(3Dtop.png,,40%);
----
Contents:
#CONTENTS
----
**Research Motivation [#of982f98]
Global interconnects are becoming the principal performance bottleneck for high performance Systems-on-Chips (SoCs). Since the main purpose for these systems is to shrink the size of the chip as smaller as possible while seeking at the same time for more scalability, higher bandwidth, and lower latency. Conventional bus-based-systems are no longer reliable architecture for SoCs due to the lack of scalability and parallelism integration, high latency and power dissipation, and low throughput. During this last decade, Network-on-Chip (NoC) interconnect has been proposed as a promising solution for future SoC designs. It offers more scalability than the shared-bus based interconnection and allows more processors to operate concurrently. Despite the higher scalability and parallelism integration offered by NoC over traditional shared-bus based systems, it is still not an ideal solution for future large scale SoCs. This is due to some limitations such as high power consumption, high cost communication, and low throughput. Recently, merging NoC to the third dimension (3D-NoCs) has been proposed to deal with those problems, as it was a solution offering lower power consumption and higher speed.
As 3D-NoC architectures started to show their outperformance and energy efficiency against 2D-NoC systems, questions about their reliability to sustain their performance growth begun to arise. This is mainly due to challenges inherited from both 3D-ICs and NoCs: On one side, the complex nature of 3D-IC fabrics and the continuing shrinkage of semiconductor components. Furthermore, the significant heterogeneity in 3D chips which are likely to mix logic layers with memory layers and even more complex technologies increases the fault's probability in a system. On the other side, the single-point-failure nature of NoC introduces a big concern to their reliability as they are the sole communication medium.
As a result, 3D-NoC systems are becoming susceptible to a variety of faults caused by cross-talk, electromagnetic interference, impact of radiations, oxide breakdown, and so on. A simple failure in a single transistor caused by one of these factors may compromise the entire system reliability where the failure can be illustrated in corrupted message delivery, time requirements unsatisfactory, or even sometimes the entire system collapse.
----
**Research Goal [#j5e43d03]
In this research we propose 3D-Fault-Tolerant-OASIS (3D-FTO), a robust fault-tolerant 3D-NoC router architecture endorsed with reliable and graceful routing algorithms. The proposed design handles a large number of faults in the input-buffer, crossbar, and links (which are the most susceptible components to faults in 3D-NoC systems) leveraging the inherent structural redundancy in the architecture to work around errors. Contrary to previous works, the proposed system tolerates multiple faults in a single crossbar with no considerable performance degradation. In addition, the used algorithms are always minimal (as long as there exist one minimal path) and with the aid of Random-Access-Buffer (RAB) mechanism, deadlock-freedom is ensured with no significant area nor power overhead.
----
**Research Plan [#e2a06435]
***Step 1 COLOR(blue){(Completed)} [#cf888fe4]
1- Survey about fault-tolerant routing algorithms in 3D-NoC systems.
2- Proposed and implement Look-Ahead-Fault-Tolerant (LAFT) to solve link failure.
3- Evaluate the performance of LAFT with Matrix, Transpose, and Uniform applications
***Step 2 COLOR(blue){(Completed)} [#ob382801]
1- Propose Random-Access-Buffer mechanism (RAB) to solve the deadlock in LAFT algorithm
2- Proposed Hybrid-Look-Ahead-Fault-Tolerant (HLAFT) routing algorithm that solves the drawbacks of LAFT by combining both look-ahead and local routing.
3- Implement and evaluate the performance of LAFT with JPEG, with Matrix, Transpose, and Uniform applications.
4- Compare the performance of HLAFT and LAFT
***Step 3 COLOR(blue){(Completed)} [#h591d782]
1- Optimize RAB to be able to recover from transient and permanent fault in the input-buffer.
2- Integrate Traffic-Prediction-Unit (TPU) with RAB to alleviate the congestion in faulty input-buffers
***Step 4 COLOR(blue){(Completed)} [#d325f669]
1- Implement Bypass-Link-on-Demand (BLoD) to tackle failures in the crossbar.
2- Evaluate the performance of BLoD when increasing the number of faults in the crossbar links
***Step 5 COLOR(blue){(Completed)} [#f9cc18e0]
1- Synthesize the entire reliable router including LAFT, RAB, TPU, and BLoD using Synopsys Design Compiler and obtain its hardware complexity.
2- Evaluate the latency/flit and throughput of the proposed router under different fault-rates
***Step 6 COLOR(blue){(Completed)} [#ye662169]
1- Write the first draft of the thesis. COLOR(blue){(Completed on October 10, 2014)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.rar]]]
2- Make the Doctoral Dissertation preliminary review COLOR(blue){(Presented on October 20, 2014)}
-- High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems.
[[[slides.pptx>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD/Prelim_Oct202014.pptx]]]
***Step 7 COLOR(blue){(Completed)} [#p80e8b77]
1- Write the second draft of the thesis for the final review. COLOR(blue){(Completed on January 07, 2015)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.rar]]]
2- Make the Doctoral Dissertation final review COLOR(blue){(Presented on January 14, 2015)}
-- High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems.
[[[slides.pptx>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/FinalReview/Final.pptx]]]
***Step 8 COLOR(blue){(Completed)} [#p80e8177]
1- Design Through-Silicon-Vias and integrate it with the reliable router
2- Evaluate the complete router's hardware complexity (Area, power, clock frequency)
***Step 9 COLOR(blue){(Completed)} [#p80e8077]
1- Write the final draft of the thesis. COLOR(blue){(Completed on February 27, 2015)}
-- [[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Public/Public.pdf]]]
-- [[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Public/Public.rar]]]
***Step 10 COLOR(red){(To be completed by March 27th)} [#p80e8077]
1- Make a detailed tutorial about the TSV implementation with 3D-OASIS-NoC router
**Achievement (Jnl/Conference Publications, Technical Reports, Students Guidance, Public presentations) [#wb31ce60]
CENTER:COLOR(red){UPCOMING CONFERENCES: http://aslweb.u-aizu.ac.jp/aslint/index.php?Conferences}
***COLOR(blue){Journal papers Under Review} [#md4217fb]
- 1 A. Ben Ahmed, A. Ben Abdallah, [[Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC systems>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC.pdf]], submitted to the ([[Journal of Parallel and Distributed Computing>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]) on February 10th, 2014.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC.rar]]).
-- Conditionally accepted on February 4th 2015
-- Revised manuscript submitted on February 22nd 2015 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC(FTO)/JPDC-14-26R1.pdf]])
***COLOR(blue){Conference papers Under Review} [#pb478a2e]
//- Akram Ben Ahmed, Nam Khanh Dang, Yuichi Okuyama, Abderazek Ben Abdallah, [[Architecture and Design of the Reliable Router for 3D-Network-on-Chips>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/2015/COMPSAC/COMPSAC]]. Submitted to ([[The 39th Annual International Computers, Software & Applications Conference>http://www.computer.org/web/compsac]]) January 27th 2015
//([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/2015/COMPSAC/COMPSAC.rar]])
***COLOR(blue){Published Journal Papers} [#u735ac7e]
- 2. A. Ben Ahmed, A. Ben Abdallah, [[Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC-preprint.pdf]]. To be published in the ([[Journal of Parallel and Distributed Computing>http://www.journals.elsevier.com/journal-of-parallel-and-distributed-computing/]]) in 2014
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC-preprint.rar]]), ([[Final>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JPDC/JPDC.pdf]])
- 1. A. Ben Ahmed, A. Ben Abdallah, [[Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC-preprint.pdf]], published in the ([[Journal of Supercomputing>http://www.springer.com/computer/swe/journal/11227]]). [[DOI>http://link.springer.com/article/10.1007%2Fs11227-013-0940-9]]: 10.1007/s11227-013-0940-9.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC-preprint.rar]]), ([[Final>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/JSC/JSC.pdf]])
***COLOR(blue){Public Presentation @ Conferences } [#o56f8d37]
- 7 A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, [[Adaptive Error- and Traffic-aware Router Architecture for Electrical 3D Network-on-Chip Systems>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14.pdf]], the [[IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-14)>http://www.mcsoc-forum.org/]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14.rar]].
[[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/14/MCSOC14-slides.pdf]].
- 6. Ak. Ben Ahmed, Ach. Ben Ahmed, A. Ben Abdallah, [[Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6657906]]. IEEE 7th International Symposium on Embedded Multicore SoCs, National Institute of Informatics ([[MCSoC13>http://www.mcsoc-forum.org]]), Tokyo, Japan, September 26-28, 2013; ([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSOC13.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/13/MCSOC13-slides.pdf]]).
- 5. A. Ben Ahmed, Takayuki Ochi, Shohei Miura, A. Ben Abdallah, [[Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6603929]]''', The 6th International Workshop on Engineering Parallel and Multicore Systems ([[ePaMuS2013>http://www.lsi.upc.edu/~fatos/ePaMuS2013/index.html]]) July 2013. (''[[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/EPAMUS.rar]]''),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/EPAMUS2013-slides.pdf]])
-4. A. Ben Ahmed, A. Ben Abdallah, [[Low-overhead Routing Algorithm for 3D Network-on-Chip>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6424540]], The Third International Conference on Networking and Computing ([[ICNC-12>http://www.ic-nc.org/]]) Dec. 2012. [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICNC12.rar]]
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICNC12-slides.pdf]])
- 3. A. Ben Ahmed, A. Ben Abdallah, [[LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6354695]], The IEEE 6th International Symposium on Embedded Multicore SoCs ([[MCSoC-12>http://www.ieee-mcsoc.org//]]) Sep. 2012. 
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC2012.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/MCSoC/12/MCSoC2012-slides.pdf]])
- 2. A. Ben Ahmed, K. Mori, A. Ben Abdallah, [[ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6469623]], The 4th International Conference on Awareness Science and Technology ([[iCAST-2012>http://icast2012.korea.ac.kr/]]) Aug. 2012.
([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICAST2012.rar]]),
([[Slides>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/ICAST2012-slides.pdf]])
- 1. A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, [[Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5633768]]''', IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications ([[BWCCA-2010>http://www.lsi.upc.edu/~net4all/BWCCA-2010/]]), Nov. 2010. ([[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Conferences/BWCCA2010.rar]]),
([[Slides>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Akram-slides.pdf]])
***COLOR(blue){Theses and Technical Reports} [#u73fac7e]
- Akram Ben Ahmed, [[On the Design of a 3D Network-on-Chip for Many-core SoC >http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], Master's Thesis, The University of Aizu, Feb. 2012. [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
- Akram Ben Ahmed, A. Ben Abdallah, On the Design of 3D Network-on-Chip, Technical Report, Adaptive System Laboratory, School of Computer Science and Engineering, The University of Aizu, March 2012, Ref. 14AKA-TR12.
([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/m5141153_TR.pdf]])
***[[Research and Publications Schedules >Akram Ben Ahmed/coming-journal-paper-schedule]] [#t0c78e2f]
**Related References [#hfcd540b]
*** References Related to Fault Tolerant NoC [#w3159bcf]
- Please refer to the following [[page>Akram Ben Ahmed/Fault-Tolerant-NoC-References]] for more information.
***OASIS 3D-Router [#b78ed7d4]
-Verilog Source Code
--[[3D-OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
-Physical Design
--[[OASIS 3D-Router Physical Design Tutorial>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], July 2014.
-[[VLSI@ASL>http://aslweb.u-aizu.ac.jp/aslint/index.php?VLSI-Design]]
***3D/2D NoC References [#ma887ee7]
- [[Miscellaneous 3D-NoC References>http://aslweb.u-aizu.ac.jp/benlab/index.php?3D-NoC-References]]
-[[Fabrication of TSVs>http://aslweb.u-aizu.ac.jp/aslint/index.php?TSV]] [#rc8be140]
*[[Doctoral Dissertation>Akram-Thesis]] [#rc8be140]
[[Akram Ben Ahmed]]
CENTER:SIZE(50){COLOR(#990199){Thesis schedule}}
* Official thesis submission schedule from the [[University website>http://www.u-aizu.ac.jp/e-campus/e-calendar.html]] [#s814395d]
|BGCOLOR(#87CEFA):|BGCOLOR(#87CvFA):|c
|Procedure|Date|Note|
//////////////////////////////////////////////
/////////////// Preliminary Review////////////
//////////////////////////////////////////////
|Inquiry regarding thesis title and establishment of the Thesis Review Committee|Friday, July 31|SAD-> Chief Referee|
|Submission of "Report on the Determination of Doctoral Thesis Title" and "Recommendation of Candidates for a Doctoral Thesis Review Committee"|Wednesday, August 26|Student, Chief Referee-> SAD|
|GSAAC meeting (Deliberation on thesis title and establishment of Thesis Review Committee)|Wednesday, September 2|GSAAC|
|GSFA meeting (Deliberation/decision on thesis title and establishment of Thesis Review Committee)|Wednesday, September 9|GSFA|
|Inquiry regarding Preliminary Review schedule|Friday, September 25|SAD-> Chief Referee|
|Response regarding Preliminary Review schedule|Wednesday, October 7|Chief Referee-> SAD|
|GSAAC meeting (Approval of the implementation (schedule) of Preliminary Reviews)|Wednesday, October 14|GSAAC|
|GSFA meeting (Report on the implementation (schedule) of Preliminary Reviews)|Wednesday, October 21|GSFA|
|Submission of the documents for Preliminary Review|Monday, October 26|Student-> SAD|
|Preliminary Review|Tuesday, November 5-Friday, November 8||
|Submission of "Report on Results Regarding Doctoral Thesis Preliminary Review"|Monday, November 9|Thesis Review Committee->Dean|
|GSAAC meeting (Deliberation on the results from Preliminary Reviews)|Wednesday, November 11|GSAAC|
|GSFA meeting (Report on deliberation on the results from Preliminary Reviews)|Wednesday, November 18|GSFA|
|Notification of the results of deliberation|Friday, November 20|GSAAC -> Chief Referee-> Student|
//////////////////////////////////////////////
///////////////////// Final Review////////////
//////////////////////////////////////////////
|Inquiry regarding Final Review Schedule|Friday, November 20|SAD-> Chief Referee|
|Response regarding Final Review Schedule|Friday, November 27|Chief Referee-> SAD|
|GSAAC meeting (Approval of the implementation (schedule) of Final Reviews)|Friday, December 9|GSAAC|
|GSFA meeting (Report on the implementation (schedule) of Final Reviews)|Wednesday, December 16|GSFA|
|Submission of the documents for Final Review|Wednesday, January 6|Student-> SAD, Referees|
|Final Review|Tuesday, January 14- Thursday, January 16||
|Submission of "Report on Results Regarding The Final Doctoral Thesis Review"|Saturday, January 23|Thesis Review Committee->Dean|
|GSAAC meeting (Deliberation on the results from Final Review)|Friday, January 29|GSAAC|
|GSFA meeting (Report on deliberation on the results from Final Review)|Friday, February 5|GSFA|
|Notification of results of deliberation|Sunday, February 7|GSFA-> Chief Referee-> Student|
|Submission of the final thesis (including abstract) and "Application for the Academic Degree"|Wednesday, February 24|Student-> Dean, President|
|Submission of "Summary of the Doctoral Thesis Review Results"|Wednesday, February 24|Chief Referee-> Dean|
|GSAAC meeting (Deliberation on conferment of Academic Degree)|Wednesday, February 24|GSAAC|
|GSFA meeting (Authorization for conferment of Academic Degree)|Wednesday, March 2|GSFA|
|Submission of the materials for Thesis Presentation|Wednesday, March 2|Student-> SAD|
|Thesis Presentation|Tuesday, March 15||
|Degree Conferment Ceremony|Friday, March 18||
- Official detailed Schedule (tentative) can be found &ref(Doctor-schedule.pdf,,here);
----
* Graduation thesis contents [#x60vv334]
- Title: COLOR(red){High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems}
- Organization:
-- Abstract
-- Chapter 1: Introduction
-- Chapter 2: Network-on-Chip overview and Fault analysis
-- Chapter 3: Related work
-- Chapter 4: Fault-tolerant routing algorithms
-- Chapter 5: System Architecture
-- Chapter 6: Evaluation
-- Chapter 7: Conclusion & Future work
----
* Thesis Schedule [#x6024334]
|BGCOLOR(#87CEFA):|BGCOLOR(#87CEFA):|BGCOLOR(#87CEFA):|c
|Procedure|Completion deadline| Notes|
|Abstract|June 16th||
|Chapter 1: Introduction|June 23rd||
|Chapter 2: NoC overview adn Fault analysis|June 27th||
|Chapter 3: Related work|July 4th||
|Chapter 4: Routing algorithms|July 11th||
|Chapter 5: Router architecture|July 7th||
|Chapter 6: Evaluation|July 22nd||
|Chapter 7: Conclusion|July 22nd||
|Complete initial draft|July 23rd||
----
* [[Detailed thesis contents>Thesis-Content]] [#of2565e8]
----
* Thesis drafts [#of25g5e8]
** First draft: Completed on July 22, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-1st.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-1st.rar]]) [#hf15efd5]
** Second draft: Completed on October 10, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-2nd.rar]]) [#hf15eff5]
** Third draft: Completed on December 29, 2014 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-3rd.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-3rd.rar]]) [#hf15eff5]
** Fourth draft: Completed on January 7th, 2015 ([[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-4th.pdf]], [[Latex>http://aslweb.u-aizu.ac.jp/~m5141153/Thesis/Thesis-4th.rar]]) [#hf15eff5]
----
Last update: Friday, October 10, 2015.
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