3D-Matrix Processor
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開始行:
[[Mitsuhiro Nakamura]]
CENTER:SIZE(60){COLOR(#990199){Design and Evaluation of 3D-OASIS-NoC Matrix Processor}}
*Background [#nec7d6fe]
During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://aslweb.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
*Research goal[#mec7d6fe]
Design and Evaluation of 3D-OASIS-NoC Matrix Processor.
*3D-OASIS-NoC Router Design & Simulation Workflow [#e7dd9de5]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,100%);
CENTER:COLOR(green){Fig. 2 3D-OASIS-NoC Router Design & Simulation Workflow}
*References[#jec7d6fe]
**Papers, Theses [#ka39bd91]
-1. Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture'', '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6354695]]]
-2. [[OASIS-NoC Benchmark suite>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]], April 2013.
-3. [[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
-4. [[OASIS 3D-Router Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], Tutorial, July 5, 2014.
-5. R. Okada, A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC [[Thesis>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011.pdf]], [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011-slides.pdf]], [[Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]], [[Webpage>Ryuya Okada]]
-6 A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu.
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-7. [[About TSV: Physical design of a 3D router: reducing the number of vertical connections and enabling asynchronous Operation>https://drive.google.com/file/d/0B2HMlO4p7SuwaFV4cHp4VVdCTVE/view?usp=sharing]]
*Schedule [#zb13610d]
-1st: What application
-2nd: How to design 3D-chip
-3rd: Study OASIS 3D router
-4th: Integrate everything
*Links [#l24b8b6b]
-[[OASIS Project>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]]
-[[VLSI@ASL>http://aslweb.u-aizu.ac.jp/wiki/index.php?VLSI%40ASL]]
終了行:
[[Mitsuhiro Nakamura]]
CENTER:SIZE(60){COLOR(#990199){Design and Evaluation of 3D-OASIS-NoC Matrix Processor}}
*Background [#nec7d6fe]
During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://aslweb.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
*Research goal[#mec7d6fe]
Design and Evaluation of 3D-OASIS-NoC Matrix Processor.
*3D-OASIS-NoC Router Design & Simulation Workflow [#e7dd9de5]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,100%);
CENTER:COLOR(green){Fig. 2 3D-OASIS-NoC Router Design & Simulation Workflow}
*References[#jec7d6fe]
**Papers, Theses [#ka39bd91]
-1. Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture'', '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6354695]]]
-2. [[OASIS-NoC Benchmark suite>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]], April 2013.
-3. [[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]]
-4. [[OASIS 3D-Router Physical Design>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf]], Tutorial, July 5, 2014.
-5. R. Okada, A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC [[Thesis>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011.pdf]], [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011-slides.pdf]], [[Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]], [[Webpage>Ryuya Okada]]
-6 A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu.
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]
-7. [[About TSV: Physical design of a 3D router: reducing the number of vertical connections and enabling asynchronous Operation>https://drive.google.com/file/d/0B2HMlO4p7SuwaFV4cHp4VVdCTVE/view?usp=sharing]]
*Schedule [#zb13610d]
-1st: What application
-2nd: How to design 3D-chip
-3rd: Study OASIS 3D router
-4th: Integrate everything
*Links [#l24b8b6b]
-[[OASIS Project>http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS]]
-[[VLSI@ASL>http://aslweb.u-aizu.ac.jp/wiki/index.php?VLSI%40ASL]]
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