猪狩/日誌/2010-08-16
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開始行:
[[猪狩/日誌]]&br;&br;
3泊4日郡山の旅
***研究 [#b356371b]
-動的再構成命令の設計
--PR Controller Register Descriptions
|Register Name|Base Address + Offset (hex)|Access|
|Software Reset Register (RST)|C_BASEADDR + 0|Write|
|PRM Control Register (PRMCR)|C_BASEADDR + 4|R/W|
|Source Register (SR)|C_BASEADDR + 8|R/W|
|Length (LENGTH)|C_BASEADDR + C|R/W|
|PRM Status Register (PRMSR)|C_BASEADDR + 10|Read|
|PRM Type Register (PRMTR)|C_BASEADDR + 14|Read|
|Interrupt Status Register (ISR)|C_BASEADDR + 18|R/TOW|
|Interrupt Enable Register (IER)|C_BASEADDR + 1C|R/W|
---Software Reset Register (RST)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|RST|Write|N/A|Software Reset&br;A write of 0x0000000A causes reset of the XPS Central PRM Controller. A write of any other value has undefined effect and returns a bus error. A read of this register returns zero.|
---PRM Control Register (PRMCR)
|Bits|Name|Core Access|Reset Value|Description|
|0|SINC|R/W|’1’|Source Increment: Increment the source address by the number of source bytes read.&br;’1’ = Increment the source address.&br;’0’ = Do not increment the source address. SINC = ’0’ is allowed if and only if the Source Address register is written with a keyhole address.|
|1-31||||Reserved|
---Source Register (SR)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|SR|Write|N/A|Source Address: Source address for the current PRM operation. When SINC = ’1’, as data is moved from the source address, this register updates to track the current source address. When SINC = ’0’, the source address remains constant at the programmed value. (See also the SINC field of the PRM Control Register).|
---Length (LENGTH)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|LENGTH|R/W|0|Length of the DMA Transfer for PRM: The DMA operation starts when the number of bytes to be transferred from source to destination is written to the Length Register. Therefore, this register is written only after the DMA Control register, the Source Address and the Destination Address registers have been written with their desired values and any other setup is complete. As bytes are successfully written to the destination, the Length Register decrements to reflect the number of bytes remaining to be transferred. The Length Register will be zero after a successful DMA operation.|
---PRM Status Register (PRMSR)
|Bits|Name|Core Access|Reset Value|Description|
|0|RECONF|Read|'0'|PRM Reconfigure:&br;'0' = Reconfiguring operation is not in progress.&br;'1' = Reconfiguring operation is in progress.|
|1|PRMBSY|Read|'0'|PRM Busy:&br;'0' = PRM is not busy.&br;'1' = PRM is busy.|
|2|PRMEN|Read|'0'|PRM Enable:&br;'0' = PRM is not enable.&br;'1' = PRM is enable.|
|3-31||||Reserved|
---PRM Type Register (PRMTR)
|Bits|Name|Core Access|Reset Value|Description|
|0|PRM0|Read|'0'|'0' = PRM0 is not implemented.&br;'1' = PRM0 is implemented.|
|1|PRM1|Read|'0'|'0' = PRM1 is not implemented.&br;'1' = PRM1 is implemented.|
|2-31||||Reserved|
---Interrupt Status Register (ISR)
|Bits|Name|Core Access|Reset Value|Description|
|0-29||||Reserved|
|30|PRMER|R/TOW|'0'|PRM Error:&br;'0' = No PRM error.&br;'1' = PRM error.|
|31|RD|R/TOW|'0'|Reconfig Done:&br;'0' = Reconfiguring operation is not done.&br;'1' = Reconfiguring operation is done.|
---Interrupt Enable Register (IER)
|Bits|Name|Core Access|Reset Value|Description|
||||||
***コメント [#p6fcd5ff]
#comment
終了行:
[[猪狩/日誌]]&br;&br;
3泊4日郡山の旅
***研究 [#b356371b]
-動的再構成命令の設計
--PR Controller Register Descriptions
|Register Name|Base Address + Offset (hex)|Access|
|Software Reset Register (RST)|C_BASEADDR + 0|Write|
|PRM Control Register (PRMCR)|C_BASEADDR + 4|R/W|
|Source Register (SR)|C_BASEADDR + 8|R/W|
|Length (LENGTH)|C_BASEADDR + C|R/W|
|PRM Status Register (PRMSR)|C_BASEADDR + 10|Read|
|PRM Type Register (PRMTR)|C_BASEADDR + 14|Read|
|Interrupt Status Register (ISR)|C_BASEADDR + 18|R/TOW|
|Interrupt Enable Register (IER)|C_BASEADDR + 1C|R/W|
---Software Reset Register (RST)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|RST|Write|N/A|Software Reset&br;A write of 0x0000000A causes reset of the XPS Central PRM Controller. A write of any other value has undefined effect and returns a bus error. A read of this register returns zero.|
---PRM Control Register (PRMCR)
|Bits|Name|Core Access|Reset Value|Description|
|0|SINC|R/W|’1’|Source Increment: Increment the source address by the number of source bytes read.&br;’1’ = Increment the source address.&br;’0’ = Do not increment the source address. SINC = ’0’ is allowed if and only if the Source Address register is written with a keyhole address.|
|1-31||||Reserved|
---Source Register (SR)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|SR|Write|N/A|Source Address: Source address for the current PRM operation. When SINC = ’1’, as data is moved from the source address, this register updates to track the current source address. When SINC = ’0’, the source address remains constant at the programmed value. (See also the SINC field of the PRM Control Register).|
---Length (LENGTH)
|Bits|Name|Core Access|Reset Value|Description|
|0-31|LENGTH|R/W|0|Length of the DMA Transfer for PRM: The DMA operation starts when the number of bytes to be transferred from source to destination is written to the Length Register. Therefore, this register is written only after the DMA Control register, the Source Address and the Destination Address registers have been written with their desired values and any other setup is complete. As bytes are successfully written to the destination, the Length Register decrements to reflect the number of bytes remaining to be transferred. The Length Register will be zero after a successful DMA operation.|
---PRM Status Register (PRMSR)
|Bits|Name|Core Access|Reset Value|Description|
|0|RECONF|Read|'0'|PRM Reconfigure:&br;'0' = Reconfiguring operation is not in progress.&br;'1' = Reconfiguring operation is in progress.|
|1|PRMBSY|Read|'0'|PRM Busy:&br;'0' = PRM is not busy.&br;'1' = PRM is busy.|
|2|PRMEN|Read|'0'|PRM Enable:&br;'0' = PRM is not enable.&br;'1' = PRM is enable.|
|3-31||||Reserved|
---PRM Type Register (PRMTR)
|Bits|Name|Core Access|Reset Value|Description|
|0|PRM0|Read|'0'|'0' = PRM0 is not implemented.&br;'1' = PRM0 is implemented.|
|1|PRM1|Read|'0'|'0' = PRM1 is not implemented.&br;'1' = PRM1 is implemented.|
|2-31||||Reserved|
---Interrupt Status Register (ISR)
|Bits|Name|Core Access|Reset Value|Description|
|0-29||||Reserved|
|30|PRMER|R/TOW|'0'|PRM Error:&br;'0' = No PRM error.&br;'1' = PRM error.|
|31|RD|R/TOW|'0'|Reconfig Done:&br;'0' = Reconfiguring operation is not done.&br;'1' = Reconfiguring operation is done.|
---Interrupt Enable Register (IER)
|Bits|Name|Core Access|Reset Value|Description|
||||||
***コメント [#p6fcd5ff]
#comment
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