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開始行:
[[大堀/研究/データ]]
[[大堀/研究/データ/論文-ZERODRAFT]]
//研究室限定
*Thesis - ZERO DRAFT [#n0fe4021]
-箇条書き
-意味の重複が存在
-文型が統一されていない
という問題はあるが、まずは、どんな内容を書くかということだけまとめ。
**Introduction [#x0f7ecb9]
In my work, acceleration of real-time image processing using FPGA is proposed.
For example physics engines and super computers are used for scientific calculation, physical calculation.
My research presents to use physics engines efficiently for image processing by considering calculation in pixel level to particle methods.
The system is based on PROGRAPE-4 under a pipeline approach to achieve acceleration of process.
PROGRAPE-4 uses to theoretical astronomy, molecular dynamics, fluid dynamics.
My design is coded in PGDL that permits to model a system without specific hardware.
**Literature Review [#ne159ddb]
Physics engines or super computers are able to calculate and simulate the problems of astronomy, molecular dynamics, fluid dynamics.
The problems need to calculate the interparticle interaction whose complexity is O(N~2).
Those hardwares accept those complexity within a range of practical use.
Throughout history, many scientific calculations have been calculated on those hardwares.
Though, those hardwares are used little other than scientific calculation.
Therefore, my research presents real-time image processing using physics engines.
With considering a pixel as a particle, the architecture processing image is presented.
This paper focuses on that those hardwares are often calculate interparticle interaction.
**Methodology [#b265d8f2]
According to some thesis, critical path of image processing is a part of obtaining a pixel value from several pixel values.
Image processing software is coded in C.
Image processing hardware is coded in PGDL.
The architecture is implemented on PROGRAPE-4.
- There are five FPGAs on PROGRAPE-4.
- One of them is for connection control, the others are for calculation.
SuSE Linux 9.3 (x86-64) is used as the system development environment.
Using PGDL makes circuit Designs be possible to implement on other FPGA board.
It is important in part of compatibility.
-Procedure
1. Coding a image processing software in C.
2. Finding the critical path by verifying.
3. Coding the logic circuit in PGDL.
4. Converting PGDL to VHDL(one of Hardware Description Languages). (automatically)
5. Making the logic design by logic synthesis. (automatically)
6. Configuring the logic design to PROGRAPE-4.
7. Checking whether the process by the system is correct or not.
8. If the process is not correct, returning to step.3
9. If the process is correct, there is a acceleration system of the image processing.
10. (advanced) Building onto real-time processing application.(for example Effectv)
**Results [#f702b269]
A accelerated system of the image processing is presented.
The architecture is reconfigurable.
The feature of the architecture is pallarel processing.
Changing logic design is easy by PGDL. (For example, number of pipelines)
Therefore, my several designs of image processing are able to be compared with the performance.
The comparing is shown in this thesis.(Using figure)
The image processing on physics engines or super computers are possible with considering the pixel values as particles.
**Conclusion [#mab07034]
The better performance of the physics engines or super computers is created, the better performance of the image processing is presented.
In this research, image processing as the one way of using physics engines or super computers is proposed.
Under considering to implement on the future hardwares easily, the paper is proposed the architecture.
They will be important to accelerate the image processing.
**Reference [#p5b1f72d]
- Real-Time FPGA Based Architecture for Bicubic Interpolation An Application for Digital Image Scaling
- An Execution Environment for Image Processing using
終了行:
[[大堀/研究/データ]]
[[大堀/研究/データ/論文-ZERODRAFT]]
//研究室限定
*Thesis - ZERO DRAFT [#n0fe4021]
-箇条書き
-意味の重複が存在
-文型が統一されていない
という問題はあるが、まずは、どんな内容を書くかということだけまとめ。
**Introduction [#x0f7ecb9]
In my work, acceleration of real-time image processing using FPGA is proposed.
For example physics engines and super computers are used for scientific calculation, physical calculation.
My research presents to use physics engines efficiently for image processing by considering calculation in pixel level to particle methods.
The system is based on PROGRAPE-4 under a pipeline approach to achieve acceleration of process.
PROGRAPE-4 uses to theoretical astronomy, molecular dynamics, fluid dynamics.
My design is coded in PGDL that permits to model a system without specific hardware.
**Literature Review [#ne159ddb]
Physics engines or super computers are able to calculate and simulate the problems of astronomy, molecular dynamics, fluid dynamics.
The problems need to calculate the interparticle interaction whose complexity is O(N~2).
Those hardwares accept those complexity within a range of practical use.
Throughout history, many scientific calculations have been calculated on those hardwares.
Though, those hardwares are used little other than scientific calculation.
Therefore, my research presents real-time image processing using physics engines.
With considering a pixel as a particle, the architecture processing image is presented.
This paper focuses on that those hardwares are often calculate interparticle interaction.
**Methodology [#b265d8f2]
According to some thesis, critical path of image processing is a part of obtaining a pixel value from several pixel values.
Image processing software is coded in C.
Image processing hardware is coded in PGDL.
The architecture is implemented on PROGRAPE-4.
- There are five FPGAs on PROGRAPE-4.
- One of them is for connection control, the others are for calculation.
SuSE Linux 9.3 (x86-64) is used as the system development environment.
Using PGDL makes circuit Designs be possible to implement on other FPGA board.
It is important in part of compatibility.
-Procedure
1. Coding a image processing software in C.
2. Finding the critical path by verifying.
3. Coding the logic circuit in PGDL.
4. Converting PGDL to VHDL(one of Hardware Description Languages). (automatically)
5. Making the logic design by logic synthesis. (automatically)
6. Configuring the logic design to PROGRAPE-4.
7. Checking whether the process by the system is correct or not.
8. If the process is not correct, returning to step.3
9. If the process is correct, there is a acceleration system of the image processing.
10. (advanced) Building onto real-time processing application.(for example Effectv)
**Results [#f702b269]
A accelerated system of the image processing is presented.
The architecture is reconfigurable.
The feature of the architecture is pallarel processing.
Changing logic design is easy by PGDL. (For example, number of pipelines)
Therefore, my several designs of image processing are able to be compared with the performance.
The comparing is shown in this thesis.(Using figure)
The image processing on physics engines or super computers are possible with considering the pixel values as particles.
**Conclusion [#mab07034]
The better performance of the physics engines or super computers is created, the better performance of the image processing is presented.
In this research, image processing as the one way of using physics engines or super computers is proposed.
Under considering to implement on the future hardwares easily, the paper is proposed the architecture.
They will be important to accelerate the image processing.
**Reference [#p5b1f72d]
- Real-Time FPGA Based Architecture for Bicubic Interpolation An Application for Digital Image Scaling
- An Execution Environment for Image Processing using
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