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開始行:
[[増田]]
#contents
*Registers in MIPS [#e6ebe78b]
総レジスタ数:176~
レジスタ内分け~
0〜31:General Purpose Register~
32〜63:Floating Point Register~
64〜65:Multiply/divide Register~
67〜74:Status Register~
残り:CoProcessor0,2,3~
~
*Register Class in MIPS [#z603385e]
|~Class|~Meaning|
|NO_REGS|no registers in set|
|M16_NA_REGS|mips16 regs not used to pass args|
|M16_REGS|mips16 directly accessible registers|
|T_REG|mips16 T register($24)|
|M16_R_REGS|mips16 registers plus T register|
|PIC_FN_ADDR_REG|SVR4 PIC function address register|
|LEA_REGS|Every GPR except $25|
|GR_REGS|integer registers|
|FP_REGS|floating point registers|
|HI_REGS|hi register|
|LO_REGS|lo register|
|MD_REGS|multiply/divide registers (hi/lo)|
|COP0_REGS, COP2_REGS, COP3_REGS|gegeneric coprocessor classes|
|HI_AND_GR_REGS, LO_AND_GR_REGS, HI_AND_FP_REGS|union classes|
|ST_REGS|status registers|
|ALL_REGS|all registers|
|LIM_REG_CLASSES|max value + 1|
*define文 [#uaefd1f3]
|MASK_INT64|0x00000001|ints are 64 bits|
|MASK_LONG64|0x00000002|longs are 64 bits|
|MASK_SPLIT_ADDR|0x00000004|Address splitting is enabled|
|MASK_NO_FUSED_MADD|0x0000008|Don't generate floating point multiply-add operations|
|MASK_EXPLICIT_RELOCS|0x00000010|Use relocation operators|
|MASK_MEMCPY|0x00000020|call memcpy instead of inline code|
|MASK_SOFT_FLOAT|0x00000040|software floating point|
|MASK_FLOAT64|0x00000080|fp registers are 64 bits|
|MASK_ABICALLS|0x00000100|emit .abicalls/.cprestore/.cpload|
|MASK_XGOT|0x00000200|emit big-got PIC|
|MASK_LONG_CALLS|0x00000400|Always call through a register|
|MASK_64BIT|0x00000800|Use 64 bit GP registers and insns|
|MASK_EMBEDDED_DATA|0x00001000|Reduce RAM usage, not fast code|
|MASK_BIG_ENDIAN|0x00002000|Generate big endian code|
|MASK_SINGLE_FLOAT|0x00004000|Only single precision FPU|
|MASK_MAD|0x00008000|Generate mad/madu as on 4650|
|MASK_4300_MUL_FIX|0x00010000|Work-around early vr.4300 CPU bug|
|MASK_MIPS16|0x00020000|Generate mips16 code|
|MASK_NO_CHECK_ZERO_DIV|0x00040000|divide by zero checking|
|MASK_BRANCHLIKELY|0x00080000|Generate Branch Likely instructions|
|MASK_UNINIT_CONST_IN_RODATA|0x00100000|Store uninitialized consts in rodata|
|MASK_FIX_R4000|0x00200000|Work around R4000 errata|
|MASK_FIX_R4400|0x00400000|Work around R4400 errata|
|MASK_FIX_SB1|0x00800000|Work around SB-1 errata|
|MASK_FIX_VR4120|0x01000000|Work around VR4120 errata|
|MASK_VR4130_ALIGN|0x02000000|Perform VR4130 alignment opts|
|MASK_FP_EXCEPTIONS|0x04000000|FP exceptions are enabled|
|MASK_DIVIDE_BREAKS|0x08000000|Divide by zero check uses break instead of trap|
|MASK_PAIRED_SINGLE|0x10000000|Support paired-single FPU|
|MASK_MIPS3D|0x20000000|Support MIPS-3D instructions|
|MASK_SYM32|0x40000000|Assume 32-bit symbol values|
|MASK_DEBUG|0|unused|
|MASK_DEBUG_D|0|don't do define_split's|
|MASK_MIPS_TFILE|0|flag for mips-tfile usage|
終了行:
[[増田]]
#contents
*Registers in MIPS [#e6ebe78b]
総レジスタ数:176~
レジスタ内分け~
0〜31:General Purpose Register~
32〜63:Floating Point Register~
64〜65:Multiply/divide Register~
67〜74:Status Register~
残り:CoProcessor0,2,3~
~
*Register Class in MIPS [#z603385e]
|~Class|~Meaning|
|NO_REGS|no registers in set|
|M16_NA_REGS|mips16 regs not used to pass args|
|M16_REGS|mips16 directly accessible registers|
|T_REG|mips16 T register($24)|
|M16_R_REGS|mips16 registers plus T register|
|PIC_FN_ADDR_REG|SVR4 PIC function address register|
|LEA_REGS|Every GPR except $25|
|GR_REGS|integer registers|
|FP_REGS|floating point registers|
|HI_REGS|hi register|
|LO_REGS|lo register|
|MD_REGS|multiply/divide registers (hi/lo)|
|COP0_REGS, COP2_REGS, COP3_REGS|gegeneric coprocessor classes|
|HI_AND_GR_REGS, LO_AND_GR_REGS, HI_AND_FP_REGS|union classes|
|ST_REGS|status registers|
|ALL_REGS|all registers|
|LIM_REG_CLASSES|max value + 1|
*define文 [#uaefd1f3]
|MASK_INT64|0x00000001|ints are 64 bits|
|MASK_LONG64|0x00000002|longs are 64 bits|
|MASK_SPLIT_ADDR|0x00000004|Address splitting is enabled|
|MASK_NO_FUSED_MADD|0x0000008|Don't generate floating point multiply-add operations|
|MASK_EXPLICIT_RELOCS|0x00000010|Use relocation operators|
|MASK_MEMCPY|0x00000020|call memcpy instead of inline code|
|MASK_SOFT_FLOAT|0x00000040|software floating point|
|MASK_FLOAT64|0x00000080|fp registers are 64 bits|
|MASK_ABICALLS|0x00000100|emit .abicalls/.cprestore/.cpload|
|MASK_XGOT|0x00000200|emit big-got PIC|
|MASK_LONG_CALLS|0x00000400|Always call through a register|
|MASK_64BIT|0x00000800|Use 64 bit GP registers and insns|
|MASK_EMBEDDED_DATA|0x00001000|Reduce RAM usage, not fast code|
|MASK_BIG_ENDIAN|0x00002000|Generate big endian code|
|MASK_SINGLE_FLOAT|0x00004000|Only single precision FPU|
|MASK_MAD|0x00008000|Generate mad/madu as on 4650|
|MASK_4300_MUL_FIX|0x00010000|Work-around early vr.4300 CPU bug|
|MASK_MIPS16|0x00020000|Generate mips16 code|
|MASK_NO_CHECK_ZERO_DIV|0x00040000|divide by zero checking|
|MASK_BRANCHLIKELY|0x00080000|Generate Branch Likely instructions|
|MASK_UNINIT_CONST_IN_RODATA|0x00100000|Store uninitialized consts in rodata|
|MASK_FIX_R4000|0x00200000|Work around R4000 errata|
|MASK_FIX_R4400|0x00400000|Work around R4400 errata|
|MASK_FIX_SB1|0x00800000|Work around SB-1 errata|
|MASK_FIX_VR4120|0x01000000|Work around VR4120 errata|
|MASK_VR4130_ALIGN|0x02000000|Perform VR4130 alignment opts|
|MASK_FP_EXCEPTIONS|0x04000000|FP exceptions are enabled|
|MASK_DIVIDE_BREAKS|0x08000000|Divide by zero check uses break instead of trap|
|MASK_PAIRED_SINGLE|0x10000000|Support paired-single FPU|
|MASK_MIPS3D|0x20000000|Support MIPS-3D instructions|
|MASK_SYM32|0x40000000|Assume 32-bit symbol values|
|MASK_DEBUG|0|unused|
|MASK_DEBUG_D|0|don't do define_split's|
|MASK_MIPS_TFILE|0|flag for mips-tfile usage|
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