西牧/春のプロジェクト2010/第6回
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開始行:
[[西牧/春のプロジェクト2010]]
-stack.v
module stack(ck,reset,load,push,pop,d,qtop,qnext);
input ck,reset,load,push,pop;
input [15:0] d;
output [15:0] qtop,qnext;
reg [15:0] q[3:0];
assign qtop = q[0];
assign qnext = q[1];
always @(posedge ck or negedge reset) begin
if (reset == 0)
begin
q[0] <= 0;
q[1] <= 0;
q[2] <= 0;
q[3] <= 0;
end
else if(load == 1)
q[0] <= d;
else if(pop == 1)
begin
q[0] <= q[1];
q[1] <= q[2];
q[2] <= q[3];
end
else if(push == 1)
begin
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
end
end // always @ (posedge ck or negedge reset)
endmodule // stack
-stack2.v
module stack2(ck,reset,load,push,pop,d,qtop,qnext);
parameter N = 8;
input ck,reset,load,push,pop;
input [15:0] d;
output [15:0] qtop,qnext;
reg [15:0] q[N-1:0];
assign qtop = q[0];
assign qnext = q[1];
integer i;
always @(posedge ck or negedge reset) begin
if (reset == 0)
for(i = 0; i < N;i=i+1)
q[i] <= 0;
else if(load == 1)
q[0] <= d;
else if(pop == 1)
for(i = 0; i < N - 1;i=i+1)
q[i] <= q[i+1];
else if(push == 1)
for(i = 0; i < N - 1;i=i+1)
q[i+1] <= q[i];
end // always @ (posedge ck or negedge reset)
endmodule // stack
-opstack.v
`include "alu.v"
`include "stack2.v"
module opstack(ck,reset,num,op,x);
input ck,reset,num,op;
input [15:0] x;
wire [15:0] qtop,qnext,aluout;
wire load,push,pop;
reg [15:0] stackin;
alu alu0(qtop,qnext,x[4:0],aluout);
stack2 stack0(ck,reset,load,push,pop,stackin,qtop,qnext);
assign load = num | op;
assign push = num;
assign pop = op & !x[4];
always @(num or op or x or aluout)
if(num) stackin = x;
else if(op) stackin = aluout;
else stackin = 16'hxxxx;
endmodule // opstack
-opstack_tb.v
`timescale 1ns /1ps
`include "opstack.v"
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define NOT 5'b10001
`define BNOT 5'b10010
module opstack_tb;
reg ck,reset,num,op;
reg [15:0] x;
opstack opstack0(ck,reset,num,op,x);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
$dumpfile("opstack_tb.vcd");
$dumpvars(0,opstack_tb);
reset = 0;
num = 0;
op =0;
x =0;
#100;
reset = 1;
num = 1;
op = 0;
x = 2;
#100;
num = 1;
op = 0;
x = 3;
#100;
num = 1;
op = 0;
x = 4;
#100;
num = 0;
op = 1;
x = `MUL;
#100;
num = 0;
op = 1;
x = `ADD;
#100;
num = 0;
op = 1;
x = `NEG;
#100;
num = 1;
op = 0;
x = 5;
#100;
num = 0;
op = 1;
x = `LT;
#100;
num = 1;
op = 0;
x = 6;
#100;
num = 1;
op = 0;
x = 7;
#100;
num = 0;
op = 1;
x = `GT;
#100;
num = 0;
op = 1;
x = `OR;
#100;
num = 0;
op = 0;
x = 0;
#100;
$finish;
end // initial begin
initial $monitor("ck=%d reset=%d num=%d op=%d x=%d",ck,reset,num,op,x);
endmodule // opstack_tb
終了行:
[[西牧/春のプロジェクト2010]]
-stack.v
module stack(ck,reset,load,push,pop,d,qtop,qnext);
input ck,reset,load,push,pop;
input [15:0] d;
output [15:0] qtop,qnext;
reg [15:0] q[3:0];
assign qtop = q[0];
assign qnext = q[1];
always @(posedge ck or negedge reset) begin
if (reset == 0)
begin
q[0] <= 0;
q[1] <= 0;
q[2] <= 0;
q[3] <= 0;
end
else if(load == 1)
q[0] <= d;
else if(pop == 1)
begin
q[0] <= q[1];
q[1] <= q[2];
q[2] <= q[3];
end
else if(push == 1)
begin
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
end
end // always @ (posedge ck or negedge reset)
endmodule // stack
-stack2.v
module stack2(ck,reset,load,push,pop,d,qtop,qnext);
parameter N = 8;
input ck,reset,load,push,pop;
input [15:0] d;
output [15:0] qtop,qnext;
reg [15:0] q[N-1:0];
assign qtop = q[0];
assign qnext = q[1];
integer i;
always @(posedge ck or negedge reset) begin
if (reset == 0)
for(i = 0; i < N;i=i+1)
q[i] <= 0;
else if(load == 1)
q[0] <= d;
else if(pop == 1)
for(i = 0; i < N - 1;i=i+1)
q[i] <= q[i+1];
else if(push == 1)
for(i = 0; i < N - 1;i=i+1)
q[i+1] <= q[i];
end // always @ (posedge ck or negedge reset)
endmodule // stack
-opstack.v
`include "alu.v"
`include "stack2.v"
module opstack(ck,reset,num,op,x);
input ck,reset,num,op;
input [15:0] x;
wire [15:0] qtop,qnext,aluout;
wire load,push,pop;
reg [15:0] stackin;
alu alu0(qtop,qnext,x[4:0],aluout);
stack2 stack0(ck,reset,load,push,pop,stackin,qtop,qnext);
assign load = num | op;
assign push = num;
assign pop = op & !x[4];
always @(num or op or x or aluout)
if(num) stackin = x;
else if(op) stackin = aluout;
else stackin = 16'hxxxx;
endmodule // opstack
-opstack_tb.v
`timescale 1ns /1ps
`include "opstack.v"
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define NOT 5'b10001
`define BNOT 5'b10010
module opstack_tb;
reg ck,reset,num,op;
reg [15:0] x;
opstack opstack0(ck,reset,num,op,x);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
$dumpfile("opstack_tb.vcd");
$dumpvars(0,opstack_tb);
reset = 0;
num = 0;
op =0;
x =0;
#100;
reset = 1;
num = 1;
op = 0;
x = 2;
#100;
num = 1;
op = 0;
x = 3;
#100;
num = 1;
op = 0;
x = 4;
#100;
num = 0;
op = 1;
x = `MUL;
#100;
num = 0;
op = 1;
x = `ADD;
#100;
num = 0;
op = 1;
x = `NEG;
#100;
num = 1;
op = 0;
x = 5;
#100;
num = 0;
op = 1;
x = `LT;
#100;
num = 1;
op = 0;
x = 6;
#100;
num = 1;
op = 0;
x = 7;
#100;
num = 0;
op = 1;
x = `GT;
#100;
num = 0;
op = 1;
x = `OR;
#100;
num = 0;
op = 0;
x = 0;
#100;
$finish;
end // initial begin
initial $monitor("ck=%d reset=%d num=%d op=%d x=%d",ck,reset,num,op,x);
endmodule // opstack_tb
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