西牧/春のプロジェクト2010/第5回
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開始行:
[[西牧/春のプロジェクト2010]]
-state.v
`define IDLE 3'b000
`define FETCHA 3'b001
`define FETCHB 3'b010
`define EXECA 3'b011
`define EXECB 3'b100
module state(ck,reset,run,cont,halt,cs);
input ck,reset,run,cont,halt;
output [2:0] cs;
reg [2:0] cs;
always @(posedge ck or negedge reset) begin
if (!reset) cs <= `IDLE;
else
case(cs)
`IDLE: if (run != 1)
cs <= `FETCHA;
`FETCHA: cs <= `FETCHB;
`FETCHB: cs <= `EXECA;
`EXECA:
begin
if (halt == 1) cs <= `IDLE;
else if (cont == 1) cs <= `EXECB;
else cs <= `EXECB;
end
`EXECB: cs <= `FETCHA;
default: cs <= 3'bxxx;
endcase // case (cs)
end // always @ (posedge ck or negedge reset)
endmodule // state
-state_tb.v
`timescale 1ns/1ps
`include "state.v"
module state_tb;
reg ck,reset,run,cont,halt;
wire [2:0] cs;
state state(ck,reset,run,cont,halt,cs);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
$dumpfile("state_tb.vcd");
$dumpvars(0,state_tb);
reset = 0;
run = 0;
halt =0;
cont =0;
#100
reset = 1;
run = 1;
#100
run = 0;
#200
cont = 1;
#100
cont = 0;
#600
halt = 1;
#100
halt = 0;
$finish;
end // initial begin
initial $monitor("ck=%b reset=%b run=%b cont=%b halt=%b cs=%b",ck,reset,run,cont,halt,cs);
endmodule
終了行:
[[西牧/春のプロジェクト2010]]
-state.v
`define IDLE 3'b000
`define FETCHA 3'b001
`define FETCHB 3'b010
`define EXECA 3'b011
`define EXECB 3'b100
module state(ck,reset,run,cont,halt,cs);
input ck,reset,run,cont,halt;
output [2:0] cs;
reg [2:0] cs;
always @(posedge ck or negedge reset) begin
if (!reset) cs <= `IDLE;
else
case(cs)
`IDLE: if (run != 1)
cs <= `FETCHA;
`FETCHA: cs <= `FETCHB;
`FETCHB: cs <= `EXECA;
`EXECA:
begin
if (halt == 1) cs <= `IDLE;
else if (cont == 1) cs <= `EXECB;
else cs <= `EXECB;
end
`EXECB: cs <= `FETCHA;
default: cs <= 3'bxxx;
endcase // case (cs)
end // always @ (posedge ck or negedge reset)
endmodule // state
-state_tb.v
`timescale 1ns/1ps
`include "state.v"
module state_tb;
reg ck,reset,run,cont,halt;
wire [2:0] cs;
state state(ck,reset,run,cont,halt,cs);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
$dumpfile("state_tb.vcd");
$dumpvars(0,state_tb);
reset = 0;
run = 0;
halt =0;
cont =0;
#100
reset = 1;
run = 1;
#100
run = 0;
#200
cont = 1;
#100
cont = 0;
#600
halt = 1;
#100
halt = 0;
$finish;
end // initial begin
initial $monitor("ck=%b reset=%b run=%b cont=%b halt=%b cs=%b",ck,reset,run,cont,halt,cs);
endmodule
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