西牧/春のプロジェクト2010/第4回
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開始行:
[[西牧/春のプロジェクト2010]]
-counter.v
module counter(ck,reset,load,inc,d,q);
parameter N=16;
input ck,reset,inc,load;
input [N-1:0] d;
output [N-1:0] q;
reg [N-1:0] q;
always @(posedge ck or negedge reset) begin
if (!reset)
q <= 0;
else if(load)
q <= d;
else if(inc)
q<=q+1;
end
endmodule // counter
-counter2.v
`include "ff.v"
module counter2(ck,reset,load,inc,d,q);
input ck,reset,load,inc;
input [1:0] d;
output [1:0] q;
reg [1:0] q;
wire d0,d1;
ff ff0(ck,reset,d0,q[0]);
ff ff1(ck,reset,d1,q[1]);
assign d0 = (~load & ~inc & q[0]) | (load & d[0]) | (inc & ~q[0]);
assign d1 = (~load & ~inc & q[1]) |(load & d[1])|( inc & (q[0]^q[1]));
endmodule // counter2
-counter_tb.v
`timescale 1ns/1ps
`include "counter.v"
module counter_tb;
reg ck,reset,load,inc;
reg [15:0] d;
wire [15:0] q;
counter counter(ck,reset,load,inc,d,q);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
reset=0;
load =0;
inc=0;
d=16'h0000;
#100
reset =1;
#100 inc =1;
#300 inc = 0;
load =1;
d=16'h1234;
#100
inc =1;
load = 0;
d=16'h0000;
#500
reset = 0;
$finish;
end // initial begin
initial $monitor("ck=%b reset=%b load=%b inc=%b d=%b q=%b",ck,reset,load,inc,d,q);
endmodule // counter_tb
終了行:
[[西牧/春のプロジェクト2010]]
-counter.v
module counter(ck,reset,load,inc,d,q);
parameter N=16;
input ck,reset,inc,load;
input [N-1:0] d;
output [N-1:0] q;
reg [N-1:0] q;
always @(posedge ck or negedge reset) begin
if (!reset)
q <= 0;
else if(load)
q <= d;
else if(inc)
q<=q+1;
end
endmodule // counter
-counter2.v
`include "ff.v"
module counter2(ck,reset,load,inc,d,q);
input ck,reset,load,inc;
input [1:0] d;
output [1:0] q;
reg [1:0] q;
wire d0,d1;
ff ff0(ck,reset,d0,q[0]);
ff ff1(ck,reset,d1,q[1]);
assign d0 = (~load & ~inc & q[0]) | (load & d[0]) | (inc & ~q[0]);
assign d1 = (~load & ~inc & q[1]) |(load & d[1])|( inc & (q[0]^q[1]));
endmodule // counter2
-counter_tb.v
`timescale 1ns/1ps
`include "counter.v"
module counter_tb;
reg ck,reset,load,inc;
reg [15:0] d;
wire [15:0] q;
counter counter(ck,reset,load,inc,d,q);
initial begin
ck = 0;
forever
#50 ck = ~ck;
end
initial begin
reset=0;
load =0;
inc=0;
d=16'h0000;
#100
reset =1;
#100 inc =1;
#300 inc = 0;
load =1;
d=16'h1234;
#100
inc =1;
load = 0;
d=16'h0000;
#500
reset = 0;
$finish;
end // initial begin
initial $monitor("ck=%b reset=%b load=%b inc=%b d=%b q=%b",ck,reset,load,inc,d,q);
endmodule // counter_tb
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