西牧/春のプロジェクト2010/第3回
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開始行:
[[西牧/春のプロジェクト2010]]
-alu_f.v
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define NOT 5'b10001
`define BNOT 5'b10010
module alu_f(a,b,f,s);
input [15:0] a,b;
input [4:0] f;
output [15:0] s;
reg [15:0] s;
wire [15:0] x,y;
assign x = 16'h8000 + a;
assign y = 16'h8000 + b;
function [15:0] dec;
input [4:0] din;
case(din)
`ADD: dec = b + a;
`SUB: dec = b - a;
`MUL: dec = b * a;
`SHL: dec = b << a;
`SHR: dec = b >> a;
`BAND: dec = b & a;
`BOR: dec = b | a;
`BXOR: dec = b ^ a;
`AND: dec = b && a;
`OR: dec = b || a;
`EQ: dec = b == a;
`NE: dec = b != a;
`GE: dec = x >= y;
`LE: dec = x <= y;
`GT: dec = x > y;
`LT: dec = x < y;
`NEG: dec = -a;
`BNOT: dec = ~a;
`NOT: dec = !a;
default: dec = 16'hxxxx;
endcase // case (f)
endfunction // case
always @( a or b or x or y or f) begin
s = dec(f);
end // always @ ( a or b or x or y or f)
endmodule // alu
-alu_f_tb.v
`timescale 1ns/1ps
`include "alu_f.v"
module alu_f_tb;
reg [15:0] a,b;
reg [4:0] f;
wire [15:0] s;
parameter S = 100;
alu_f alu_f(a,b,f,s);
initial begin
$dumpfile("alu_f_tb.vcd");
$dumpvars(0,alu_f_tb);
a = -2;
b = -3;
f = 5'b01100;
#S
a = -2;
#S
a = 0;
#S
a = 1;
#S
a = 2;
#S
a = 3;
#S
a = 4;
#S
a = 5;
#S
a = 6;
end // initial begin
initial $monitor("a=%d b=%d f=%d s=%d",a,b,f,s);
endmodule // alu_tb
終了行:
[[西牧/春のプロジェクト2010]]
-alu_f.v
`define ADD 5'b00000
`define SUB 5'b00001
`define MUL 5'b00010
`define SHL 5'b00011
`define SHR 5'b00100
`define BAND 5'b00101
`define BOR 5'b00110
`define BXOR 5'b00111
`define AND 5'b01000
`define OR 5'b01001
`define EQ 5'b01010
`define NE 5'b01011
`define GE 5'b01100
`define LE 5'b01101
`define GT 5'b01110
`define LT 5'b01111
`define NEG 5'b10000
`define NOT 5'b10001
`define BNOT 5'b10010
module alu_f(a,b,f,s);
input [15:0] a,b;
input [4:0] f;
output [15:0] s;
reg [15:0] s;
wire [15:0] x,y;
assign x = 16'h8000 + a;
assign y = 16'h8000 + b;
function [15:0] dec;
input [4:0] din;
case(din)
`ADD: dec = b + a;
`SUB: dec = b - a;
`MUL: dec = b * a;
`SHL: dec = b << a;
`SHR: dec = b >> a;
`BAND: dec = b & a;
`BOR: dec = b | a;
`BXOR: dec = b ^ a;
`AND: dec = b && a;
`OR: dec = b || a;
`EQ: dec = b == a;
`NE: dec = b != a;
`GE: dec = x >= y;
`LE: dec = x <= y;
`GT: dec = x > y;
`LT: dec = x < y;
`NEG: dec = -a;
`BNOT: dec = ~a;
`NOT: dec = !a;
default: dec = 16'hxxxx;
endcase // case (f)
endfunction // case
always @( a or b or x or y or f) begin
s = dec(f);
end // always @ ( a or b or x or y or f)
endmodule // alu
-alu_f_tb.v
`timescale 1ns/1ps
`include "alu_f.v"
module alu_f_tb;
reg [15:0] a,b;
reg [4:0] f;
wire [15:0] s;
parameter S = 100;
alu_f alu_f(a,b,f,s);
initial begin
$dumpfile("alu_f_tb.vcd");
$dumpvars(0,alu_f_tb);
a = -2;
b = -3;
f = 5'b01100;
#S
a = -2;
#S
a = 0;
#S
a = 1;
#S
a = 2;
#S
a = 3;
#S
a = 4;
#S
a = 5;
#S
a = 6;
end // initial begin
initial $monitor("a=%d b=%d f=%d s=%d",a,b,f,s);
endmodule // alu_tb
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