西牧/春のプロジェクト2010/第2回
をテンプレートにして作成
[
トップ
] [
新規
|
一覧
|
単語検索
|
最終更新
|
ヘルプ
|
ログイン
]
開始行:
[[西牧/春のプロジェクト2010]]
-adder4.v
module adder4(a,b,s);
input [3:0] a,b;
output [3:0] s;
wire [2:0] c;
assign s[0] = a[0] ^ b[0];
assign c[0] = a[0] & b[0];
assign s[1] = a[1] ^ b[1] ^ c[0];
assign c[1] = (a[1] & b[1]) | (a[1] & c[0]) | (b[1] & c[0]);
assign s[2] = a[2] ^ b[2] ^ c[1];
assign c[2] = (a[2] & b[2]) | (a[2] & c[1]) | (b[2] & c[1]);
assign s[3] = a[3] ^ b[3] ^ c[2];
endmodule // adder4
-aadder4_1.v
module adder4_1(a,b,s);
input [3:0] a,b;
output [3:0] s;
reg [3:0] s;
always @(a or b) begin
s = a + b;
end
endmodule // adder4_1
-adder4_2.v
`include "fa.v"
module adder4_2(a,b,s);
input [3:0] a,b;
output [3:0] s;
wire [2:0] c;
fa fa0(a[0],b[0],0,s[0],c[0]);
fa fa1(a[1],b[1],c[0],s[1],c[1]);
fa fa2(a[2],b[2],c[1],s[2],c[2]);
fa fa3(a[3],b[3],c[2],s[3]);
endmodule // adder4_2
-adder4_tb.v
`timescale 1ns/1ps
`include "adder4.v"
module adder4_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_tb.vcd");
$dumpvars(0,adder4_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
-adder4_1_tb.v
`timescale 1ns/1ps
`include "adder4_1.v"
module adder4_1_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4_1 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_1_tb.vcd");
$dumpvars(0,adder4_1_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
-adder4_2_tb.v
`timescale 1ns/1ps
`include "adder4_2.v"
module adder4_2_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4_2 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_2_tb.vcd");
$dumpvars(0,adder4_2_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
終了行:
[[西牧/春のプロジェクト2010]]
-adder4.v
module adder4(a,b,s);
input [3:0] a,b;
output [3:0] s;
wire [2:0] c;
assign s[0] = a[0] ^ b[0];
assign c[0] = a[0] & b[0];
assign s[1] = a[1] ^ b[1] ^ c[0];
assign c[1] = (a[1] & b[1]) | (a[1] & c[0]) | (b[1] & c[0]);
assign s[2] = a[2] ^ b[2] ^ c[1];
assign c[2] = (a[2] & b[2]) | (a[2] & c[1]) | (b[2] & c[1]);
assign s[3] = a[3] ^ b[3] ^ c[2];
endmodule // adder4
-aadder4_1.v
module adder4_1(a,b,s);
input [3:0] a,b;
output [3:0] s;
reg [3:0] s;
always @(a or b) begin
s = a + b;
end
endmodule // adder4_1
-adder4_2.v
`include "fa.v"
module adder4_2(a,b,s);
input [3:0] a,b;
output [3:0] s;
wire [2:0] c;
fa fa0(a[0],b[0],0,s[0],c[0]);
fa fa1(a[1],b[1],c[0],s[1],c[1]);
fa fa2(a[2],b[2],c[1],s[2],c[2]);
fa fa3(a[3],b[3],c[2],s[3]);
endmodule // adder4_2
-adder4_tb.v
`timescale 1ns/1ps
`include "adder4.v"
module adder4_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_tb.vcd");
$dumpvars(0,adder4_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
-adder4_1_tb.v
`timescale 1ns/1ps
`include "adder4_1.v"
module adder4_1_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4_1 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_1_tb.vcd");
$dumpvars(0,adder4_1_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
-adder4_2_tb.v
`timescale 1ns/1ps
`include "adder4_2.v"
module adder4_2_tb;
reg [3:0] a,b;
wire [3:0] s;
parameter S = 100;
adder4_2 adder4(.a(a),.b(b),.s(s));
initial begin
$dumpfile ("adder4_2_tb.vcd");
$dumpvars(0,adder4_2_tb);
a = 4'h0;
b = 4'h0;
#S a = 4'd1;
#S a = 4'd2;
#S b = 4'd7;
#S a = 4'd13;
#S a = 4'd11;
#S b = 4'd9;
#S b = 4'd14;
#S a = 4'd0;
b = 4'd0;
end // initial begin
initial $monitor("a=%d b=%d c=%d",a,b,s);
endmodule
ページ名: