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開始行:
[[上坂/研究]]
#contents
*[[進捗状況>上坂/研究/進捗・まとめ/進捗状況詳細]] [#ob48ecb6]
*Research Plan [#ka54797c]
**Optimization of OASIS NoC with SCB Architecture [#y866fef2]
-1.Explain OASIS Architecture(2)
--router, switching, topology, control flow
-2.Performance evaluation HW&SW(2)
-3.SCB algorithm(2-3)
--read source code and some explain
-4.Combine SCB and OASIS NoC(2-3)
-5.evaluation OASIS SCB(2)
-6.evaluation compare OASIS NoC with OASIS SCB(goal)
**To Do [#lde6b077]
-%%ONoCのポート数を増やす%%
-%%SCB挿入のためのルーティングを考える%%
--とりあえず、Source→Destinationへのルーティングを追加
-%%Scilabの使い方%%
-%%NoCシミュレータについて%%
--ModelSimを使用
-Testbenchを作る
--Uniform,Hot Spot,Transpose Traffic
-Simulationを実行
*メモ [#t4aa6246]
**論文集 [#x7793f60]
-[[basic:http://ihome.ust.hk/~ldcse/CSIT560_papers/NOC/TJASSST2006_manuscript.pdf]]
-[[NoC 論文:http://www.starg.org/doc/noc/]]
-[[Routing Algorithm:http://www3.pucrs.br/pucrs/files/uni/poa/facin/pos/relatoriostec/tr040.pdf]]
-[[several NoC:http://www.scientificjournals.org/journals2009/articles/1423.pdf]]
-[[ONoC velilog HDL:http://web-ext.u-aizu.ac.jp/~benab/publications/treport/oasis-noc-design-2010.pdf]]
**Quartusの設定(FPGA) [#jaf266a8]
-oasis解凍後の設定
--Family : Stratix III
--Target device : Specific device ...
--Show in 'Available device' list
---Package: FBGA
---Pin count: 1152
---Speed grade: 2
---"check" show advanced devices
--Available devices: EP3SL150F1152C2
-コンパイル後の見方
--Pin -> 外部I/Oの使用量(%)
--ALUTs -> FPGAのロジック使用量
--Logic utilization -> Area
--power… -> 消費電力
-コンパイルについて
--Analysis & Synthesisだけで十分
**[[数値演算ソフト>上坂/研究/進捗・まとめ/Scilab]] [#q243eb4c]
-様々な数値演算ソフトの使い方
--Scilab
--Mathmatica
**Simulation environment [#ua233bac]
-ONoC is designed in Verilog HDL
-Synthesized with Altera CAD tool
-Simulated with ModelSim
-Target application is JPEG2000 codec
**Model Simのtest bench [#cc85cd73]
Test bench: file_name.v
Top level: module_name
Instance: network(Hard ware_top module)
*RPS [#j696b88e]
-5/10
--森さんのFAN2009
-6/28
--森さんの卒論
-7/5
--森さんの"OASIS NoC Architecture Design in verilog HDL"
-7/12
--森さんの"OASIS NoC Architecture Design in verilog HDL" vol.2
-7/26
--Short cu bus
-8/12
--Short cu bus vol.2
-9/24
--Basic idea and flow chart
-10/12
--Flow Chart with Shortcut Bus implementation
---Flow Chartについての具体例を提示
---Hardwareを完成させる
-10/22
--Absence
-11/5
--Preliminary Presentation
---Optimization of Oasis Network-on-Chip with Shortcut Bus Architecture
-11/15
--Preliminary Presentation(研究室全体)
---Network-on-Chip customization with Shortcut Bus
-11/19
--Approach to implement Shortcut Bus
---Hard Ware完成
-12/3
--Calculation on Scilab
--Scilabプログラム終了
*RPR [#j7d72f8a]
-5/31
--[[evaluation:http://www.starg.org/doc/noc/evaluation/2006-Area-and-performance-optimization-of-a-generic-NoC.pdf]]
*Reference [#he42d424]
-森さんのFAN2009
--“Design and evaluation of a complexity effective network on-chip architecture on fpga,”
-森さんの卒業論文
--“Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip”
-RPR資料
--Area and Performance Optimization of a Generic Network-on-Chip Architectute
-森さんのレポート
--OASIS NoC Architecture Design, Technical Report
-Shortcut Busについて
--Power Reduction of CMP Communication Networks via RF-Interconnects
-routing, switching, flow control
--Survey of Network on Chip (NoC) Architectures & Contributions
-routing
--Evaluation of Routing Algorithms on Mesh Based NoCs
-Flow Control
--Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes
-Long Range Link
--It`s a Small World After All: NoC Performance Optimization Via Long Range Link Insertion
-Adaptive routing
--The Turn Model for Adaptive Routing
-Test bench
--The effect of Virtual Channel Organization on the Performance of Interconnection Networks
-Scilab
--http://www.scilab.org/
終了行:
[[上坂/研究]]
#contents
*[[進捗状況>上坂/研究/進捗・まとめ/進捗状況詳細]] [#ob48ecb6]
*Research Plan [#ka54797c]
**Optimization of OASIS NoC with SCB Architecture [#y866fef2]
-1.Explain OASIS Architecture(2)
--router, switching, topology, control flow
-2.Performance evaluation HW&SW(2)
-3.SCB algorithm(2-3)
--read source code and some explain
-4.Combine SCB and OASIS NoC(2-3)
-5.evaluation OASIS SCB(2)
-6.evaluation compare OASIS NoC with OASIS SCB(goal)
**To Do [#lde6b077]
-%%ONoCのポート数を増やす%%
-%%SCB挿入のためのルーティングを考える%%
--とりあえず、Source→Destinationへのルーティングを追加
-%%Scilabの使い方%%
-%%NoCシミュレータについて%%
--ModelSimを使用
-Testbenchを作る
--Uniform,Hot Spot,Transpose Traffic
-Simulationを実行
*メモ [#t4aa6246]
**論文集 [#x7793f60]
-[[basic:http://ihome.ust.hk/~ldcse/CSIT560_papers/NOC/TJASSST2006_manuscript.pdf]]
-[[NoC 論文:http://www.starg.org/doc/noc/]]
-[[Routing Algorithm:http://www3.pucrs.br/pucrs/files/uni/poa/facin/pos/relatoriostec/tr040.pdf]]
-[[several NoC:http://www.scientificjournals.org/journals2009/articles/1423.pdf]]
-[[ONoC velilog HDL:http://web-ext.u-aizu.ac.jp/~benab/publications/treport/oasis-noc-design-2010.pdf]]
**Quartusの設定(FPGA) [#jaf266a8]
-oasis解凍後の設定
--Family : Stratix III
--Target device : Specific device ...
--Show in 'Available device' list
---Package: FBGA
---Pin count: 1152
---Speed grade: 2
---"check" show advanced devices
--Available devices: EP3SL150F1152C2
-コンパイル後の見方
--Pin -> 外部I/Oの使用量(%)
--ALUTs -> FPGAのロジック使用量
--Logic utilization -> Area
--power… -> 消費電力
-コンパイルについて
--Analysis & Synthesisだけで十分
**[[数値演算ソフト>上坂/研究/進捗・まとめ/Scilab]] [#q243eb4c]
-様々な数値演算ソフトの使い方
--Scilab
--Mathmatica
**Simulation environment [#ua233bac]
-ONoC is designed in Verilog HDL
-Synthesized with Altera CAD tool
-Simulated with ModelSim
-Target application is JPEG2000 codec
**Model Simのtest bench [#cc85cd73]
Test bench: file_name.v
Top level: module_name
Instance: network(Hard ware_top module)
*RPS [#j696b88e]
-5/10
--森さんのFAN2009
-6/28
--森さんの卒論
-7/5
--森さんの"OASIS NoC Architecture Design in verilog HDL"
-7/12
--森さんの"OASIS NoC Architecture Design in verilog HDL" vol.2
-7/26
--Short cu bus
-8/12
--Short cu bus vol.2
-9/24
--Basic idea and flow chart
-10/12
--Flow Chart with Shortcut Bus implementation
---Flow Chartについての具体例を提示
---Hardwareを完成させる
-10/22
--Absence
-11/5
--Preliminary Presentation
---Optimization of Oasis Network-on-Chip with Shortcut Bus Architecture
-11/15
--Preliminary Presentation(研究室全体)
---Network-on-Chip customization with Shortcut Bus
-11/19
--Approach to implement Shortcut Bus
---Hard Ware完成
-12/3
--Calculation on Scilab
--Scilabプログラム終了
*RPR [#j7d72f8a]
-5/31
--[[evaluation:http://www.starg.org/doc/noc/evaluation/2006-Area-and-performance-optimization-of-a-generic-NoC.pdf]]
*Reference [#he42d424]
-森さんのFAN2009
--“Design and evaluation of a complexity effective network on-chip architecture on fpga,”
-森さんの卒業論文
--“Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip”
-RPR資料
--Area and Performance Optimization of a Generic Network-on-Chip Architectute
-森さんのレポート
--OASIS NoC Architecture Design, Technical Report
-Shortcut Busについて
--Power Reduction of CMP Communication Networks via RF-Interconnects
-routing, switching, flow control
--Survey of Network on Chip (NoC) Architectures & Contributions
-routing
--Evaluation of Routing Algorithms on Mesh Based NoCs
-Flow Control
--Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes
-Long Range Link
--It`s a Small World After All: NoC Performance Optimization Via Long Range Link Insertion
-Adaptive routing
--The Turn Model for Adaptive Routing
-Test bench
--The effect of Virtual Channel Organization on the Performance of Interconnection Networks
-Scilab
--http://www.scilab.org/
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