三浦/第14回ASICデザインコンテスト/アセンブラ
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開始行:
[[三浦/第14回ASICデザインコンテスト]]
*Queue Assembly Language [#ib5ed5ca]
・for文のアセンブラ修正(Feb 23, 2009 )
~
・バックエンドの記述開始(Feb 27, 2009)
**Instructions [#c1416da2]
|Instruction |Assembly|Action|Detail in Japanese|
|no operation|nop |NO action||
|halt |hlt |Stopping PC||
|rot |rot |qt=qh||
|conver |covop addr1|set addr1||
|load |ld addr0(d)|qt=m(d+addr1.addr0)||
| |ldi value|qt=value||
|store |st addr0(d)|m(d+addr1.addr0)=qh||
|aset |setahh a, value|a(31-24bit)=value||
| |setahl a, value|a(23-16bit)=value||
| |setalh a, value|a(15-8bit)=value||
| |setall a,avalue|a(0-7bit)=value||
|dset |setdhh d, value|d(31-24bit)=value||
| |setdhl d, value|d(23-16bit)=value||
| |setdlh d, value|d(15-8bit)=value||
| |setdll d, value|d(0-7bit)=value||
|compare |comc c |CReg=(qh==c)? 1:0||
| |com n |CReg=(qh==(qh+1))? 1:0||
|branch |beq t |PC=PC+(addr1.t), if CReg==eq||
| |bne t |PC=PC+(addr1.t), if CReg==ne||
| |blt t |PC=PC+(addr1.t), if CReg==lt||
|jump |jmp t(a) |PC=(a)+(addr1.t)||
|ALU |add n |qt=qh+(qh+n)||
| |sub n |qt=qh-(qh+n)||
| |mul n |qt=qh*(qh+n)||
| |div n |qt=qh/(qh+n)||
| |and n |qt=qh and (qh+n)||
| |or n |qt=qh or (qh+n)||
|shift |sru s,n |qt=(qh+n)logical right shift (s bit)||
| |slu s,n |qt=(qh+n)logical left shift (s bit)||
| |sr s,n |qt=(qh+n)arithmetical right shift (s bit)||
**Assembly language template [#p80e2306]
1) if(a>0) a=a+1;
ld 0, 1
comc 0
blt L1
beq L1
ld 0, 1
sub 1
st 0, 1
L1:
2) while(1);
L0:
ld 0, 9
comc 0
beq L1
blt L1
jmp L0
L1:
3) for(i=0;i<10;i++);
ldi 0
st 0, 9
L0:
ld 0, 9
comc 10
blt L2
(beq L1)
jmp L1
L2:
ld 0, 9
ldi 1
add 1
st 0, 9
jmp L0
L1:
**課題プログラム [#ia50adf3]
***再帰呼び出し [#fe32d7ac]
ソースコード:
a=foo(5);
halt;
int foo(int arg) {
if(arg < 1) return arg;
return arg + foo(arg-1);
}
アセンブラ;
setahh $0 0
setahl $0 0
setalh $0 0
setall $0 0
setdhh $0 0
setdhl $0 0
setdlh $0 0
setdll $0 0
setdhh $0 1
setdhl $0 1
setdlh $0 1
setdll $127 1
ldi 5
jal foo
st 1($0)
hlt
jal L000
foo:
dsub $1 2
ast $1 0
st 1($1)
ldi 1
ld 1($1)
com 1
blt L001
ld 1($1)
jmp fooexit
L001:
ld 1($1)
dsub $1 1
st 0($1)
ld 2($1)
ldi 1
sub 1
jal foo
ld 0($1)
dadd $1 1
add 1
jmp fooexit
fooexit:
ald $1 0
dadd $1 2
jmp 0($1)
L000:
**Comment [#l1a42075]
#comment
終了行:
[[三浦/第14回ASICデザインコンテスト]]
*Queue Assembly Language [#ib5ed5ca]
・for文のアセンブラ修正(Feb 23, 2009 )
~
・バックエンドの記述開始(Feb 27, 2009)
**Instructions [#c1416da2]
|Instruction |Assembly|Action|Detail in Japanese|
|no operation|nop |NO action||
|halt |hlt |Stopping PC||
|rot |rot |qt=qh||
|conver |covop addr1|set addr1||
|load |ld addr0(d)|qt=m(d+addr1.addr0)||
| |ldi value|qt=value||
|store |st addr0(d)|m(d+addr1.addr0)=qh||
|aset |setahh a, value|a(31-24bit)=value||
| |setahl a, value|a(23-16bit)=value||
| |setalh a, value|a(15-8bit)=value||
| |setall a,avalue|a(0-7bit)=value||
|dset |setdhh d, value|d(31-24bit)=value||
| |setdhl d, value|d(23-16bit)=value||
| |setdlh d, value|d(15-8bit)=value||
| |setdll d, value|d(0-7bit)=value||
|compare |comc c |CReg=(qh==c)? 1:0||
| |com n |CReg=(qh==(qh+1))? 1:0||
|branch |beq t |PC=PC+(addr1.t), if CReg==eq||
| |bne t |PC=PC+(addr1.t), if CReg==ne||
| |blt t |PC=PC+(addr1.t), if CReg==lt||
|jump |jmp t(a) |PC=(a)+(addr1.t)||
|ALU |add n |qt=qh+(qh+n)||
| |sub n |qt=qh-(qh+n)||
| |mul n |qt=qh*(qh+n)||
| |div n |qt=qh/(qh+n)||
| |and n |qt=qh and (qh+n)||
| |or n |qt=qh or (qh+n)||
|shift |sru s,n |qt=(qh+n)logical right shift (s bit)||
| |slu s,n |qt=(qh+n)logical left shift (s bit)||
| |sr s,n |qt=(qh+n)arithmetical right shift (s bit)||
**Assembly language template [#p80e2306]
1) if(a>0) a=a+1;
ld 0, 1
comc 0
blt L1
beq L1
ld 0, 1
sub 1
st 0, 1
L1:
2) while(1);
L0:
ld 0, 9
comc 0
beq L1
blt L1
jmp L0
L1:
3) for(i=0;i<10;i++);
ldi 0
st 0, 9
L0:
ld 0, 9
comc 10
blt L2
(beq L1)
jmp L1
L2:
ld 0, 9
ldi 1
add 1
st 0, 9
jmp L0
L1:
**課題プログラム [#ia50adf3]
***再帰呼び出し [#fe32d7ac]
ソースコード:
a=foo(5);
halt;
int foo(int arg) {
if(arg < 1) return arg;
return arg + foo(arg-1);
}
アセンブラ;
setahh $0 0
setahl $0 0
setalh $0 0
setall $0 0
setdhh $0 0
setdhl $0 0
setdlh $0 0
setdll $0 0
setdhh $0 1
setdhl $0 1
setdlh $0 1
setdll $127 1
ldi 5
jal foo
st 1($0)
hlt
jal L000
foo:
dsub $1 2
ast $1 0
st 1($1)
ldi 1
ld 1($1)
com 1
blt L001
ld 1($1)
jmp fooexit
L001:
ld 1($1)
dsub $1 1
st 0($1)
ld 2($1)
ldi 1
sub 1
jal foo
ld 0($1)
dadd $1 1
add 1
jmp fooexit
fooexit:
ald $1 0
dadd $1 2
jmp 0($1)
L000:
**Comment [#l1a42075]
#comment
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