º´Æ£/PGRmemo
¤ò¥Æ¥ó¥×¥ì¡¼¥È¤Ë¤·¤ÆºîÀ®
[
¥È¥Ã¥×
] [
¿·µ¬
|
°ìÍ÷
|
ñ¸ì¸¡º÷
|
ºÇ½ª¹¹¿·
|
¥Ø¥ë¥×
|
¥í¥°¥¤¥ó
]
³«»Ï¹Ô:
//¸¦µæ¼¼¸ÂÄê
[[º´Æ£/³Ø½¬]]
*PGR¤Çʬ¤«¤Ã¤¿¤¤¤í¤¤¤í [#p10f406e]
**pg_float_div [#e1c47e7c]
pg_float_div¤Ï¡¢pg_float_recipro¤Èpg_float_mult¤ÎÁȤ߹ç¤ï¤»¤Ç¼Â¸½¤µ¤ì¤ë¡£&br;
pg_float_div¤À¤È¹çÀ®»þ¤Ë¥¨¥é¡¼¤¬µ¯¤¤ë¤Î¤Ç¡¢½ü»»´ï¤ò»È¤¤¤¿¤¤¤Ê¤épg_float_recipro¤Èpg_float_mult¤òÁȤ߹ç¤ï¤»¤Æ»È¤Ã¤¿¤Û¤¦¤¬¤¤¤¤(¤¿¤Ö¤ó)¡£
pg_float_div(x,y,z,NFLO,NMAN,NST);
¡¡¡¡¢
¢
pg_float_recipro(y,ry,NFLO,NMAN,NST);
pg_float_mult(x,ry,z,NFLO,NMAN,NST);
&br;
&br;
**pg_float_accum [#y8156e13]
¡pg_pipev.c¤Çsum¤È¤¤¤¦Ì¤ÄêµÁ¤ÎÊÑ¿ô¤¬½Ð¤Æ¤¯¤ë¡£&br;
¢ISE_PROJECT/pgpg_mem/pg_pipe.vhd¤Ç¡¢&br;¡¡¡¡
pg_float_accum_26_16_4_6 port map(x=>dens, z=>datarho, clk=>pclk,run=>run); ¡¡&br;
¤È¤¤¤¦µ½Ò(°ìÎã¤Ç¤¹)¤¬¼«Æ°¤ÇÀ¸À®¤µ¤ì¤ë¤Î¤À¤¬¡¢¤³¤Î¤Þ¤Þ¤À¤Èrun(std_logic)=>run(std_logic_vector)¤Ê¤Î¤Ç¡¢run¤ò£±bit»ØÄꤷ¤Ê¤±¤ì¤Ð¤¤¤±¤Ê¤¤¡£&br;
¡ÊÎã¡Ëpg_float_accum_26_16_4_6 port map(x=>dens, z=>datarho, clk=>pclk,run=>run(10)); &br;
&br;
&br;
**ISE_PROJECT/proj¤Î¥Õ¥¡¥¤¥ë¤Ë¤Ä¤¤¤Æ [#ae0c2fcc]
--top.par¡§ Device Utilization Summary
--top.syr¡§ Synthesis Options Summary
--top_map.mrp¡§ Design Information, Design Summary(Number of Slice FF and LUTs)
½ªÎ»¹Ô:
//¸¦µæ¼¼¸ÂÄê
[[º´Æ£/³Ø½¬]]
*PGR¤Çʬ¤«¤Ã¤¿¤¤¤í¤¤¤í [#p10f406e]
**pg_float_div [#e1c47e7c]
pg_float_div¤Ï¡¢pg_float_recipro¤Èpg_float_mult¤ÎÁȤ߹ç¤ï¤»¤Ç¼Â¸½¤µ¤ì¤ë¡£&br;
pg_float_div¤À¤È¹çÀ®»þ¤Ë¥¨¥é¡¼¤¬µ¯¤¤ë¤Î¤Ç¡¢½ü»»´ï¤ò»È¤¤¤¿¤¤¤Ê¤épg_float_recipro¤Èpg_float_mult¤òÁȤ߹ç¤ï¤»¤Æ»È¤Ã¤¿¤Û¤¦¤¬¤¤¤¤(¤¿¤Ö¤ó)¡£
pg_float_div(x,y,z,NFLO,NMAN,NST);
¡¡¡¡¢
¢
pg_float_recipro(y,ry,NFLO,NMAN,NST);
pg_float_mult(x,ry,z,NFLO,NMAN,NST);
&br;
&br;
**pg_float_accum [#y8156e13]
¡pg_pipev.c¤Çsum¤È¤¤¤¦Ì¤ÄêµÁ¤ÎÊÑ¿ô¤¬½Ð¤Æ¤¯¤ë¡£&br;
¢ISE_PROJECT/pgpg_mem/pg_pipe.vhd¤Ç¡¢&br;¡¡¡¡
pg_float_accum_26_16_4_6 port map(x=>dens, z=>datarho, clk=>pclk,run=>run); ¡¡&br;
¤È¤¤¤¦µ½Ò(°ìÎã¤Ç¤¹)¤¬¼«Æ°¤ÇÀ¸À®¤µ¤ì¤ë¤Î¤À¤¬¡¢¤³¤Î¤Þ¤Þ¤À¤Èrun(std_logic)=>run(std_logic_vector)¤Ê¤Î¤Ç¡¢run¤ò£±bit»ØÄꤷ¤Ê¤±¤ì¤Ð¤¤¤±¤Ê¤¤¡£&br;
¡ÊÎã¡Ëpg_float_accum_26_16_4_6 port map(x=>dens, z=>datarho, clk=>pclk,run=>run(10)); &br;
&br;
&br;
**ISE_PROJECT/proj¤Î¥Õ¥¡¥¤¥ë¤Ë¤Ä¤¤¤Æ [#ae0c2fcc]
--top.par¡§ Device Utilization Summary
--top.syr¡§ Synthesis Options Summary
--top_map.mrp¡§ Design Information, Design Summary(Number of Slice FF and LUTs)
¥Ú¡¼¥¸Ì¾: