+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+*
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a4d33608256f53d59b1c6470b9627803ea20b55
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb599b5602601d799de56541046a0530075fedff
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..549bfff298f5c67a35b28b5231b1636dafd4396c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* XADC Channel Sequencer Modes
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - Default : This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - One pass through sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - Continuous cycling of sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - Single channel mode: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - Simultaneous Sampling Mode: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - Independent ADC mode: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* Building the driver
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* Limitations of the driver
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..55a47a440a6a9933952aa7d70ad73b5e198c689b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+*
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9feb45eea12f5c634efd70ae448956054963f562
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h
@@ -0,0 +1,577 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps.h
+* @addtogroup canps_v3_2
+* @{
+* @details
+*
+* The Xilinx CAN driver component. This component supports the Xilinx
+* CAN Controller.
+*
+* The CAN Controller supports the following features:
+* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
+* - Supports both Standard (11 bit Identifier) and Extended (29 bit
+* Identifier) frames.
+* - Supports Bit Rates up to 1 Mbps.
+* - Transmit message object FIFO with a user configurable depth of
+* up to 64 message objects.
+* - Transmit prioritization through one TX High Priority Buffer.
+* - Receive message object FIFO with a user configurable depth of
+* up to 64 message objects.
+* - Watermark interrupts for Rx FIFO with configurable Watermark.
+* - Acceptance filtering with 4 acceptance filters.
+* - Sleep mode with automatic wake up.
+* - Loop Back mode for diagnostic applications.
+* - Snoop mode for diagnostic applications.
+* - Maskable Error and Status Interrupts.
+* - Readable Error Counters.
+* - External PHY chip required.
+* - Receive Timestamp.
+*
+* The device driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the CAN. The driver handles transmission and reception of
+* CAN frames, as well as configuration of the controller. The driver is simply a
+* pass-through mechanism between a protocol stack and the CAN. A single device
+* driver can support multiple CANs.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the CAN, no assembly or disassembly of CAN frames is done at the
+* driver-level. This assumes that the protocol stack passes a correctly
+* formatted CAN frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame
+*
+* Operation Modes
+*
+* The CAN controller supports the following modes of operation:
+* - Configuration Mode: In this mode the CAN timing parameters and
+* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
+* controller loses synchronization with the CAN bus and drives a
+* constant recessive bit on the bus line. The Error Counter Register are
+* reset. The CAN controller does not receive or transmit any messages
+* even if there are pending transmit requests from the TX FIFO or the TX
+* High Priority Buffer. The Storage FIFOs and the CAN configuration
+* registers are still accessible.
+* - Normal Mode:In Normal Mode the CAN controller participates in bus
+* communication, by transmitting and receiving messages.
+* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any
+* messages. However, if any other node transmits a message, then the CAN
+* Controller receives the transmitted message and exits from Sleep Mode.
+* If there are new transmission requests from either the TX FIFO or the
+* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
+* requests are not serviced, and the CAN Controller continues to remain
+* in Sleep Mode. Interrupts are generated when the CAN controller enters
+* Sleep mode or Wakes up from Sleep mode.
+* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a
+* recessive bit stream on to the CAN Bus. Any message that is transmitted
+* is looped back to the �Rx� line and acknowledged. The CAN controller
+* thus receives any message that it transmits. It does not participate in
+* normal bus communication and does not receive any messages that are
+* transmitted by other CAN nodes. This mode is used for diagnostic
+* purposes.
+* - Snoop Mode: In Snoop mode, the CAN controller transmits a
+* recessive bit stream on to the CAN Bus and does not participate
+* in normal bus communication but receives messages that are transmitted
+* by other CAN nodes. This mode is used for diagnostic purposes.
+*
+*
+* Buffer Alignment
+*
+* It is important to note that frame buffers passed to the driver must be
+* 32-bit aligned.
+*
+* Receive Address Filtering
+*
+* The device can be set to accept frames whose Identifiers match any of the
+* 4 filters set in the Acceptance Filter Mask/ID registers.
+*
+* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
+* Register. This value is compared with the result of masking the bits in the
+* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
+* both these values are equal, the message will be stored in the RX FIFO.
+*
+* Acceptance Filtering is performed by each of the defined acceptance filters.
+* If the incoming identifier passes through any acceptance filter then the
+* frame is stored in the RX FIFO.
+*
+* If the Accpetance Filters are not set up then all the received messages are
+* stroed in the RX FIFO.
+*
+* PHY Communication
+*
+* This driver does not provide any mechanism for directly programming PHY.
+*
+* Interrupts
+*
+* The driver has no dependencies on the interrupt controller. The driver
+* provides an interrupt handler. User of this driver needs to provide
+* callback functions. An interrupt handler example is available with
+* the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Device Reset
+*
+* Bus Off interrupt that can occur in the device requires a device reset.
+* The user is responsible for resetting the device and re-configuring it
+* based on its needs (the driver does not save the current configuration).
+* When integrating into an RTOS, these reset and re-configure obligations are
+* taken care of by the OS adapter software if it exists for that RTOS.
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xcanps_g.c files.
+* A table is defined where each entry contains configuration information
+* for a CAN device. This information includes such things as the base address
+* of the memory-mapped device.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XCanPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* XCanPs_GetTxIntrWatermark.
+* Updated the Register/bit definitions
+* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+* Changed XCANPS_IXR_RXFLL_MASK to
+* XCANPS_IXR_RXFWMFLL_MASK
+* Changed
+* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+* SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk 09/12/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.1 adk 10/11/15 Fixed CR#911958 Add support for Tx Watermark example.
+* Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+* error interrupts correctly. CR#925615
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XCANPS_H /* prevent circular inclusions */
+#define XCANPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xcanps_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name CAN operation modes
+ * @{
+ */
+#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */
+#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */
+#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */
+#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */
+#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */
+/* @} */
+
+/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
+ * @{
+ */
+#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
+#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
+#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */
+#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XCanPs_Config;
+
+/******************************************************************************/
+/**
+ * Callback type for frame sending and reception interrupts.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+ * Callback type for error interrupt.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ * @param ErrorMask is a bit mask indicating the cause of the error. Its
+ * value equals 'OR'ing one or more XCANPS_ESR_* values defined in
+ * xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/******************************************************************************/
+/**
+ * Callback type for all kinds of interrupts except sending frame interrupt,
+ * receiving frame interrupt, and error interrupt.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ * @param Mask is a bit mask indicating the pending interrupts. Its value
+ * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
+
+/**
+ * The XCanPs driver instance data. The user is required to allocate a
+ * variable of this type for every CAN device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XCanPs_Config CanConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ /**
+ * Callback and callback reference for TXOK interrupt.
+ */
+ XCanPs_SendRecvHandler SendHandler;
+ void *SendRef;
+
+ /**
+ * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
+ */
+ XCanPs_SendRecvHandler RecvHandler;
+ void *RecvRef;
+
+ /**
+ * Callback and callback reference for ERROR interrupt.
+ */
+ XCanPs_ErrorHandler ErrorHandler;
+ void *ErrorRef;
+
+ /**
+ * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
+ * Wakeup/Sleep/Bus off/ARBLST interrupts.
+ */
+ XCanPs_EventHandler EventHandler;
+ void *EventRef;
+
+} XCanPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission is complete.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the transmission is done.
+* - FALSE if the transmission is not done.
+*
+* @note C-Style signature:
+* int XCanPs_IsTxDone(XCanPs *InstancePtr)
+*
+*******************************************************************************/
+#define XCanPs_IsTxDone(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission FIFO is full.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if TX FIFO is full.
+* - FALSE if the TX FIFO is NOT full.
+*
+* @note C-Style signature:
+* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsTxFifoFull(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the Transmission High Priority Buffer is full.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the TX High Priority Buffer is full.
+* - FALSE if the TX High Priority Buffer is NOT full.
+*
+* @note C-Style signature:
+* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the receive FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if RX FIFO is empty.
+* - FALSE if the RX FIFO is NOT empty.
+*
+* @note C-Style signature:
+* int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsRxEmpty(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the CAN device is ready for the driver to change
+* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
+* Registers (AFMR).
+*
+* AFIR and AFMR for a filter are changeable only after the filter is disabled
+* and this routine returns FALSE. The filter can be disabled using the
+* XCanPs_AcceptFilterDisable function.
+*
+* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the device is busy and NOT ready to accept writes to
+* AFIR and AFMR.
+* - FALSE if the device is ready to accept writes to AFIR and
+* AFMR.
+*
+* @note C-Style signature:
+* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsAcceptFilterBusy(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates CAN message identifier value given identifier field
+* values.
+*
+* @param StandardId contains Standard Message ID value.
+* @param SubRemoteTransReq contains Substitute Remote Transmission
+* Request value.
+* @param IdExtension contains Identifier Extension value.
+* @param ExtendedId contains Extended Message ID value.
+* @param RemoteTransReq contains Remote Transmission Request value.
+*
+* @return Message Identifier value.
+*
+* @note C-Style signature:
+* u32 XCanPs_CreateIdValue(u32 StandardId,
+* u32 SubRemoteTransReq,
+* u32 IdExtension, u32 ExtendedId,
+* u32 RemoteTransReq)
+*
+* Read the CAN specification for meaning of each parameter.
+*
+*****************************************************************************/
+#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
+ ExtendedId, RemoteTransReq) \
+ ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \
+ (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
+ (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \
+ (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \
+ ((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates value for Data Length Code register given Data
+* Length Code value.
+*
+* @param DataLengCode indicates Data Length Code value.
+*
+* @return Value that can be assigned to Data Length Code register.
+*
+* @note C-Style signature:
+* u32 XCanPs_CreateDlcValue(u32 DataLengCode)
+*
+* Read the CAN specification for meaning of Data Length Code.
+*
+*****************************************************************************/
+#define XCanPs_CreateDlcValue(DataLengCode) \
+ (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the timestamp in the Timestamp Control Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_ClearTimestamp(InstancePtr) \
+ XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \
+ XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xcanps.c
+ */
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+void XCanPs_Reset(XCanPs *InstancePtr);
+u8 XCanPs_GetMode(XCanPs *InstancePtr);
+void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
+u32 XCanPs_GetStatus(XCanPs *InstancePtr);
+void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
+ u8 *TxErrorCount);
+u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
+void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
+void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
+void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
+u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 MaskValue, u32 IdValue);
+void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 *MaskValue, u32 *IdValue);
+
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
+u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+ u8 TimeSegment2, u8 TimeSegment1);
+void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
+ u8 *TimeSegment2, u8 *TimeSegment1);
+
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
+
+/*
+ * Diagnostic functions in xcanps_selftest.c
+ */
+s32 XCanPs_SelfTest(XCanPs *InstancePtr);
+
+/*
+ * Functions in xcanps_intr.c
+ */
+void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
+u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
+u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
+void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrHandler(void *InstancePtr);
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+ void *CallBackFunc, void *CallBackRef);
+
+/*
+ * Functions in xcanps_sinit.c
+ */
+XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..30ec68ab9729312706bb2d9833949250b385f9d9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_hw.h
+* @addtogroup canps_v3_2
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xcanps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 1.01a sbs 12/27/11 Updated the Register/bit definitions
+* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+* Changed XCANPS_IXR_RXFLL_MASK to
+* XCANPS_IXR_RXFWMFLL_MASK
+* Changed
+* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk 08/08/13 Updated for inclding the function prototype
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+#ifndef XCANPS_HW_H /* prevent circular inclusions */
+#define XCANPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the CAN. Each register is 32 bits.
+ * @{
+ */
+#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */
+#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */
+#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */
+#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */
+#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */
+#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */
+#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */
+
+#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */
+#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */
+#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */
+#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */
+#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */
+
+#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */
+#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */
+#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */
+#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */
+
+#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */
+#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */
+#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */
+#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */
+
+#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */
+#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */
+#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */
+#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */
+
+#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */
+#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */
+#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */
+#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */
+#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */
+#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */
+#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */
+#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */
+#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */
+/* @} */
+
+/** @name Software Reset Register (SRR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */
+#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */
+/* @} */
+
+/** @name Mode Select Register (MSR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */
+#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */
+#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */
+/* @} */
+
+/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */
+/* @} */
+
+/** @name Bit Timing Register (BTR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */
+#define XCANPS_BTR_SJW_SHIFT 7U
+#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */
+#define XCANPS_BTR_TS2_SHIFT 4U
+#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */
+/* @} */
+
+/** @name Error Counter Register (ECR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */
+#define XCANPS_ECR_REC_SHIFT 8U
+#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */
+/* @} */
+
+/** @name Error Status Register (ESR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */
+#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */
+#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */
+#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */
+#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */
+/* @} */
+
+/** @name Status Register (SR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */
+#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */
+#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */
+#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */
+#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */
+#define XCANPS_SR_ESTAT_SHIFT 7U
+#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */
+#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */
+#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */
+#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */
+#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */
+#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */
+#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */
+/* @} */
+
+/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */
+#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
+#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
+#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */
+#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */
+#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */
+#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */
+#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */
+#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */
+#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */
+#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */
+#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */
+#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */
+#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */
+#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */
+#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \
+ (u32)XCANPS_IXR_WKUP_MASK | \
+ (u32)XCANPS_IXR_SLP_MASK | \
+ (u32)XCANPS_IXR_BSOFF_MASK | \
+ (u32)XCANPS_IXR_ERROR_MASK | \
+ (u32)XCANPS_IXR_RXNEMP_MASK | \
+ (u32)XCANPS_IXR_RXOFLW_MASK | \
+ (u32)XCANPS_IXR_RXUFLW_MASK | \
+ (u32)XCANPS_IXR_RXOK_MASK | \
+ (u32)XCANPS_IXR_TXBFLL_MASK | \
+ (u32)XCANPS_IXR_TXFLL_MASK | \
+ (u32)XCANPS_IXR_TXOK_MASK | \
+ (u32)XCANPS_IXR_ARBLST_MASK)
+/* @} */
+
+/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */
+/* @} */
+
+/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */
+#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */
+#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */
+
+/* @} */
+
+/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
+ Mask/Acceptance Filter ID)
+ * @{
+ */
+#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */
+#define XCANPS_IDR_ID1_SHIFT 21U
+#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */
+#define XCANPS_IDR_SRR_SHIFT 20U
+#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */
+#define XCANPS_IDR_IDE_SHIFT 19U
+#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */
+#define XCANPS_IDR_ID2_SHIFT 1U
+#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */
+/* @} */
+
+/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */
+#define XCANPS_DLCR_DLC_SHIFT 28U
+#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */
+
+/* @} */
+
+/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */
+#define XCANPS_DW1R_DB0_SHIFT 24U
+#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */
+#define XCANPS_DW1R_DB1_SHIFT 16U
+#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */
+#define XCANPS_DW1R_DB2_SHIFT 8U
+#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */
+/* @} */
+
+/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */
+#define XCANPS_DW2R_DB4_SHIFT 24U
+#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */
+#define XCANPS_DW2R_DB5_SHIFT 16U
+#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */
+#define XCANPS_DW2R_DB6_SHIFT 8U
+#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */
+/* @} */
+
+/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */
+#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */
+#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */
+#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */
+#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \
+ (u32)XCANPS_AFR_UAF3_MASK | \
+ (u32)XCANPS_AFR_UAF2_MASK | \
+ (u32)XCANPS_AFR_UAF1_MASK)
+/* @} */
+
+/** @name CAN frame length constants
+ * @{
+ */
+#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
+/* @} */
+
+/* For backwards compatibilty */
+#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET
+#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET
+#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET
+#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET
+
+#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
+#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET
+#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK
+
+
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XCanPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the CanPs interface
+ */
+void XCanPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..67959e3274632a6ca7b5bd3225679cc0c3e1f10f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..95c8ba5360707e6032e28cfc4847ee9df969fd1c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_5
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+******************************************************************************/
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h
new file mode 100644
index 0000000000000000000000000000000000000000..c8804d2ed33d87cd0d678d73a63bb0ddedee86f1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h
new file mode 100644
index 0000000000000000000000000000000000000000..650946bd01f4555daaeaf12db9919130e4aecf7d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..b9a0111d695aeb71f09195025549f3df8283d9fb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h
@@ -0,0 +1,403 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c506ca59fc936b96086d96b074f85bee0959c104
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
@@ -0,0 +1,395 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a0c1a28e3d1a6a35a13ffe728420c260da05f5b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_3
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..628f1ec4f92b9a685afcb900029ac9d3d41c89fa
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_3
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h
new file mode 100644
index 0000000000000000000000000000000000000000..6d4b15b24338a4618844512250528f0c1fc1897a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h
@@ -0,0 +1,809 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_7
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h
new file mode 100644
index 0000000000000000000000000000000000000000..83f9a87fc1e6b6411f50a38931636c0a20f1144c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h
@@ -0,0 +1,804 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_7
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
new file mode 100644
index 0000000000000000000000000000000000000000..b89e89885b9109f3db432b7592b1d71dd8c6e88d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -0,0 +1,241 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..e535470c2e5b0c663b26a7780c0e2c42ccdb5edb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
+ transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
+ */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h
new file mode 100644
index 0000000000000000000000000000000000000000..3d97bebd450eda76d8221c8a9b012bb723c9b6ca
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+*
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h
new file mode 100644
index 0000000000000000000000000000000000000000..f18601874bb5b8a84f10954730b4aca1bc988598
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h
new file mode 100644
index 0000000000000000000000000000000000000000..fda562d9190651d7a655d00c57d930d13fad5232
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h
@@ -0,0 +1,277 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_3
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ff01906750193cf49b097c7921a0c38c516c4641
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h
new file mode 100644
index 0000000000000000000000000000000000000000..d3713de471faaa1242d156a58b25ab89ced025b7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h
@@ -0,0 +1,425 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_7
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface. The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+* the static configuration structure defined in xiicps_g.c. This is
+* setup by the tools. For some operating systems the config structure
+* will be initialized by the software and this call is not needed.
+*
+* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a
+* system with address translation, the provided virtual memory base
+* address replaces the physical address in the configuration
+* structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*Repeated Start
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/08 First release
+* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
+* XIicPs_ClearOptions where the InstancePtr->Options
+* was not updated correctly.
+* Updated the InstancePtr->Options in the
+* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* Updated the XIicPs_SetupMaster to not check for
+* Bus Busy condition when the Hold Bit is set.
+* Removed some unused variables.
+* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+* check for transfer completion is added, which indicates
+* the completion of current transfer.
+* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
+* to achieve I2C clock with minimum error for
+* CR #674195
+* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
+* This is fix for CR#704398 to remove warning.
+* 2.0 hk 03/07/14 Added check for error status in the while loop that
+* checks for completion.
+* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+* Limited frequency set when 100KHz or 400KHz is
+* selected. This is a hardware limitation. CR#779290.
+* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+* Explicitly reset CR and clear FIFO in Abort function
+* and state the same in the comments. CR# 784254.
+* Fix for CR# 761060 - provision for repeated start.
+* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
+* read mode and clear transfer size register.
+* Disable NACK to avoid interrupts on each retry.
+* 2.3 sk 10/07/14 Repeated start feature deleted.
+* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
+* in XIicPs_Reset.
+* 12/06/14 Implemented Repeated start feature.
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 02/18/15 Implemented larger data transfer using repeated start
+* in Zynq UltraScale MP.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
+* as per the other examples (CR#997545)
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIICPS_H /* prevent circular inclusions */
+#define XIICPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC. Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver. These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
+#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE 1 /**< Transfer direction is sending */
+#define RECVING_ROLE 0 /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* not important to the driver, so it is a void pointer.
+* @param StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XIicPs_Config Config; /* Configuration structure */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Options set in the device */
+
+ u8 *SendBufferPtr; /* Pointer to send buffer */
+ u8 *RecvBufferPtr; /* Pointer to recv buffer */
+ s32 SendByteCount; /* Number of bytes still expected to send */
+ s32 RecvByteCount; /* Number of bytes still expected to receive */
+ s32 CurrByteCount; /* No. of bytes expected in current transfer */
+
+ s32 UpdateTxSize; /* If tx size register has to be updated */
+ s32 IsSend; /* Whether master is sending or receiving */
+ s32 IsRepeatedStart; /* Indicates if user set repeated start */
+
+ XIicPs_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param InstancePtr is the instance of IIC
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr) \
+{ \
+ u8 Data; \
+ Data = *((InstancePtr)->SendBufferPtr); \
+ XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ + (u32)(XIICPS_DATA_OFFSET), \
+ (u32)(Data)); \
+ (InstancePtr)->SendBufferPtr += 1; \
+ (InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param InstancePtr is the instance of IIC
+*
+* @return None.
+*
+* @note C-Style signature:
+* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr) \
+{ \
+ u8 *Data, Value; \
+ Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ + (u32)XIICPS_DATA_OFFSET)); \
+ Data = &Value; \
+ *(InstancePtr)->RecvBufferPtr = *Data; \
+ (InstancePtr)->RecvBufferPtr += 1; \
+ (InstancePtr)->RecvByteCount --; \
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+ u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+ XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9d63ec8f68e84d3d746dee4b0d7cabe4a6f9975
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_7
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.04a kpc 11/07/13 Added function prototype.
+* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H /* prevent circular inclusions */
+#define XIICPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
+#define XIICPS_SR_OFFSET 0x04U /**< Status */
+#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
+#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
+#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
+ 0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
+ Master receiver*/
+#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
+ 0=10 bit */
+#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
+ 0=Slave */
+#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
+ transfer 0=Transmitter,
+ 1=Receiver*/
+#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
+ register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists. Other flags are
+ * edge triggered, which means they are set one the interrupt condition occurs
+ * then remain set until they are cleared by software.
+ * The interrupts are cleared by writing a one to the interrupt bit position
+ * in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Disable Register
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
+ mask */
+#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
+ Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
+ Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
+ mask */
+#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
+ Interrupt mask */
+#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
+ Interrupt mask */
+#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
+ Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+* - Master transmitter mode: number of data bytes still not transmitted minus
+* one
+* - Master receiver mode: number of data bytes that are still expected to be
+* received
+* - Slave transmitter mode: number of bytes remaining in the FIFO after the
+* master terminates the transfer
+* - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+ XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return Current bit mask that represents currently enabled interrupts.
+*
+* @note C-Style signature:
+* u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+ XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param IntrMask is the interrupts to be enabled.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+ XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param IntrMask is the interrupts to be disabled.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+ (IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h
new file mode 100644
index 0000000000000000000000000000000000000000..add4124e2c0c48a8844dfb3aad307c8ec5ae6e38
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accomodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6614d5f992709379ce97da6e8be0cfb9eb80d8b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..fa92c6b1c4087b05b80e256770a5c0d023d99fe2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h
new file mode 100644
index 0000000000000000000000000000000000000000..490aebeabe7f0d17ed05105a8bfe9433f74515fd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+*
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h
new file mode 100644
index 0000000000000000000000000000000000000000..83303875d43a0de16324293bade2e2050e7d1370
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h
@@ -0,0 +1,260 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h
new file mode 100644
index 0000000000000000000000000000000000000000..d4434d07fa748457f2f476ebf82f9f8b20c93c91
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c5aa43c7ecbc506145d0aaf5f409992bb08036e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebafde87d7ff8a38bd28724a08ecca7701ea4f58
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h
new file mode 100644
index 0000000000000000000000000000000000000000..a2d5e6681d9b82f40e81baa106789d512da27f6b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
new file mode 100644
index 0000000000000000000000000000000000000000..c228c988eb3035912db6e0d906d41609afac4b38
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd14b63b7057e38c5df9eadbab636379d684e30e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h
new file mode 100644
index 0000000000000000000000000000000000000000..016ae3b2f6b40423b9efe6063e2282dc1d9ffb74
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..4bfac0ac46f7d9516516cb2c0dbc6c85977e2cac
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+*
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h
new file mode 100644
index 0000000000000000000000000000000000000000..c35e9a463f05d7fa7e176b96369f5af1493d3127
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+*
Cache test
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad68ead6430fef3b1a961165119aca5b8c557652
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+*
I/O test
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h
new file mode 100644
index 0000000000000000000000000000000000000000..c204728223b2c15e57d4e9f8afc944ad02a40c76
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+*
Memory test
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..8143aff1ea4481ade21acf41eba4c361096081a9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include
+#include
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h
new file mode 100644
index 0000000000000000000000000000000000000000..735e26dd4df8663a93b4f22ce5eb5cd712bc6653
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d0a61f07d193f41dc887b73052a3be9b1b5b78f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+*
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h
new file mode 100644
index 0000000000000000000000000000000000000000..cfa88870ecc7ae4425d6fd77b01b22c28191e748
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -0,0 +1,499 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0U
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xE0001000
+#define STDOUT_BASEADDRESS 0xE0001000
+
+/******************************************************************/
+
+/* Platform specific definitions */
+#define PLATFORM_ZYNQ
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
+/* Definitions for driver CANPS */
+#define XPAR_XCANPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_CAN_0 */
+#define XPAR_PS7_CAN_0_DEVICE_ID 0
+#define XPAR_PS7_CAN_0_BASEADDR 0xE0008000
+#define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF
+#define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CAN_0 */
+#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID
+#define XPAR_XCANPS_0_BASEADDR 0xE0008000
+#define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF
+#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_I2C_0 */
+#define XPAR_PS7_I2C_0_DEVICE_ID 0
+#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUTIMER */
+#define XPAR_XSCUTIMER_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_BUS_WIDTH 0
+#define XPAR_PS7_SD_0_MIO_BANK 0
+#define XPAR_PS7_SD_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xE0100000
+#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 0
+#define XPAR_XSDPS_0_MIO_BANK 0
+#define XPAR_XSDPS_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3U
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver USBPS */
+#define XPAR_XUSBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
+#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h
new file mode 100644
index 0000000000000000000000000000000000000000..0fa77710d14ea0476deb274aaa458285bfb8cf84
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h
@@ -0,0 +1,338 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..0582222bc9d6b07a08f87199fc8f7622c6c3f6cb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+*
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..45f091982497d96d757ce80559712dbd227905e6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+*
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
new file mode 100644
index 0000000000000000000000000000000000000000..4ad9e5d73cf6aa041462b24325df210f40a23bd4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..37971bc59d96983f89152b26e5bb97bdb58e62a5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h
new file mode 100644
index 0000000000000000000000000000000000000000..139ce4d3801b49f191a9b96ba36fa8f84a89f290
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h
@@ -0,0 +1,799 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_4
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Linear Mode
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..96c867ad3383fe4303731581d63f41db1ffb9231
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_4
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Disable Register
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc9a4ebd2c36ac3f03ad6816b05610129a6a7943
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h
new file mode 100644
index 0000000000000000000000000000000000000000..e22ee5bc283595250258993723a4d1b8aa28077b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h
@@ -0,0 +1,372 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_8
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..08e65f456e41dcb0ea23b58e7bd3387a22cc6155
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h
@@ -0,0 +1,650 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_8
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac7b42934796aa41e49adfc510057e951e0b2e0d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..372bbc3439aadbb94cf3fe04b97535757d4d1107
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2067d3a531870de0fe1851b65a2f653f58aa73f8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8d979d1d768214c5986d7899cbaa81ba5369c0d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+#ifdef __aarch64__
+ u64 Address; /**< Address of current dma transfer */
+#else
+ u32 Address; /**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
+ /**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c63d8f62afe518b28b3a3fadbeb820a323d9ee81
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h
@@ -0,0 +1,1301 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+*
+*
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * Normal and Error Interrupt Status Register
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * Normal and Error Interrupt Status Enable Register
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * Normal and Error Interrupt Signal Enable Register
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD0_ITAPDLYSEL_SD50 0x00000014U
+#define SD0_OTAPDLYSEL_SD50 0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD0_ITAPDLYSEL_HSD 0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
+#define SD1_ITAPDLYSEL_SD50 0x00140000U
+#define SD1_OTAPDLYSEL_SD50 0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
+#define SD1_ITAPDLYSEL_HSD 0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h
new file mode 100644
index 0000000000000000000000000000000000000000..993747588d94aa9364dfacd1f14cd5970331d66a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b872b6cb696a54594707facec1b228bd9facc42
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+*
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b7b4e1950d5ab0c6a73ab70616dd549f8143d078
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h
@@ -0,0 +1,467 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_5
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+* . At a regular, predefined period, that is on a timed interval
+* . When the counter registers overflow
+* . When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+* - Overflow Mode
+* - Internal clock (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of ttcps in xparameters.h
+* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
+*
+*
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H /* prevent circular inclusions */
+#define XTTCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
+ external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID for device */
+ u32 BaseAddress; /**< Base address for device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+ XTtcPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count and Match register value
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+typedef u16 XMatchRegValue;
+#else
+typedef u32 XInterval;
+typedef u32 XMatchRegValue;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+ (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+ (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance
+*
+* @return Non-zero if the device has started, '0' otherwise.
+*
+* @note C-style signature:
+* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+ ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Value is the 16-bit value to be set in the interval register.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value) \
+ InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be enabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be enabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
+ (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be disabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be disabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
+ ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be cleared.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be cleared, cleared bits
+* will not be cleared.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+ (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+ XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..b1fa545bda22600511bbb0c4560a3c6729ae4678
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h
@@ -0,0 +1,233 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+* mask 16 bit values for zynq and 32 bit values for
+* zynq ultrascale+mpsoc "
+*
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H /* prevent circular inclusions */
+#define XTTCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */
+#endif
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */
+#endif
+#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param MatchIndex is the 0-2 value of the match register
+*
+* @return MATCH_N_OFFSET.
+*
+* @note C-style signature:
+* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+ ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h
new file mode 100644
index 0000000000000000000000000000000000000000..33758c23b3733d2ffce9e1b8a27bfbdc22e0f4d1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..9a2bc430544035bcbde490106a1b9b1f2c4c09cd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h
@@ -0,0 +1,451 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+*
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b5c472ef9e3d912141993ac47da134013c9d3d06
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h
@@ -0,0 +1,1098 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_4
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ *
Introduction
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ *
USB Controller Features
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ * High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ * cost connections
+ *
+ *
Initialization & Configuration
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ * In this stage the basic parameters for the driver are configured,
+ * including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ * If DEVICE mode is desired, the endpoints of the controller need to be
+ * configured using the XUsbPs_DeviceConfig data structure. Once the
+ * endpoint configuration is set up in the data structure, The user then
+ * needs to allocate the required amount of DMAable memory and
+ * finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ * e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ * In the second stage the parameters for DEVICE are configured.
+ * The caller only needs to configure the modes that are
+ * actually used. Configuration is done with the:
+ * XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ * into these functions using the:
+ * XUsbPs_DeviceConfig data structures.
+ *
+ *
+ *
USB Device Endpoints
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ *
Interrupt Handling
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ * - General device interrupts
+ * - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ * XUsbPs_IntrSetHandler()
+ * and
+ * XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ *
Data buffer handling
+ *
+ * Data buffers are sent to and received from endpoint using the
+ * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ * XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ *
Zero copy
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ *
DMA
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
+ * Tabs for CR 657898
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1 kpc 04/28/14 Removed unused function prototypes
+ * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ * code coverage tests.
+ * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ * moving of dTD Head/Tail Pointers. Invalidate the cache
+ * after buffer receive in Endpoint Buffer Handler.
+ * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ * ms 03/17/17 Added readme.txt file in examples folder for doxygen
+ * generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ * XUSBPS_CMD_OFFSET) &
+ * XUSBPS_CMD_RST_MASK) && --Timeout) {
+ * ;
+ * }
+ * if (0 == Timeout) {
+ * return XST_FAILURE;
+ * }
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER 1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ * The direction is always defined from the perspective of the HOST! This
+ * means that an IN endpoint on the controller is used for sending data while
+ * the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH 0x400
+#define ENDPOINT_MAXP_MULT_MASK 0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT 10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
+ /**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX 0x02
+ /**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX 0x03
+ /**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE 1024
+ /**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param EpNum is the Number of the endpoint that caused the event.
+ * @param EventType is the type of the event that occured on the endpoint.
+ * @param Data is a pointer to user data pointer specified when callback
+ * was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+ u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param IrqMask is the Content of the interrupt status register. This
+ * value can be used by the callback function to distinguish the
+ * individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< Pointer to the first dTD of the dTD list for this
+ * endpoint. */
+
+ XUsbPs_dTD *dTDCurr;
+ /**< Buffer to the currently processed descriptor. */
+
+ u8 *dTDBufs;
+ /**< Pointer to the first buffer of the buffer list for this
+ * endpoint. */
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< List of pointers to the Transfer Descriptors of the
+ * endpoint. */
+
+ XUsbPs_dTD *dTDHead;
+ /**< Buffer to the next available descriptor in the list. */
+
+ XUsbPs_dTD *dTDTail;
+ /**< Buffer to the last unsent descriptor in the list*/
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+ /* Each endpoint has an OUT and an IN component.
+ */
+ XUsbPs_EpOut Out; /**< OUT endpoint structure */
+ XUsbPs_EpIn In; /**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+ u8 bmRequestType; /**< bmRequestType in setup data */
+ u8 bRequest; /**< bRequest in setup data */
+ u16 wValue; /**< wValue in setup data */
+ u16 wIndex; /**< wIndex in setup data */
+ u16 wLength; /**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+ u32 Type;
+ /**< Endpoint type:
+ - XUSBPS_EP_TYPE_CONTROL
+ - XUSBPS_EP_TYPE_ISOCHRONOUS
+ - XUSBPS_EP_TYPE_BULK
+ - XUSBPS_EP_TYPE_INTERRUPT */
+
+ u32 NumBufs;
+ /**< Number of buffers to be handled by this endpoint. */
+ u32 BufSize;
+ /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+ u16 MaxPacketSize;
+ /**< Maximum packet size for this endpoint. This number will
+ * define the maximum number of bytes sent on the wire per
+ * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+ XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
+ XUsbPs_EpSetup In; /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+ u8 NumEndpoints; /**< Number of Endpoints for the controller.
+ This number depends on the runtime
+ configuration of driver. The driver may
+ configure fewer endpoints than are available
+ in the core. */
+
+ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint configurations. */
+
+
+ u32 DMAMemPhys; /**< Physical base address of DMAable memory
+ allocated for the driver. */
+
+ /* The following members are used internally by the L0/L1 driver. They
+ * MUST NOT be accesses and/or modified in any way by the upper layers.
+ *
+ * The reason for having these members is that we generally try to
+ * avoid allocating memory in the L0/L1 driver as we want to be OS
+ * independent. In order to avoid allocating memory for this data
+ * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+ * structure which is allocated by the caller.
+ */
+ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint metadata structures. */
+
+ u32 PhysAligned; /**< 64 byte aligned base address of the DMA
+ memory block. Will be computed and set by
+ the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+ u16 DeviceID; /**< Unique ID of controller. */
+ u32 BaseAddress; /**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XUsbPs_Config Config; /**< Configuration structure */
+
+ int CurrentAltSetting; /**< Current alternative setting of interface */
+
+ void *UserDataPtr; /**< Data pointer to be used by upper layers to
+ store application dependent data structures.
+ The upper layers are responsible to allocated
+ and free the memory. The driver will not
+ mofidy this data pointer. */
+
+ /**
+ * The following structures hold the configuration for DEVICE mode
+ * of the controller. They are initialized using the
+ * XUsbPs_ConfigureDevice() function call.
+ */
+ XUsbPs_DeviceConfig DeviceConfig;
+ /**< Configuration for the DEVICE mode. */
+
+ XUsbPs_IntrHandlerFunc HandlerFunc;
+ /**< Handler function for the controller. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+ u32 HandlerMask;
+ /**< User interrupt mask. Defines which interrupts will cause
+ * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @return The current frame number.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note C-style signature:
+ * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) \
+{ \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK | \
+ XUSBPS_TIMER_RESET_MASK | \
+ XUSBPS_TIMER_REPEAT_MASK); \
+} \
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_CTL_OFFSET) & \
+ XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to enable.
+* @param Dir is direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to disable.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to stall.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the Number of the endpoint to unstall.
+* @param Dir is the Direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to flush.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
+ 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
+ XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+* enabled.
+* @note C-style signature:
+* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+* disabled.
+*
+* @note
+* C-style signature:
+* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note C-style signature:
+* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Threshold is the Interrupt threshold to be set.
+* Allowed values:
+* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* C-style signature:
+* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - TRUE: The tripwire bit is still set.
+* - FALSE: The tripwire bit has been cleared.
+*
+* @note C-style signature:
+* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
+ (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET) & \
+ XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits is the Bits to be set in the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits are the bits to be cleared in the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..1cb0cfcd3e755d485abb3837c546125ee65b4418
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDNLP_T_MASK 0x00000001
+ /**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
+ /**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * XUsbPs_dQHInvalidateCache()
+ * XUsbPs_dQHFlushCache()
+ * XUsbPs_dTDInvalidateCache()
+ * XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+ Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+ Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Len is the length to be set. Range: 0..16384
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr) \
+ (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+ & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param NLP is the Next Link Pointer
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_ADDR_MASK) | \
+ ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr) \
+ (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
+ & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
+ XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * - TRUE: The buffer is active.
+ * - FALSE: The buffer is not active.
+ *
+ * @note C-style signature:
+ * int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr) \
+ ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ * @param Val is the value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
+ (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ * Software must ensure that no interface data structure reachable by the
+ * Device Controller spans a 4K-page boundary. The first element of the
+ * Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
+ overlay */
+#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ * @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
+ /**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
+ /**< USB dQH Maximum Packet Length
+ * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT 16
+#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
+ /**< USB dQH Zero Length Termination
+ * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
+ /* USB dQH Number of Transactions Field
+ * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT 30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the length to be set.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ * @param Val is the Value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
+ (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..69f3ebffb4fef5b1f9ff7ad459509df87b94882c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING 4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK 0x80000000
+#define XUSBPS_TIMER_STOP_MASK 0x80000000
+#define XUSBPS_TIMER_RESET_MASK 0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
+
+#define XUSBPS_EP_NUM_MASK 0x3E
+#define XUSBPS_EP_NUM_SHIFT 1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n) \
+ (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
+ * this core. */
+#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
+ * registers */
+#define XUSBPS_EPCRn_OFFSET(n) \
+ (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define XUSBPS_EPFLUSH_RX_SHIFT 0
+#define XUSBPS_EPFLUSH_TX_SHIFT 16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ * @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
+#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ * @{
+ */
+#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ * @{
+ */
+#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
+ * Read Only */
+#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
+#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
+ * Read Only */
+#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
+ XUSBPS_IXR_UE_MASK | \
+ XUSBPS_IXR_PC_MASK | \
+ XUSBPS_IXR_FRE_MASK | \
+ XUSBPS_IXR_AA_MASK | \
+ XUSBPS_IXR_UR_MASK | \
+ XUSBPS_IXR_SR_MASK | \
+ XUSBPS_IXR_SLE_MASK | \
+ XUSBPS_IXR_ULPI_MASK | \
+ XUSBPS_IXR_HCH_MASK | \
+ XUSBPS_IXR_RCL_MASK | \
+ XUSBPS_IXR_PS_MASK | \
+ XUSBPS_IXR_AS_MASK | \
+ XUSBPS_IXR_NAK_MASK | \
+ XUSBPS_IXR_UA_MASK | \
+ XUSBPS_IXR_UP_MASK | \
+ XUSBPS_IXR_TI0_MASK | \
+ XUSBPS_IXR_TI1_MASK)
+ /**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ * @{
+ */
+#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
+#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK 0x00000010
+#define XUSBPS_MODE_VALID_MASK 0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ * @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
+ /**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
+ /**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
+ /**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX 127
+ /**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ * @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ * @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ * @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
+ /**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
+ /**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
+ /**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ * @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ * @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+ * Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+ * Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ * @{
+ */
+#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
+ * Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
+ * Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
+ * Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
+ * B Disconnect to A
+ * Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
+ * Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
+ * Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
+ XUSBPS_OTGSC_AVVIS_MASK | \
+ XUSBPS_OTGSC_ASVIS_MASK | \
+ XUSBPS_OTGSC_BSVIS_MASK | \
+ XUSBPS_OTGSC_BSEIS_MASK | \
+ XUSBPS_OTGSC_1MSS_MASK | \
+ XUSBPS_OTGSC_DPIS_MASK)
+ /** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
+ XUSBPS_OTGSC_AVVIE_MASK | \
+ XUSBPS_OTGSC_ASVIE_MASK | \
+ XUSBPS_OTGSC_BSVIE_MASK | \
+ XUSBPS_OTGSC_BSEE_IEB_MASK | \
+ XUSBPS_OTGSC_1MSE_MASK | \
+ XUSBPS_OTGSC_DPIE_MASK)
+ /** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN 2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN 64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN 32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE 4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN 4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddress is the base address for the USB registers.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddress is the the base address for the USB registers.
+* @param RegOffset is the register offset to be written.
+* @param Data is the the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c
new file mode 100644
index 0000000000000000000000000000000000000000..f852de4e6c218c59970696bbb2f35ec3f206f695
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c
@@ -0,0 +1,1205 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps.c
+* @addtogroup canps_v3_2
+* @{
+*
+* Functions in this file are the minimum required functions for the XCanPs
+* driver. See xcanps.h for a detailed description of the driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* XCanPs_GetTxIntrWatermark.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XCanPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XCanPs structure.
+* - Reset the CAN device. The CAN device will enter Configuration Mode
+* immediately after the reset is finished.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param ConfigPtr points to the XCanPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS always.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->IsReady = 0U;
+ InstancePtr->CanConfig.BaseAddr = EffectiveAddr;
+ InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Set all handlers to stub values, let user configure this data later.
+ */
+ InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler;
+ InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler;
+ InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler;
+ InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler;
+
+ /*
+ * Indicate the component is now ready to use.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Reset the device to get it into its initial state.
+ */
+ XCanPs_Reset(InstancePtr);
+
+ Status = XST_SUCCESS;
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the CAN device. Calling this function resets the device
+* immediately, and any pending transmission or reception is terminated at once.
+* Both Object Layer and Transfer Layer are reset. This function does not reset
+* the Physical Layer. All registers are reset to the default values, and no
+* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
+* Buffer are also reset.
+*
+* When a reset is required due to an internal error, the driver notifies the
+* upper layer software of this need through the error status code or interrupts.
+* The upper layer software is responsible for calling this Reset function and
+* then re-configuring the device.
+*
+* The CAN device will be in Configuration Mode immediately after this function
+* returns.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_Reset(XCanPs *InstancePtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \
+ XCANPS_SRR_SRST_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine returns the current operation mode of the CAN device.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - XCANPS_MODE_CONFIG if the device is in Configuration Mode.
+* - XCANPS_MODE_SLEEP if the device is in Sleep Mode.
+* - XCANPS_MODE_NORMAL if the device is in Normal Mode.
+* - XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode.
+* - XCANPS_MODE_SNOOP if the device is in Snoop Mode.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XCanPs_GetMode(XCanPs *InstancePtr)
+{
+ u32 StatusReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ StatusReg = XCanPs_GetStatus(InstancePtr);
+
+ if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) {
+ return (u8)XCANPS_MODE_CONFIG;
+
+ }
+ else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) {
+ return (u8)XCANPS_MODE_SLEEP;
+
+ }
+ else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) {
+ if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) {
+ return (u8)XCANPS_MODE_SNOOP;
+ } else {
+ return (u8)XCANPS_MODE_NORMAL;
+ }
+ }
+ else {
+ /*
+ * If this line is reached, the device is in Loop Back Mode.
+ */
+ return (u8)XCANPS_MODE_LOOPBACK;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This function allows the CAN device to enter one of the following operation
+* modes:
+* - Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG
+* - Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP
+* - Normal Mode: Pass in parameter XCANPS_MODE_NORMAL
+* - Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK.
+* - Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP.
+*
+* Read the xcanps.h file and device specification for detailed description of
+* each operation mode.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param OperationMode specify which operation mode to enter. Valid value
+* is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes
+* can not be entered at the same time.
+*
+* @return None.
+*
+* @note
+*
+* This function does NOT ensure CAN device enters the specified operation mode
+* before it returns the control to the caller. The caller is responsible for
+* checking current operation mode using XCanPs_GetMode().
+*
+******************************************************************************/
+void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode)
+{
+ u8 CurrentMode;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) ||
+ (OperationMode == (u8)XCANPS_MODE_SLEEP) ||
+ (OperationMode == (u8)XCANPS_MODE_NORMAL) ||
+ (OperationMode == (u8)XCANPS_MODE_LOOPBACK) ||
+ (OperationMode == (u8)XCANPS_MODE_SNOOP));
+
+ CurrentMode = XCanPs_GetMode(InstancePtr);
+
+ /*
+ * If current mode is Normal Mode and the mode to enter is Sleep Mode,
+ * or if current mode is Sleep Mode and the mode to enter is Normal
+ * Mode, no transition through Configuration Mode is needed.
+ */
+ if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) &&
+ (OperationMode == (u8)XCANPS_MODE_SLEEP)) {
+ /*
+ * Normal Mode ---> Sleep Mode
+ */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
+ return;
+
+ } else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) &&
+ (OperationMode == (u8)XCANPS_MODE_NORMAL)) {
+ /*
+ * Sleep Mode ---> Normal Mode
+ */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, 0U);
+ return;
+ }
+ else {
+ /*This else was made for misra-c compliance*/
+ ;
+ }
+
+ /*
+ * If the mode transition is not any of the two cases above, CAN must
+ * enter Configuration Mode before switching into the target operation
+ * mode.
+ */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SRR_OFFSET, 0U);
+
+ /*
+ * Check if the device has entered Configuration Mode, if not, return to
+ * the caller.
+ */
+ if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+ return;
+ }
+
+ switch (OperationMode) {
+ case XCANPS_MODE_CONFIG:
+ /*
+ * As CAN is in Configuration Mode already.
+ * Nothing is needed to be done here.
+ */
+ break;
+
+ case XCANPS_MODE_SLEEP:
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+ break;
+
+ case XCANPS_MODE_NORMAL:
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, 0U);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+ break;
+
+ case XCANPS_MODE_LOOPBACK:
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+ break;
+
+ case XCANPS_MODE_SNOOP:
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK);
+ break;
+
+ default:
+ /*This default was made for misra-c compliance*/
+ break;
+
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns Status value from Status Register (SR). Use the
+* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned
+* value.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The 32-bit value read from Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XCanPs_GetStatus(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_SR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads Receive and Transmit error counters.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param RxErrorCount is a pointer to data in which the Receive Error
+* counter value is returned.
+* @param TxErrorCount is a pointer to data in which the Transmit Error
+* counter value is returned.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
+ u8 *TxErrorCount)
+{
+ u32 ErrorCount;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(RxErrorCount != NULL);
+ Xil_AssertVoid(TxErrorCount != NULL);
+ /*
+ * Read Error Counter Register and parse it.
+ */
+ ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_ECR_OFFSET);
+ *RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >>
+ XCANPS_ECR_REC_SHIFT);
+ *TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads Error Status value from Error Status Register (ESR). Use
+* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the
+* returned value.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The 32-bit value read from Error Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_ESR_OFFSET);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears Error Status bit(s) previously set in Error
+* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h
+* to create the value to pass in. If a bit was cleared in Error Status Register
+* before this function is called, it will not be modified.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @param Mask is he 32-bit mask used to clear bits in Error Status
+* Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear
+* multiple bits.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_ESR_OFFSET, Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sends a CAN Frame. If the TX FIFO is not full then the given
+* frame is written into the the TX FIFO otherwise, it returns an error code
+* immediately.
+* This function does not wait for the given frame being sent to CAN bus.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FramePtr is a pointer to a 32-bit aligned buffer containing the
+* CAN frame to be sent.
+*
+* @return
+* - XST_SUCCESS if TX FIFO was not full and the given frame was
+* written into the FIFO.
+* - XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the
+* given frame.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FramePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) {
+ Status = XST_FIFO_NO_ROOM;
+ } else {
+
+ /*
+ * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+ */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXFIFO_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXFIFO_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function receives a CAN Frame. This function first checks if RX FIFO is
+* empty, if not, it then reads a frame from the RX FIFO into the given buffer.
+* This function returns error code immediately if there is no frame in the RX
+* FIFO.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN
+* frame to be written.
+*
+* @return
+* - XST_SUCCESS if RX FIFO was not empty and a frame was read from
+* RX FIFO successfully and written into the given buffer.
+* - XST_NO_DATA if there is no frame to be received from the FIFO.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FramePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) {
+ Status = XST_NO_DATA;
+ } else {
+
+ /*
+ * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device.
+ */
+ FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_RXFIFO_ID_OFFSET);
+ FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_RXFIFO_DLC_OFFSET);
+ FramePtr[2] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_RXFIFO_DW1_OFFSET));
+ FramePtr[3] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_RXFIFO_DW2_OFFSET));
+
+ /*
+ * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call
+ * returns correct RX FIFO occupancy/empty condition.
+ */
+ XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sends a CAN High Priority frame. This function first checks if
+* TX High Priority Buffer is empty. If yes, it then writes the given frame into
+* the Buffer. If not, this function returns immediately. This function does not
+* wait for the given frame being sent to CAN bus.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FramePtr is a pointer to a 32-bit aligned buffer containing the
+* CAN High Priority frame to be sent.
+*
+* @return
+* - XST_SUCCESS if TX High Priority Buffer was not full and the
+* given frame was written into the buffer.
+* - XST_FIFO_NO_ROOM if there is no room in the TX High Priority
+* Buffer for this frame.
+*
+* @note
+*
+* If the frame needs to be sent immediately and not delayed by processor's
+* interrupt handling, the caller should disable interrupt at processor
+* level before invoking this function.
+*
+******************************************************************************/
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FramePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) {
+ Status = XST_FIFO_NO_ROOM;
+ } else {
+
+ /*
+ * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device.
+ */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXHPB_ID_OFFSET, FramePtr[0]);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXHPB_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2]));
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_TXHPB_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3]));
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine enables individual acceptance filters. Up to 4 filters could
+* be enabled.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FilterIndexes specifies which filter(s) to enable. Use
+* any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or"
+* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
+* to be enabled. Any filter not specified in this parameter will
+* keep its previous enable/disable setting.
+*
+* @return None.
+*
+* @note None.
+*
+*
+******************************************************************************/
+void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes)
+{
+ u32 EnabledFilters;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Calculate the new value and write to AFR.
+ */
+ EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFR_OFFSET);
+ EnabledFilters |= FilterIndexes;
+ EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK;
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
+ EnabledFilters);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine disables individual acceptance filters. Up to 4 filters could
+* be disabled. If all acceptance filters are disabled then all the received
+* frames are stored in the RX FIFO.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FilterIndexes specifies which filter(s) to disable. Use
+* any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or"
+* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need
+* to be disabled. Any filter not specified in this parameter will
+* keep its previous enable/disable setting. If all acceptance
+* filters are disabled then all received frames are stored in the
+* RX FIFO.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes)
+{
+ u32 EnabledFilters;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Calculate the new value and write to AFR.
+ */
+ EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFR_OFFSET);
+ EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET,
+ EnabledFilters);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK
+* defined in xcanps_hw.h to interpret the returned value. If no acceptance
+* filters are enabled then all received frames are stored in the RX FIFO.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The value stored in Acceptance Filter Register.
+*
+* @note None.
+*
+*
+******************************************************************************/
+u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFR_OFFSET);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets values to the Acceptance Filter Mask Register (AFMR) and
+* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
+* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the
+* filter. Read the xcanps.h file and device specification for details.
+*
+* This function should be called only after:
+* - The given filter is disabled by calling XCanPs_AcceptFilterDisable()
+* - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
+* XCanPs_IsAcceptFilterBusy() returns FALSE.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FilterIndex defines which Acceptance Filter Mask and ID Register
+* to set. Use any single XCANPS_AFR_UAF*_MASK value.
+* @param MaskValue is the value to write to the chosen Acceptance Filter
+* Mask Register.
+* @param IdValue is the value to write to the chosen Acceptance Filter
+* ID Register.
+*
+* @return
+* - XST_SUCCESS if the values were set successfully.
+* - XST_FAILURE if the given filter was not disabled, or the CAN
+* device was not ready to accept writes to AFMR and AFIR.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 MaskValue, u32 IdValue)
+{
+ u32 EnabledFilters;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF3_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF2_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF1_MASK));
+
+ /*
+ * Return an error if the given filter is currently enabled.
+ */
+ EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr);
+ if ((EnabledFilters & FilterIndex) == FilterIndex) {
+ Status = XST_FAILURE;
+ } else {
+
+ /*
+ * If the CAN device is not ready to accept writes to AFMR and AFIR,
+ * return error code.
+ */
+ if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) {
+ Status = XST_FAILURE;
+ } else {
+
+ /*
+ * Write to the AFMR and AFIR of the specified filter.
+ */
+ switch (FilterIndex) {
+ case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */
+
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR1_OFFSET, MaskValue);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR1_OFFSET, IdValue);
+ break;
+
+ case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR2_OFFSET, MaskValue);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR2_OFFSET, IdValue);
+ break;
+
+ case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR3_OFFSET, MaskValue);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR3_OFFSET, IdValue);
+ break;
+
+ case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR4_OFFSET, MaskValue);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR4_OFFSET, IdValue);
+ break;
+
+ default:
+ /*This default was made for misra-c compliance*/
+ break;
+ }
+
+ Status = XST_SUCCESS;
+ }
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function reads the values of the Acceptance Filter Mask and ID Register
+* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h
+* to interpret the values. Read the xcanps.h file and device specification for
+* details.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param FilterIndex defines which Acceptance Filter Mask Register to get
+* Mask and ID from. Use any single XCANPS_FILTER_* value.
+* @param MaskValue is a pointer to the data in which the Mask value read
+* from the chosen Acceptance Filter Mask Register is returned.
+* @param IdValue is a pointer to the data in which the ID value read
+* from the chosen Acceptance Filter ID Register is returned.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 *MaskValue, u32 *IdValue)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF3_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF2_MASK) ||
+ (FilterIndex == XCANPS_AFR_UAF1_MASK));
+ Xil_AssertVoid(MaskValue != NULL);
+ Xil_AssertVoid(IdValue != NULL);
+
+ /*
+ * Read from the AFMR and AFIR of the specified filter.
+ */
+ switch (FilterIndex) {
+ case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */
+ *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR1_OFFSET);
+ *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR1_OFFSET);
+ break;
+
+ case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */
+ *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR2_OFFSET);
+ *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR2_OFFSET);
+ break;
+
+ case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */
+ *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR3_OFFSET);
+ *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR3_OFFSET);
+ break;
+
+ case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */
+ *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFMR4_OFFSET);
+ *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_AFIR4_OFFSET);
+ break;
+
+ default:
+ /*This default was made for misra-c compliance*/
+ break;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sets Baud Rate Prescaler value. The system clock for the CAN
+* controller is divided by (Prescaler + 1) to generate the quantum clock
+* needed for sampling and synchronization. Read the device specification
+* for details.
+*
+* Baud Rate Prescaler can be set only if the CAN device is in Configuration
+* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this
+* function.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Prescaler is the value to set. Valid values are from 0 to 255.
+*
+* @return
+* - XST_SUCCESS if the Baud Rate Prescaler value is set
+* successfully.
+* - XST_FAILURE if CAN device is not in Configuration Mode.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+ Status = XST_FAILURE;
+ } else {
+
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET,
+ (u32)Prescaler);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine gets Baud Rate Prescaler value. The system clock for the CAN
+* controller is divided by (Prescaler + 1) to generate the quantum clock
+* needed for sampling and synchronization. Read the device specification for
+* details.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return Current used Baud Rate Prescaler value. The value's range is
+* from 0 to 255.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr)
+{
+ u32 ReadValue;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_BRPR_OFFSET);
+ return ((u8)ReadValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine sets Bit time. Time segment 1, Time segment 2 and
+* Synchronization Jump Width are set in this function. Device specification
+* requires the values passed into this function be one less than the actual
+* values of these fields. Read the device specification for details.
+*
+* Bit time can be set only if the CAN device is in Configuration Mode.
+* Call XCanPs_EnterMode() to enter Configuration Mode before using this
+* function.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param SyncJumpWidth is the Synchronization Jump Width value to set.
+* Valid values are from 0 to 3.
+* @param TimeSegment2 is the Time Segment 2 value to set. Valid values
+* are from 0 to 7.
+* @param TimeSegment1 is the Time Segment 1 value to set. Valid values
+* are from 0 to 15.
+*
+* @return
+* - XST_SUCCESS if the Bit time is set successfully.
+* - XST_FAILURE if CAN device is not in Configuration Mode.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+ u8 TimeSegment2, u8 TimeSegment1)
+{
+ u32 Value;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U);
+ Xil_AssertNonvoid(TimeSegment2 <= (u8)7U);
+ Xil_AssertNonvoid(TimeSegment1 <= (u8)15U );
+
+ if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+ Status = XST_FAILURE;
+ } else {
+
+ Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK;
+ Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) &
+ XCANPS_BTR_TS2_MASK;
+ Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) &
+ XCANPS_BTR_SJW_MASK;
+
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_BTR_OFFSET, Value);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine gets Bit time. Time segment 1, Time segment 2 and
+* Synchronization Jump Width values are read in this function. According to
+* device specification, the actual value of each of these fields is one
+* more than the value read. Read the device specification for details.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param SyncJumpWidth will store the Synchronization Jump Width value
+* after this function returns. Its value ranges from 0 to 3.
+* @param TimeSegment2 will store the Time Segment 2 value after this
+* function returns. Its value ranges from 0 to 7.
+* @param TimeSegment1 will store the Time Segment 1 value after this
+* function returns. Its value ranges from 0 to 15.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
+ u8 *TimeSegment2, u8 *TimeSegment1)
+{
+ u32 Value;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(SyncJumpWidth != NULL);
+ Xil_AssertVoid(TimeSegment2 != NULL);
+ Xil_AssertVoid(TimeSegment1 != NULL);
+
+ Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_BTR_OFFSET);
+
+ *TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK);
+ *TimeSegment2 =
+ (u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT);
+ *SyncJumpWidth =
+ (u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine sets the Rx Full threshold in the Watermark Interrupt Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Threshold is the threshold to be set. The valid values are
+* from 1 to 63.
+*
+* @return
+* - XST_FAILURE - If the CAN device is not in Configuration Mode.
+* - XST_SUCCESS - If the Rx Full threshold is set in Watermark
+* Interrupt Register.
+*
+* @note The threshold can only be set when the CAN device is in the
+* configuration mode.
+*
+*****************************************************************************/
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+{
+
+ u32 ThrReg;
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Threshold <= (u8)63);
+
+ if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+ Status = XST_FAILURE;
+ } else {
+
+ ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET);
+
+ ThrReg &= XCANPS_WIR_EW_MASK;
+ ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET, ThrReg);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This routine gets the Rx Full threshold from the Watermark Interrupt Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The Rx FIFO full watermark threshold value. The valid values
+* are 1 to 63.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET) &
+ XCANPS_WIR_FW_MASK);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Threshold is the threshold to be set. The valid values are
+* from 1 to 63.
+*
+* @return
+* - XST_FAILURE - If the CAN device is not in Configuration Mode.
+* - XST_SUCCESS - If the threshold is set in Watermark
+* Interrupt Register.
+*
+* @note The threshold can only be set when the CAN device is in the
+* configuration mode.
+*
+*****************************************************************************/
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold)
+{
+ u32 ThrReg;
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Threshold <= (u8)63);
+
+ if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) {
+ Status = XST_FAILURE;
+ } else {
+
+ ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET);
+
+ ThrReg &= XCANPS_WIR_FW_MASK;
+ ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT)
+ & XCANPS_WIR_EW_MASK);
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET, ThrReg);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This routine gets the Tx Empty threshold from Watermark Interrupt Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The Tx Empty FIFO threshold value. The valid values are 1 to 63.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >>
+ XCANPS_WIR_EW_SHIFT);
+}
+
+
+
+/******************************************************************************/
+/*
+ * This routine is a stub for the asynchronous callbacks. The stub is here in
+ * case the upper layer forgot to set the handler(s). On initialization, all
+ * handlers are set to this callback. It is considered an error for this handler
+ * to be invoked.
+ *
+ ******************************************************************************/
+static void StubHandler(void)
+{
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9feb45eea12f5c634efd70ae448956054963f562
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h
@@ -0,0 +1,577 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps.h
+* @addtogroup canps_v3_2
+* @{
+* @details
+*
+* The Xilinx CAN driver component. This component supports the Xilinx
+* CAN Controller.
+*
+* The CAN Controller supports the following features:
+* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
+* - Supports both Standard (11 bit Identifier) and Extended (29 bit
+* Identifier) frames.
+* - Supports Bit Rates up to 1 Mbps.
+* - Transmit message object FIFO with a user configurable depth of
+* up to 64 message objects.
+* - Transmit prioritization through one TX High Priority Buffer.
+* - Receive message object FIFO with a user configurable depth of
+* up to 64 message objects.
+* - Watermark interrupts for Rx FIFO with configurable Watermark.
+* - Acceptance filtering with 4 acceptance filters.
+* - Sleep mode with automatic wake up.
+* - Loop Back mode for diagnostic applications.
+* - Snoop mode for diagnostic applications.
+* - Maskable Error and Status Interrupts.
+* - Readable Error Counters.
+* - External PHY chip required.
+* - Receive Timestamp.
+*
+* The device driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the CAN. The driver handles transmission and reception of
+* CAN frames, as well as configuration of the controller. The driver is simply a
+* pass-through mechanism between a protocol stack and the CAN. A single device
+* driver can support multiple CANs.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the CAN, no assembly or disassembly of CAN frames is done at the
+* driver-level. This assumes that the protocol stack passes a correctly
+* formatted CAN frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame
+*
+* Operation Modes
+*
+* The CAN controller supports the following modes of operation:
+* - Configuration Mode: In this mode the CAN timing parameters and
+* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
+* controller loses synchronization with the CAN bus and drives a
+* constant recessive bit on the bus line. The Error Counter Register are
+* reset. The CAN controller does not receive or transmit any messages
+* even if there are pending transmit requests from the TX FIFO or the TX
+* High Priority Buffer. The Storage FIFOs and the CAN configuration
+* registers are still accessible.
+* - Normal Mode:In Normal Mode the CAN controller participates in bus
+* communication, by transmitting and receiving messages.
+* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any
+* messages. However, if any other node transmits a message, then the CAN
+* Controller receives the transmitted message and exits from Sleep Mode.
+* If there are new transmission requests from either the TX FIFO or the
+* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
+* requests are not serviced, and the CAN Controller continues to remain
+* in Sleep Mode. Interrupts are generated when the CAN controller enters
+* Sleep mode or Wakes up from Sleep mode.
+* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a
+* recessive bit stream on to the CAN Bus. Any message that is transmitted
+* is looped back to the �Rx� line and acknowledged. The CAN controller
+* thus receives any message that it transmits. It does not participate in
+* normal bus communication and does not receive any messages that are
+* transmitted by other CAN nodes. This mode is used for diagnostic
+* purposes.
+* - Snoop Mode: In Snoop mode, the CAN controller transmits a
+* recessive bit stream on to the CAN Bus and does not participate
+* in normal bus communication but receives messages that are transmitted
+* by other CAN nodes. This mode is used for diagnostic purposes.
+*
+*
+* Buffer Alignment
+*
+* It is important to note that frame buffers passed to the driver must be
+* 32-bit aligned.
+*
+* Receive Address Filtering
+*
+* The device can be set to accept frames whose Identifiers match any of the
+* 4 filters set in the Acceptance Filter Mask/ID registers.
+*
+* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
+* Register. This value is compared with the result of masking the bits in the
+* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
+* both these values are equal, the message will be stored in the RX FIFO.
+*
+* Acceptance Filtering is performed by each of the defined acceptance filters.
+* If the incoming identifier passes through any acceptance filter then the
+* frame is stored in the RX FIFO.
+*
+* If the Accpetance Filters are not set up then all the received messages are
+* stroed in the RX FIFO.
+*
+* PHY Communication
+*
+* This driver does not provide any mechanism for directly programming PHY.
+*
+* Interrupts
+*
+* The driver has no dependencies on the interrupt controller. The driver
+* provides an interrupt handler. User of this driver needs to provide
+* callback functions. An interrupt handler example is available with
+* the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Device Reset
+*
+* Bus Off interrupt that can occur in the device requires a device reset.
+* The user is responsible for resetting the device and re-configuring it
+* based on its needs (the driver does not save the current configuration).
+* When integrating into an RTOS, these reset and re-configure obligations are
+* taken care of by the OS adapter software if it exists for that RTOS.
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xcanps_g.c files.
+* A table is defined where each entry contains configuration information
+* for a CAN device. This information includes such things as the base address
+* of the memory-mapped device.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XCanPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* XCanPs_GetTxIntrWatermark.
+* Updated the Register/bit definitions
+* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+* Changed XCANPS_IXR_RXFLL_MASK to
+* XCANPS_IXR_RXFWMFLL_MASK
+* Changed
+* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+* SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk 09/12/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.1 adk 10/11/15 Fixed CR#911958 Add support for Tx Watermark example.
+* Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+* error interrupts correctly. CR#925615
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XCANPS_H /* prevent circular inclusions */
+#define XCANPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xcanps_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name CAN operation modes
+ * @{
+ */
+#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */
+#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */
+#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */
+#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */
+#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */
+/* @} */
+
+/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
+ * @{
+ */
+#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
+#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
+#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */
+#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XCanPs_Config;
+
+/******************************************************************************/
+/**
+ * Callback type for frame sending and reception interrupts.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+ * Callback type for error interrupt.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ * @param ErrorMask is a bit mask indicating the cause of the error. Its
+ * value equals 'OR'ing one or more XCANPS_ESR_* values defined in
+ * xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/******************************************************************************/
+/**
+ * Callback type for all kinds of interrupts except sending frame interrupt,
+ * receiving frame interrupt, and error interrupt.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions, and passed back to the
+ * upper layer when the callback is invoked.
+ * @param Mask is a bit mask indicating the pending interrupts. Its value
+ * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
+*******************************************************************************/
+typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
+
+/**
+ * The XCanPs driver instance data. The user is required to allocate a
+ * variable of this type for every CAN device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XCanPs_Config CanConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ /**
+ * Callback and callback reference for TXOK interrupt.
+ */
+ XCanPs_SendRecvHandler SendHandler;
+ void *SendRef;
+
+ /**
+ * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
+ */
+ XCanPs_SendRecvHandler RecvHandler;
+ void *RecvRef;
+
+ /**
+ * Callback and callback reference for ERROR interrupt.
+ */
+ XCanPs_ErrorHandler ErrorHandler;
+ void *ErrorRef;
+
+ /**
+ * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
+ * Wakeup/Sleep/Bus off/ARBLST interrupts.
+ */
+ XCanPs_EventHandler EventHandler;
+ void *EventRef;
+
+} XCanPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission is complete.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the transmission is done.
+* - FALSE if the transmission is not done.
+*
+* @note C-Style signature:
+* int XCanPs_IsTxDone(XCanPs *InstancePtr)
+*
+*******************************************************************************/
+#define XCanPs_IsTxDone(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the transmission FIFO is full.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if TX FIFO is full.
+* - FALSE if the TX FIFO is NOT full.
+*
+* @note C-Style signature:
+* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsTxFifoFull(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the Transmission High Priority Buffer is full.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the TX High Priority Buffer is full.
+* - FALSE if the TX High Priority Buffer is NOT full.
+*
+* @note C-Style signature:
+* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the receive FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if RX FIFO is empty.
+* - FALSE if the RX FIFO is NOT empty.
+*
+* @note C-Style signature:
+* int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsRxEmpty(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the CAN device is ready for the driver to change
+* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
+* Registers (AFMR).
+*
+* AFIR and AFMR for a filter are changeable only after the filter is disabled
+* and this routine returns FALSE. The filter can be disabled using the
+* XCanPs_AcceptFilterDisable function.
+*
+* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - TRUE if the device is busy and NOT ready to accept writes to
+* AFIR and AFMR.
+* - FALSE if the device is ready to accept writes to AFIR and
+* AFMR.
+*
+* @note C-Style signature:
+* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_IsAcceptFilterBusy(InstancePtr) \
+ (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
+ XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates CAN message identifier value given identifier field
+* values.
+*
+* @param StandardId contains Standard Message ID value.
+* @param SubRemoteTransReq contains Substitute Remote Transmission
+* Request value.
+* @param IdExtension contains Identifier Extension value.
+* @param ExtendedId contains Extended Message ID value.
+* @param RemoteTransReq contains Remote Transmission Request value.
+*
+* @return Message Identifier value.
+*
+* @note C-Style signature:
+* u32 XCanPs_CreateIdValue(u32 StandardId,
+* u32 SubRemoteTransReq,
+* u32 IdExtension, u32 ExtendedId,
+* u32 RemoteTransReq)
+*
+* Read the CAN specification for meaning of each parameter.
+*
+*****************************************************************************/
+#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
+ ExtendedId, RemoteTransReq) \
+ ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \
+ (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
+ (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \
+ (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \
+ ((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
+
+
+/****************************************************************************/
+/**
+*
+* This macro calculates value for Data Length Code register given Data
+* Length Code value.
+*
+* @param DataLengCode indicates Data Length Code value.
+*
+* @return Value that can be assigned to Data Length Code register.
+*
+* @note C-Style signature:
+* u32 XCanPs_CreateDlcValue(u32 DataLengCode)
+*
+* Read the CAN specification for meaning of Data Length Code.
+*
+*****************************************************************************/
+#define XCanPs_CreateDlcValue(DataLengCode) \
+ (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the timestamp in the Timestamp Control Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
+*
+*****************************************************************************/
+#define XCanPs_ClearTimestamp(InstancePtr) \
+ XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \
+ XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xcanps.c
+ */
+s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+void XCanPs_Reset(XCanPs *InstancePtr);
+u8 XCanPs_GetMode(XCanPs *InstancePtr);
+void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
+u32 XCanPs_GetStatus(XCanPs *InstancePtr);
+void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
+ u8 *TxErrorCount);
+u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
+void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
+s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
+s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
+void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
+void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
+u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
+s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 MaskValue, u32 IdValue);
+void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
+ u32 *MaskValue, u32 *IdValue);
+
+s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
+u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
+s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
+ u8 TimeSegment2, u8 TimeSegment1);
+void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
+ u8 *TimeSegment2, u8 *TimeSegment1);
+
+s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
+s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
+u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
+
+/*
+ * Diagnostic functions in xcanps_selftest.c
+ */
+s32 XCanPs_SelfTest(XCanPs *InstancePtr);
+
+/*
+ * Functions in xcanps_intr.c
+ */
+void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
+u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
+u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
+void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
+void XCanPs_IntrHandler(void *InstancePtr);
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+ void *CallBackFunc, void *CallBackRef);
+
+/*
+ * Functions in xcanps_sinit.c
+ */
+XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..bd2b1970814908357b7bbd0e5e4e17add032a5d0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xcanps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_CAN_0_DEVICE_ID,
+ XPAR_PS7_CAN_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..7ca2f81ebaef522c86307d6ed53bf4a4454ae5be
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_hw.c
+* @addtogroup canps_v3_2
+* @{
+*
+* This file contains the implementation of the canps interface reset sequence
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk 08/08/13 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function resets the CAN device. Calling this function resets the device
+* immediately, and any pending transmission or reception is terminated at once.
+* Both Object Layer and Transfer Layer are reset. This function does not reset
+* the Physical Layer. All registers are reset to the default values, and no
+* previous status will be restored. TX FIFO, RX FIFO and TX High Priority
+* Buffer are also reset.
+*
+* The CAN device will be in Configuration Mode immediately after this function
+* returns.
+*
+* @param BaseAddr is the baseaddress of the interface.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_ResetHw(u32 BaseAddr)
+{
+ XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
+ XCANPS_SRR_SRST_MASK);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..30ec68ab9729312706bb2d9833949250b385f9d9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_hw.h
+* @addtogroup canps_v3_2
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xcanps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 1.01a sbs 12/27/11 Updated the Register/bit definitions
+* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+* Changed XCANPS_IXR_RXFLL_MASK to
+* XCANPS_IXR_RXFWMFLL_MASK
+* Changed
+* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk 08/08/13 Updated for inclding the function prototype
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+#ifndef XCANPS_HW_H /* prevent circular inclusions */
+#define XCANPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the CAN. Each register is 32 bits.
+ * @{
+ */
+#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */
+#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */
+#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */
+#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */
+#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */
+#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */
+#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */
+
+#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */
+#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */
+#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */
+#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */
+#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */
+
+#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */
+#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */
+#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */
+#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */
+
+#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */
+#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */
+#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */
+#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */
+
+#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */
+#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */
+#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */
+#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */
+
+#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */
+#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */
+#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */
+#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */
+#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */
+#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */
+#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */
+#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */
+#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */
+/* @} */
+
+/** @name Software Reset Register (SRR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */
+#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */
+/* @} */
+
+/** @name Mode Select Register (MSR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */
+#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */
+#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */
+/* @} */
+
+/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */
+/* @} */
+
+/** @name Bit Timing Register (BTR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */
+#define XCANPS_BTR_SJW_SHIFT 7U
+#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */
+#define XCANPS_BTR_TS2_SHIFT 4U
+#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */
+/* @} */
+
+/** @name Error Counter Register (ECR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */
+#define XCANPS_ECR_REC_SHIFT 8U
+#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */
+/* @} */
+
+/** @name Error Status Register (ESR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */
+#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */
+#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */
+#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */
+#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */
+/* @} */
+
+/** @name Status Register (SR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */
+#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */
+#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */
+#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */
+#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */
+#define XCANPS_SR_ESTAT_SHIFT 7U
+#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */
+#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */
+#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */
+#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */
+#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */
+#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */
+#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */
+/* @} */
+
+/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */
+#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
+#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
+#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */
+#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */
+#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */
+#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */
+#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */
+#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */
+#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */
+#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */
+#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */
+#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */
+#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */
+#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */
+#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \
+ (u32)XCANPS_IXR_WKUP_MASK | \
+ (u32)XCANPS_IXR_SLP_MASK | \
+ (u32)XCANPS_IXR_BSOFF_MASK | \
+ (u32)XCANPS_IXR_ERROR_MASK | \
+ (u32)XCANPS_IXR_RXNEMP_MASK | \
+ (u32)XCANPS_IXR_RXOFLW_MASK | \
+ (u32)XCANPS_IXR_RXUFLW_MASK | \
+ (u32)XCANPS_IXR_RXOK_MASK | \
+ (u32)XCANPS_IXR_TXBFLL_MASK | \
+ (u32)XCANPS_IXR_TXFLL_MASK | \
+ (u32)XCANPS_IXR_TXOK_MASK | \
+ (u32)XCANPS_IXR_ARBLST_MASK)
+/* @} */
+
+/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */
+/* @} */
+
+/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */
+#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */
+#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */
+
+/* @} */
+
+/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
+ Mask/Acceptance Filter ID)
+ * @{
+ */
+#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */
+#define XCANPS_IDR_ID1_SHIFT 21U
+#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */
+#define XCANPS_IDR_SRR_SHIFT 20U
+#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */
+#define XCANPS_IDR_IDE_SHIFT 19U
+#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */
+#define XCANPS_IDR_ID2_SHIFT 1U
+#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */
+/* @} */
+
+/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */
+#define XCANPS_DLCR_DLC_SHIFT 28U
+#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */
+
+/* @} */
+
+/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */
+#define XCANPS_DW1R_DB0_SHIFT 24U
+#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */
+#define XCANPS_DW1R_DB1_SHIFT 16U
+#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */
+#define XCANPS_DW1R_DB2_SHIFT 8U
+#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */
+/* @} */
+
+/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
+ * @{
+ */
+#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */
+#define XCANPS_DW2R_DB4_SHIFT 24U
+#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */
+#define XCANPS_DW2R_DB5_SHIFT 16U
+#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */
+#define XCANPS_DW2R_DB6_SHIFT 8U
+#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */
+/* @} */
+
+/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
+ * @{
+ */
+#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */
+#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */
+#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */
+#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */
+#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \
+ (u32)XCANPS_AFR_UAF3_MASK | \
+ (u32)XCANPS_AFR_UAF2_MASK | \
+ (u32)XCANPS_AFR_UAF1_MASK)
+/* @} */
+
+/** @name CAN frame length constants
+ * @{
+ */
+#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
+/* @} */
+
+/* For backwards compatibilty */
+#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET
+#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET
+#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET
+#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET
+
+#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
+#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET
+#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK
+
+
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XCanPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the CanPs interface
+ */
+void XCanPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..715b35eb25c65257a3b4892ef819227aa6fbbb28
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c
@@ -0,0 +1,421 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_intr.c
+* @addtogroup canps_v3_2
+* @{
+*
+* This file contains functions related to CAN interrupt handling.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler to handle error
+* interrupts correctly. CR#925615
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+*
+* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in
+* xcanps_hw.h to create the bit-mask to enable interrupts.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Mask is the mask to enable. Bit positions of 1 will be enabled.
+* Bit positions of 0 will keep the previous setting. This mask is
+* formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask)
+{
+ u32 IntrValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the IER to enable the specified interrupts.
+ */
+ IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
+ IntrValue |= Mask;
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_IER_OFFSET, IntrValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in
+* xcanps_hw.h to create the bit-mask to disable interrupt(s).
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Mask is the mask to disable. Bit positions of 1 will be
+* disabled. Bit positions of 0 will keep the previous setting.
+* This mask is formed by OR'ing XCANPS_IXR_* bits defined in
+* xcanps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask)
+{
+ u32 IntrValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the IER to disable the specified interrupts.
+ */
+ IntrValue = XCanPs_IntrGetEnabled(InstancePtr);
+ IntrValue &= ~Mask;
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_IER_OFFSET, IntrValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants
+* defined in xcanps_hw.h to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return Enabled interrupt(s) in a 32-bit format.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_IER_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This routine returns interrupt status read from Interrupt Status Register.
+* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the
+* returned value.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return The value stored in Interrupt Status Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr,
+ XCANPS_ISR_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param Mask is the mask to clear. Bit positions of 1 will be cleared.
+* Bit positions of 0 will not change the previous interrupt
+* status. This mask is formed by OR'ing XCANPS_IXR_* bits defined
+* in xcanps_hw.h.
+*
+* @note None.
+*
+*****************************************************************************/
+void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask)
+{
+ u32 IntrValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Clear the currently pending interrupts.
+ */
+ IntrValue = XCanPs_IntrGetStatus(InstancePtr);
+ IntrValue &= Mask;
+ XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET,
+ IntrValue);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is the interrupt handler for the CAN driver.
+*
+* This handler reads the interrupt status from the ISR, determines the source of
+* the interrupts, calls according callbacks, and finally clears the interrupts.
+*
+* Application beyond this driver is responsible for providing callbacks to
+* handle interrupts and installing the callbacks using XCanPs_SetHandler()
+* during initialization phase. An example delivered with this driver
+* demonstrates how this could be done.
+*
+* @param InstancePtr is a pointer to the XCanPs instance that just
+* interrupted.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCanPs_IntrHandler(void *InstancePtr)
+{
+ u32 PendingIntr;
+ u32 EventIntr;
+ u32 ErrorStatus;
+ XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr);
+
+ Xil_AssertVoid(CanPtr != NULL);
+ Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ PendingIntr = XCanPs_IntrGetStatus(CanPtr);
+ PendingIntr &= XCanPs_IntrGetEnabled(CanPtr);
+
+ /*
+ * Clear all pending interrupts.
+ * Rising Edge interrupt
+ */
+ XCanPs_IntrClear(CanPtr, PendingIntr);
+
+ /*
+ * An error interrupt is occurring.
+ */
+ if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
+ (CanPtr->ErrorHandler != NULL)) {
+ ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
+ CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus);
+ /*
+ * Clear Error Status Register.
+ */
+ XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus);
+ }
+
+ /*
+ * Check if any following event interrupt is pending:
+ * - RX FIFO Overflow
+ * - RX FIFO Underflow
+ * - TX High Priority Buffer full
+ * - TX FIFO Full
+ * - Wake up from sleep mode
+ * - Enter sleep mode
+ * - Enter Bus off status
+ * - Arbitration is lost
+ *
+ * If so, call event callback provided by upper level.
+ */
+ EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
+ (u32)XCANPS_IXR_RXUFLW_MASK |
+ (u32)XCANPS_IXR_TXBFLL_MASK |
+ (u32)XCANPS_IXR_TXFLL_MASK |
+ (u32)XCANPS_IXR_WKUP_MASK |
+ (u32)XCANPS_IXR_SLP_MASK |
+ (u32)XCANPS_IXR_BSOFF_MASK |
+ (u32)XCANPS_IXR_ARBLST_MASK);
+ if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
+ CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
+
+ if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
+ /*
+ * Event callback should reset whole device if "Enter
+ * Bus Off Status" interrupt occurred. All pending
+ * interrupts are cleared and no further checking and
+ * handling of other interrupts is needed any more.
+ */
+ return;
+ } else {
+ /*This else was made for misra-c compliance*/
+ ;
+ }
+ }
+
+
+ if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
+ XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
+ (CanPtr->RecvHandler != NULL)) {
+
+ /*
+ * This case happens when
+ * A number of frames depending on the Rx FIFO Watermark
+ * threshold are received.
+ * And also when frame was received and is sitting in RX FIFO.
+ *
+ * XCANPS_IXR_RXOK_MASK is not used because the bit is set
+ * just once even if there are multiple frames sitting
+ * in the RX FIFO.
+ *
+ * XCANPS_IXR_RXNEMP_MASK is used because the bit can be
+ * set again and again automatically as long as there is
+ * at least one frame in RX FIFO.
+ */
+ CanPtr->RecvHandler(CanPtr->RecvRef);
+ }
+
+ /*
+ * A frame was transmitted successfully.
+ */
+ if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) &&
+ (CanPtr->SendHandler != NULL)) {
+ CanPtr->SendHandler(CanPtr->SendRef);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This routine installs an asynchronous callback function for the given
+* HandlerType:
+*
+*
+* HandlerType Callback Function Type
+* ----------------------- ------------------------
+* XCANPS_HANDLER_SEND XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT XCanPs_EventHandler
+*
+* HandlerType Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND A frame transmitted by a call to
+* XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV A frame(s) has been received and is sitting in
+* the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT Any other kind of interrupt is occurring.
+*
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+* @param HandlerType specifies which handler is to be attached.
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return
+* - XST_SUCCESS when handler is installed.
+* - XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note
+* Invoking this function for a handler that already has been installed replaces
+* it with the new handler.
+*
+******************************************************************************/
+s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
+ void *CallBackFunc, void *CallBackRef)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ switch (HandlerType) {
+ case XCANPS_HANDLER_SEND:
+ InstancePtr->SendHandler =
+ (XCanPs_SendRecvHandler) CallBackFunc;
+ InstancePtr->SendRef = CallBackRef;
+ Status = XST_SUCCESS;
+ break;
+
+ case XCANPS_HANDLER_RECV:
+ InstancePtr->RecvHandler =
+ (XCanPs_SendRecvHandler) CallBackFunc;
+ InstancePtr->RecvRef = CallBackRef;
+ Status = XST_SUCCESS;
+ break;
+
+ case XCANPS_HANDLER_ERROR:
+ InstancePtr->ErrorHandler =
+ (XCanPs_ErrorHandler) CallBackFunc;
+ InstancePtr->ErrorRef = CallBackRef;
+ Status = XST_SUCCESS;
+ break;
+
+ case XCANPS_HANDLER_EVENT:
+ InstancePtr->EventHandler =
+ (XCanPs_EventHandler) CallBackFunc;
+ InstancePtr->EventRef = CallBackRef;
+ Status = XST_SUCCESS;
+ break;
+
+ default:
+ Status = XST_INVALID_PARAM;
+ break;
+ }
+ return Status;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..26c9fcb68101e47bcc3049b271f96573dc009931
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c
@@ -0,0 +1,234 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_selftest.c
+* @addtogroup canps_v3_2
+* @{
+*
+* This file contains a diagnostic self-test function for the XCanPs driver.
+*
+* Read xcanps.h file for more information.
+*
+* @note
+* The Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR)
+* are setup such that CAN baud rate equals 40Kbps, given the CAN clock
+* equal to 24MHz. These need to be changed based on the desired baudrate
+* and CAN clock frequency.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 2.1 adk 23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+* SDK claims a 40kbps baud rate but it's not.
+* 3.00 kvn 02/13/15 Modified code for MISRA_C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xcanps.h"
+
+/************************** Constant Definitions ****************************/
+
+#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32)))
+
+#define FRAME_DATA_LENGTH 8U /* Frame Data field length */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/*
+ * Buffers to hold frames to send and receive. These are declared as global so
+ * that they are not on the stack.
+ */
+static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
+static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS];
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the CAN driver/device. The test resets
+* the device, sets up the Loop Back mode, sends a standard frame, receives the
+* frame, verifies the contents, and resets the device again.
+*
+* Note that this is a destructive test in that resets of the device are
+* performed. Refer the device specification for the device status after
+* the reset operation.
+*
+*
+* @param InstancePtr is a pointer to the XCanPs instance.
+*
+* @return
+* - XST_SUCCESS if the self-test passed. i.e., the frame
+* received via the internal loop back has the same contents as
+* the frame sent.
+* - XST_FAILURE Otherwise.
+*
+* @note
+*
+* If the CAN device does not work properly, this function may enter an
+* infinite loop and will never return to the caller.
+*
+* If XST_FAILURE is returned, the device is not reset so that the caller could
+* have a chance to check reason(s) causing the failure.
+*
+******************************************************************************/
+s32 XCanPs_SelfTest(XCanPs *InstancePtr)
+{
+ u8 *FramePtr;
+ s32 Status;
+ u32 Index;
+ u8 GetModeResult;
+ u32 RxEmptyResult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XCanPs_Reset(InstancePtr);
+
+ /*
+ * The device should enter Configuration Mode immediately after
+ * reset above is finished. Now check the mode and return error code if
+ * it is not Configuration Mode.
+ */
+ if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /*
+ * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register
+ * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock
+ * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B,
+ * ISO 11898-1 specifications.
+ */
+ (void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U);
+ (void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U);
+
+ /*
+ * Enter the loop back mode.
+ */
+ XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK);
+ GetModeResult = XCanPs_GetMode(InstancePtr);
+ while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) {
+ GetModeResult = XCanPs_GetMode(InstancePtr);
+ }
+
+ /*
+ * Create a frame to send with known values so we can verify them
+ * on receive.
+ */
+ TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U);
+ TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U);
+
+ FramePtr = (u8 *)((void *)(&TxFrame[2]));
+ for (Index = 0U; Index < 8U; Index++) {
+ if(*FramePtr != 0U) {
+ *FramePtr = (u8)Index;
+ FramePtr++;
+ }
+ }
+
+ /*
+ * Send the frame.
+ */
+ Status = XCanPs_Send(InstancePtr, TxFrame);
+ if (Status != (s32)XST_SUCCESS) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /*
+ * Wait until the frame arrives RX FIFO via internal loop back.
+ */
+ RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+
+ while (RxEmptyResult == (u32)0U) {
+ RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr),
+ XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK;
+ }
+
+ /*
+ * Receive the frame.
+ */
+ Status = XCanPs_Recv(InstancePtr, RxFrame);
+ if (Status != (s32)XST_SUCCESS) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /*
+ * Verify Identifier and Data Length Code.
+ */
+ if (RxFrame[0] !=
+ (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+
+ for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) {
+ if (RxFrame[Index] != TxFrame[Index]) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+ }
+
+ /*
+ * Reset device again before returning to the caller.
+ */
+ XCanPs_Reset(InstancePtr);
+
+ Status = XST_SUCCESS;
+ return Status;
+}
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..5321669d77b422acf2fa11d7e87da63813e070be
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcanps_sinit.c
+* @addtogroup canps_v3_2
+* @{
+*
+* This file contains the implementation of the XCanPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00a xd/sv 01/12/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xcanps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XCanPs_ConfigTable[] contains the configuration information for
+* each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId)
+{
+ XCanPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) {
+ if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XCanPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XCanPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
new file mode 100644
index 0000000000000000000000000000000000000000..fca26ca2ec803781230884079bac6c232222947b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -0,0 +1,188 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_4
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.2 kvn 10/09/15 Add support for IAR Compiler.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include
+#include
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+* @param Data is the byte of data to send
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+ (void) BaseAddress;
+ while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+ dsb();
+#ifdef __aarch64__
+ asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mcr p14, 0, %0, c0, c5, 0"
+ : : "r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Reg = Data;
+ }
+#endif
+ isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+*
+* @return The byte of data received.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+ u8 Data = 0U;
+ (void) BaseAddress;
+
+ while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+ dsb();
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c5, 0"
+ : "=r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Data = Reg;
+ }
+#endif
+ isb();
+
+ return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+ u32 Status = 0U;
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c1, 0"
+ : "=r" (Status) : : "cc");
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+ Status = Reg;
+ }
+#endif
+ return Status;
+#endif
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..67959e3274632a6ca7b5bd3225679cc0c3e1f10f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..95c8ba5360707e6032e28cfc4847ee9df969fd1c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_5
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+******************************************************************************/
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
new file mode 100644
index 0000000000000000000000000000000000000000..c8804d2ed33d87cd0d678d73a63bb0ddedee86f1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
new file mode 100644
index 0000000000000000000000000000000000000000..e9447e7e32f37a6d684164bd18db3087068aec2f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
@@ -0,0 +1,945 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XDcfg
+* driver. Refer to the header file xdevcfg.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Updated the XDcfg_Transfer function to use the
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize the Device Config Interface driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note The very first APB access to the Device Configuration Interface
+* block needs to be a write to the UNLOCK register with the value
+* of 0x757BDF0D. This step is to be done once after reset, any
+* other APB access has to come after this. The APB access is
+* considered illegal if the step is not done or if it is done
+* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
+* the following additional actions would be carried out.
+* In other words, if all bits are low, the following steps are not
+* done.
+* 1. AES is disabled
+* 2. All APB writes disabled
+* 3. SoC debug fully enabled
+*
+******************************************************************************/
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0;
+
+
+ /* Unlock the Device Configuration Interface */
+ XDcfg_Unlock(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* The functions enables the PCAP interface by setting the PCAP mode bit in the
+* control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note Enable FPGA programming from PCAP interface. Enabling this bit
+* disables all the external interfaces from programming of FPGA
+* except for ICAP. The user needs to ensure that the FPGA is
+* programmed through either PCAP or ICAP.
+*
+*****************************************************************************/
+void XDcfg_EnablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The functions disables the PCAP interface by clearing the PCAP mode bit in
+* the control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_DisablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit mask data to be written to the Register.
+* The mask definitions are defined in the xdevcfg_hw.h file.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function Clears the specified bit positions of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit value which holds the bit positions to be cleared.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Control
+* Register.
+* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Lock Register. These bits
+* can only be set to a 1. They will be cleared after a Power On Reset.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Lock Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Lock
+* Register.
+* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Lock Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Config
+* Register.
+* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Status
+* Register.
+* Use the XDCFG_STATUS_*_MASK constants defined in
+* xdevcfg_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Status Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the ROM Shadow Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note This register is can only be written and is used to control the
+* RAM shadow of 32 bit 4K page ROM pages in user mode
+*
+*****************************************************************************/
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
+ Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Software ID Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API for reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Software ID Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the bit mask for the feature in Miscellaneous Control
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the feature to be set.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
+ (RegData | Mask));
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API to reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
+}
+
+/******************************************************************************/
+/**
+*
+* This function checks if DMA command queue is full.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return XST_SUCCESS is the DMA is busy
+* XST_FAILURE if the DMA is idle
+*
+* @note The DMA queue has a depth of two.
+*
+****************************************************************************/
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
+{
+
+ u32 RegData;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the PCAP status register for DMA status */
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET);
+
+ if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK){
+ return XST_SUCCESS;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function initiates the DMA transfer.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return None.
+*
+* @note It is the responsibility of the caller function to ensure that
+* correct values are passed to this function.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+****************************************************************************/
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength)
+{
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_ADDR_OFFSET,
+ SourcePtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_ADDR_OFFSET,
+ DestPtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_LEN_OFFSET,
+ SrcWordLength);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_LEN_OFFSET,
+ DestWordLength);
+}
+
+/******************************************************************************/
+/**
+*
+* This function Implements the DMA Read Command. This command is used to
+* transfer the image data from FPGA to the external memory.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return - XST_INVALID_PARAM if source address/length is invalid.
+* - XST_SUCCESS if DMA transfer initiated properly.
+*
+* @note None.
+*
+****************************************************************************/
+static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
+ u32 SrcWordLength, u32 DestPtr,
+ u32 DestWordLength)
+{
+ u32 IntrReg;
+
+ /*
+ * Send READ Frame command to FPGA
+ */
+ XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
+ SrcWordLength, 0);
+
+ /*
+ * Store the enabled interrupts to enable before the actual read
+ * transfer is initiated and Disable all the interrupts temporarily.
+ */
+ IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
+ XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
+
+ /*
+ * Wait till you get the DMA done for the read command sent
+ */
+ while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET) &
+ XDCFG_IXR_D_P_DONE_MASK) !=
+ XDCFG_IXR_D_P_DONE_MASK);
+ /*
+ * Enable the previously stored Interrupts .
+ */
+ XDcfg_IntrEnable(InstancePtr, IntrReg);
+
+ /*
+ * Initiate the DMA write command.
+ */
+ XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
+ 0, DestWordLength);
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function starts the DMA transfer. This function only starts the
+* operation and returns before the operation may be completed.
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is completed, otherwise it is necessary to poll the Status register
+* to determine when it is completed. It is the responsibility of the caller to
+* determine when the operation is completed by handling the generated interrupt
+* or polling the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+* @param TransferType contains the type of PCAP transfer being requested.
+* The definitions can be found in the xdevcfg.h file.
+* @return
+* - XST_SUCCESS.if DMA transfer initiated successfully
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_INVALID_PARAM if invalid Source / Destination address
+* is sent or an invalid Source / Destination length is
+* sent
+*
+* @note It is the responsibility of the caller to ensure that the cache
+* is flushed and invalidated both before the DMA operation is
+* started and after the DMA operation completes if the memory
+* pointed to is cached. The caller must also ensure that the
+* pointers contain physical address rather than a virtual address
+* if address translation is being used.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+*****************************************************************************/
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType)
+{
+
+ u32 CtrlReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Check whether the fabric is in initialized state
+ */
+ if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
+ & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
+ /*
+ * We don't need to check PCFG_INIT to be high for
+ * non-encrypted loopback transfers.
+ */
+ if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ return XST_FAILURE;
+ }
+ }
+
+ if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
+ (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
+
+ /* Check for valid source pointer and length */
+ if ((!SourcePtr) || (SrcWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
+ /*
+ * AES engine handles only 8 bit data every clock cycle.
+ * Hence, Encrypted PCAP data which is 32 bit data can
+ * only be sent in every 4 clock cycles. Set the control
+ * register QUARTER_PCAP_RATE_EN bit to achieve this
+ * operation.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+
+ }
+
+ if (TransferType == XDCFG_PCAP_READBACK) {
+
+ if ((!DestPtr) || (DestWordLength == 0)) {
+
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * For PCAP readback of FPGA configuration register or memory,
+ * the read command is first sent (written) to the FPGA fabric
+ * which responds by returning the required read data. Read data
+ * from the FPGA is captured if pcap_radata_v is active.A DMA
+ * read transfer is required to obtain the readback command,
+ * which is then sent to the FPGA, followed by a DMA write
+ * transfer to support this mode of operation.
+ */
+ return XDcfg_PcapReadback(InstancePtr,
+ (u32)SourcePtr, SrcWordLength,
+ (u32)DestPtr, DestWordLength);
+ }
+
+
+ if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
+ (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
+
+ if ((!SourcePtr) || (SrcWordLength == 0) ||
+ (!DestPtr) || (DestWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ /* Enable internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg |
+ XDCFG_MCTRL_PCAP_LPBK_MASK));
+
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * Set the QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every 4 clock
+ * cycles, this is required for encrypted data.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+ }
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..b9a0111d695aeb71f09195025549f3df8283d9fb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
@@ -0,0 +1,403 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..e96911d51705032b94bf4c80d6204657d9d0fac9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdevcfg.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDcfg_Config XDcfg_ConfigTable[] =
+{
+ {
+ XPAR_PS7_DEV_CFG_0_DEVICE_ID,
+ XPAR_PS7_DEV_CFG_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..bcb238f062cfddb05cca741e27512f6ec1f37d58
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given devcfg interface by
+* configuring the appropriate control bits in the devcfg specifc registers
+* the devcfg reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status
+* Update relevant config registers with reset values
+* Disbale the looopback mode and pcap rate enable
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* devcfg controller
+******************************************************************************/
+void XDcfg_ResetHw(u32 BaseAddr)
+{
+ u32 Regval = 0;
+
+ /* Mask the interrupts */
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
+ XDCFG_IXR_ALL_MASK);
+ /* Clear the interuupt status */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
+ /* Clear the source address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
+ /* Clear the destination address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
+ /* Clear the source length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
+ /* Clear the destination length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
+ /* Clear the loopback enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
+ Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
+ /*Reset the configuration register to reset value */
+ XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
+ XDCFG_CONFIG_RESET_VALUE);
+ /*Disable the PCAP rate enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
+ Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c506ca59fc936b96086d96b074f85bee0959c104
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
@@ -0,0 +1,395 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..b41b7ea370b596df0e0af5b38c865f3d81a48c90
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
@@ -0,0 +1,310 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains the implementation of interrupt related functions of the XDcfg
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the IMR.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Mask Register.
+ */
+ return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Interrupt
+* Status register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET,
+ Mask);
+
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the Device Config Interface.
+*
+* Events are signaled to upper layer for proper handling.
+*
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XDcfg_InterruptHandler(XDcfg *InstancePtr)
+{
+ u32 IntrStatusReg;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so that no
+ * subsequent interrupts are missed while processing this interrupt.
+ * This also does the DMA acknowledgment automatically.
+ */
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET, IntrStatusReg);
+
+ /*
+ * Signal application that there are events to handle.
+ */
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ IntrStatusReg);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XDcfg instance
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallBackFunc != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..40cf1de6abc45a9b9601651ccea7e3d9e2c6168a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains diagnostic self-test functions for the XDcfg driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm 02/27/13 Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the Device Configuration Interface. This test does a
+* control register write and reads back the same value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if fails.
+*
+* @note None.
+*
+******************************************************************************/
+int XDcfg_SelfTest(XDcfg *InstancePtr)
+{
+ u32 OldCfgReg;
+ u32 CfgReg;
+ int Status = XST_SUCCESS;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
+
+ CfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the original values of the register
+ */
+ XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
+
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..bbc96a0c6bd98d5b331cf330da84e08b18d47b3c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5 ms 08/07/17 Fixed compilation warnings.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
+{
+ extern XDcfg_Config XDcfg_ConfigTable[];
+ XDcfg_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+ if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDcfg_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (CfgPtr);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
new file mode 100644
index 0000000000000000000000000000000000000000..9db769284bdd6c4ac26be76d5eda1b758bdecece
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
@@ -0,0 +1,1982 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.c
+* @addtogroup dmaps_v2_3
+* @{
+*
+* This file contains the implementation of the interface functions for XDmaPs
+* driver. Refer to the header file xdmaps.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/2010 First Release
+* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
+* since it is being defined in xil_io.h
+* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include
+
+#include "xstatus.h"
+#include "xdmaps.h"
+#include "xil_io.h"
+#include "xil_cache.h"
+
+#include "xil_printf.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread);
+
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
+
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
+
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength);
+
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
+
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XDmaPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstPtr is a pointer to the XDmaPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XDmaPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, pass in
+* the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS on initialization completion
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr)
+{
+ int Status = XST_SUCCESS;
+ unsigned int CacheLength = 0;
+ u32 CfgReg;
+ unsigned Channel;
+ XDmaPs_ChannelData *ChanData;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /*
+ * Setup the driver instance using passed in parameters
+ */
+ InstPtr->Config.DeviceId = Config->DeviceId;
+ InstPtr->Config.BaseAddress = EffectiveAddr;
+
+ CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
+ CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
+ if (CacheLength < 2 || CacheLength > 5)
+ CacheLength = 0;
+ else
+ CacheLength = 1 << CacheLength;
+
+ InstPtr->CacheLength = CacheLength;
+
+ memset(InstPtr->Chans, 0,
+ sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
+
+ for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
+ ChanData = InstPtr->Chans + Channel;
+ ChanData->ChanId = Channel;
+ ChanData->DevId = Config->DeviceId;
+ }
+
+ InstPtr->IsReady = 1;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the DMA Manager.
+*
+* @param InstPtr is the DMA instance.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetManager(XDmaPs *InstPtr)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ 0, 0);
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the specified DMA Channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel to be reset.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ Channel, 1);
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver fault interrupt service routine
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_FaultISR(XDmaPs *InstPtr)
+{
+
+ void *DmaProgBuf;
+ u32 Fsm; /* Fault status DMA manager register value */
+ u32 Fsc; /* Fault status DMA channel register value */
+ u32 FaultType; /* Fault type DMA manager register value */
+
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+
+ u32 Pc; /* DMA Pc or channel Pc */
+ XDmaPs_ChannelData *ChanData;
+
+ unsigned Chan;
+ unsigned DevId;
+
+ XDmaPs_Cmd *DmaCmd;
+
+ Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
+ Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
+
+
+ DevId = InstPtr->Config.DeviceId;
+
+ if (Fsm) {
+ /*
+ * if DMA manager is fault
+ */
+ FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
+ Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
+
+ xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
+ DevId,
+ FaultType, Pc);
+
+ /* kill the DMA manager thread */
+ /* Should we disable interrupt?*/
+ XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
+ }
+
+ /*
+ * check which channel faults and kill the channel thread
+ */
+ for (Chan = 0;
+ Chan < XDMAPS_CHANNELS_PER_DEV;
+ Chan++) {
+ if (Fsc & (0x01 << Chan)) {
+ FaultType =
+ XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_FTCn_OFFSET(Chan));
+ Pc = XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CPCn_OFFSET(Chan));
+
+ /* kill the channel thread */
+ /* Should we disable interrupt? */
+ XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
+
+ /*
+ * get the fault type and fault Pc and invoke the
+ * fault callback.
+ */
+ ChanData = InstPtr->Chans + Chan;
+
+ DmaCmd = ChanData->DmaCmdToHw;
+
+ /* Should we check DmaCmd is not null */
+ DmaCmd->DmaStatus = -1;
+ DmaCmd->ChanFaultType = FaultType;
+ DmaCmd->ChanFaultPCAddr = Pc;
+ ChanData->DmaCmdFromHw = DmaCmd;
+ ChanData->DmaCmdToHw = NULL;
+
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ if (InstPtr->FaultHandler)
+ InstPtr->FaultHandler(Chan,
+ DmaCmd,
+ InstPtr->FaultRef);
+
+ }
+ }
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the done handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel number.
+* @param DoneHandler is the done interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef)
+{
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ if (Channel >= XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+
+ ChanData = InstPtr->Chans + Channel;
+
+ ChanData->DoneHandler = DoneHandler;
+ ChanData->DoneRef = CallbackRef;
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the fault handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param FaultHandler is the fault interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ InstPtr->FaultHandler = FaultHandler;
+ InstPtr->FaultRef = CallbackRef;
+
+ return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+* Construction function for DMAEND instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for
+* the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
+{
+ /*
+ * DMAEND encoding:
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 0 0 0
+ */
+ *DmaProg = 0x0;
+
+ return 1;
+}
+
+static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
+{
+ *Dst = *Src;
+ *(Dst + 1) = *(Src + 1);
+ *(Dst + 2) = *(Src + 2);
+ *(Dst + 3) = *(Src + 3);
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAGO instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Cn is the Channel number, 0 - 7
+* @param Imm is 32-bit immediate number written to the Channel Program
+* Counter.
+* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
+* the Non-secure state. If Ns is 0, the execution depends on the
+* security state of the DMA manager:
+* DMA manager is in the Secure state, DMA channel operates in the
+* Secure state.
+* DMA manager is in the Non-secure state, DMAC aborts.
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns)
+{
+ /*
+ * DMAGO encoding:
+ * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+ * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ */
+ *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
+
+ *(DmaProg + 1) = (u8)(Cn & 0x07);
+
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ /* success */
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALD instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for the
+* instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
+{
+ /*
+ * DMALD encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 1 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x04;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALP instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Lc is the Loop counter register, can either be 0 or 1.
+* @param LoopIterations: the number of interations, LoopInterations - 1
+* will be encoded in the DMALP instruction.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations)
+{
+ /*
+ * DMALP encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | iter[7:0] |0 0 1 0 0 0 lc 0
+ */
+ *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
+ *(DmaProg + 1) = (u8)(LoopIterations - 1);
+ return 2;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALPEND instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param BodyStart is the starting address of the loop body. It is used
+* to calculate the bytes of backward jump.
+* @param Lc is the Loop counter register, can either be 0 or 1.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
+{
+ /*
+ * DMALPEND encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
+ *
+ * lc: loop counter
+ * nf is for loop forever. The driver does not support loop forever,
+ * so nf is 1.
+ * The driver does not support conditional LPEND, so bs is 0, x is 0.
+ */
+ *DmaProg = 0x38 | ((Lc & 1) << 2);
+ *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
+
+ return 2;
+}
+
+/*
+ * Register number for the DMAMOV instruction
+ */
+#define XDMAPS_MOV_SAR 0x0
+#define XDMAPS_MOV_CCR 0x1
+#define XDMAPS_MOV_DAR 0x2
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAMOV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
+* @param Imm is the 32-bit immediate number
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
+{
+ /*
+ * DMAMOV encoding
+ * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ *
+ * rd: b000 for SAR, b001 CCR, b010 DAR
+ */
+ *DmaProg = 0xBC;
+ *(DmaProg + 1) = Rd & 0x7;
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMANOP instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
+{
+ /*
+ * DMANOP encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 1 0 0 0
+ */
+ *DmaProg = 0x18;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMARMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
+{
+ /*
+ * DMARMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x12;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMASEV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param EventNumber is the Event number to signal.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
+{
+ /*
+ * DMASEV encoding
+ * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
+ * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
+ */
+ *DmaProg = 0x34;
+ *(DmaProg + 1) = (u8)(EventNumber << 3);
+
+ return 2;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAST instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
+{
+ /*
+ * DMAST encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 1 0 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x08;
+ return 1;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAWMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
+{
+ /*
+ * DMAWMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x13;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the endian swap size to the bit encoding of the CCR
+*
+* @param EndianSwapSize is the endian swap size, in terms of bits, it
+* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
+*
+* @return The endian swap size bit encoding for the CCR.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
+{
+ switch (EndianSwapSize) {
+ case 0:
+ case 8:
+ return 0;
+ case 16:
+ return 1;
+ case 32:
+ return 2;
+ case 64:
+ return 3;
+ case 128:
+ return 4;
+ default:
+ return 0;
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the burst size to the bit encoding of the CCR
+*
+* @param BurstSize is the burst size. It's the data width.
+* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
+* It must be no larger than the bus width.
+* (We are using DMA assembly syntax.)
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
+{
+ switch (BurstSize) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ return 2;
+ case 8:
+ return 3;
+ case 16:
+ return 4;
+ case 32:
+ return 5;
+ case 64:
+ return 6;
+ case 128:
+ return 7;
+ default:
+ return 0;
+ }
+}
+
+
+/****************************************************************************/
+/**
+*
+* Conversion function from PL330 bus transfer descriptors to CCR value. All the
+* values passed to the functions are in terms of assembly languages, not in
+* terms of the register bit encoding.
+*
+* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
+*
+* @return The 32-bit CCR value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
+{
+ /*
+ * Channel Control Register encoding
+ * [31:28] - endian_swap_size
+ * [27:25] - dst_cache_ctrl
+ * [24:22] - dst_prot_ctrl
+ * [21:18] - dst_burst_len
+ * [17:15] - dst_burst_size
+ * [14] - dst_inc
+ * [13:11] - src_cache_ctrl
+ * [10:8] - src_prot_ctrl
+ * [7:4] - src_burst_len
+ * [3:1] - src_burst_size
+ * [0] - src_inc
+ */
+
+ unsigned es =
+ XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
+
+ unsigned dst_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
+ unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
+ unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
+ | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
+ unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
+ unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
+
+ unsigned src_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
+ unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
+ unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
+ | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
+ unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
+ unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
+
+ u32 ccr_value = (es << 28)
+ | (dst_cache_ctrl << 25)
+ | (dst_prot_ctrl << 22)
+ | (dst_burst_len << 18)
+ | (dst_burst_size << 15)
+ | (dst_inc_bit << 14)
+ | (src_cache_ctrl << 11)
+ | (src_prot_ctrl << 8)
+ | (src_burst_len << 4)
+ | (src_burst_size << 1)
+ | (src_inc_bit);
+
+ return ccr_value;
+}
+
+/****************************************************************************/
+/**
+* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
+* The function also makes sure the loop body and the lpend is in the same
+* cache line.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCount The inner loop count. Loop count - 1 will be used to
+* initialize the loop counter.
+*
+* @return The number of bytes the loop has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ int LoopCount)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 3;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/****************************************************************************/
+/**
+* Construct a nested loop with only DMALD and DMAST in the inner loop body.
+* It uses loop counter 1 for the outer loop and loop counter 0 for the
+* inner loop.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCountOuter The outer loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+* @param LoopCountInner The inner loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+*
+* @return The number byes the nested loop program has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ unsigned int LoopCountOuter,
+ unsigned int LoopCountInner)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *InnerLoopStart;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
+ InnerLoopStart = DmaProgBuf;
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ if (CacheLength < 8) {
+ /*
+ * if the cache line is too small to fit both loops
+ * just align the inner loop
+ */
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCountInner);
+ /* outer loop end */
+ DmaProgBuf +=
+ XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart,
+ 1);
+
+ /*
+ * the nested loop is constructed for
+ * smaller cache line
+ */
+ return DmaProgBuf - DmaProgLoopStart;
+ }
+
+ /*
+ * Now let's handle the case where a cache line can
+ * fit the nested loops.
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 7;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ /* insert the inner DMALP */
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
+
+ /* DMALD and DMAST instructions */
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+
+ /* inner DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+ /* outer DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart, 1);
+
+ /* return the number of bytes */
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/*
+ * [31:28] endian_swap_size b0000
+ * [27:25] dst_cache_ctrl b000
+ * [24:22] dst_prot_ctrl b000
+ * [21:18] dst_burst_len b0000
+ * [17:15] dst_burst_size b000
+ * [14] dst_inc b0
+ * [27:25] src_cache_ctrl b000
+ * [24:22] src_prot_ctrl b000
+ * [21:18] src_burst_len b0000
+ * [17:15] src_burst_size b000
+ * [14] src_inc b0
+ */
+#define XDMAPS_CCR_SINGLE_BYTE (0x0)
+#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
+
+
+/****************************************************************************/
+/**
+*
+* Construct the DMA program based on the descriptions of the DMA transfer.
+* The function handles memory to memory DMA transfers.
+* It also handles unalgined head and small amount of residue tail.
+*
+* @param Channel DMA channel number
+* @param Cmd is the DMA command.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+*
+* @returns The number of bytes for the program.
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength)
+{
+ /*
+ * unpack arguments
+ */
+ char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
+ unsigned DevChan = Channel;
+ unsigned long DmaLength = Cmd->BD.Length;
+ u32 SrcAddr = Cmd->BD.SrcAddr;
+
+ unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
+ u32 DstAddr = Cmd->BD.DstAddr;
+ unsigned DstInc = Cmd->ChanCtrl.DstInc;
+
+ char *DmaProgStart = DmaProgBuf;
+
+ unsigned int BurstBytes;
+ unsigned int LoopCount;
+ unsigned int LoopCount1 = 0;
+ unsigned int LoopResidue = 0;
+ unsigned int TailBytes;
+ unsigned int TailWords;
+ int DmaProgBytes;
+ u32 CCRValue;
+ unsigned int Unaligned;
+ unsigned int UnalignedCount;
+ unsigned int MemBurstSize = 1;
+ u32 MemAddr = 0;
+ unsigned int Index;
+ unsigned int SrcUnaligned = 0;
+ unsigned int DstUnaligned = 0;
+
+ XDmaPs_ChanCtrl *ChanCtrl;
+ XDmaPs_ChanCtrl WordChanCtrl;
+ static XDmaPs_ChanCtrl Mem2MemByteCC;
+
+ Mem2MemByteCC.EndianSwapSize = 0;
+ Mem2MemByteCC.DstCacheCtrl = 0;
+ Mem2MemByteCC.DstProtCtrl = 0;
+ Mem2MemByteCC.DstBurstLen = 1;
+ Mem2MemByteCC.DstBurstSize = 1;
+ Mem2MemByteCC.DstInc = 1;
+ Mem2MemByteCC.SrcCacheCtrl = 0;
+ Mem2MemByteCC.SrcProtCtrl = 0;
+ Mem2MemByteCC.SrcBurstLen = 1;
+ Mem2MemByteCC.SrcBurstSize = 1;
+ Mem2MemByteCC.SrcInc = 1;
+
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ /* insert DMAMOV for SAR and DAR */
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_SAR,
+ SrcAddr);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_DAR,
+ DstAddr);
+
+
+ if (ChanCtrl->SrcInc)
+ SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
+
+ if (ChanCtrl->DstInc)
+ DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
+
+ if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
+ ChanCtrl = &Mem2MemByteCC;
+ }
+
+ if (ChanCtrl->SrcInc) {
+ MemBurstSize = ChanCtrl->SrcBurstSize;
+ MemAddr = SrcAddr;
+
+ } else if (ChanCtrl->DstInc) {
+ MemBurstSize = ChanCtrl->DstBurstSize;
+ MemAddr = DstAddr;
+ }
+
+ /* check whether the head is aligned or not */
+ Unaligned = MemAddr % MemBurstSize;
+
+ if (Unaligned) {
+ /* if head is unaligned, transfer head in bytes */
+ UnalignedCount = MemBurstSize - Unaligned;
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ for (Index = 0; Index < UnalignedCount; Index++) {
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ }
+
+ DmaLength -= UnalignedCount;
+ }
+
+ /* now the burst transfer part */
+ CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
+
+ LoopCount = DmaLength / BurstBytes;
+ TailBytes = DmaLength % BurstBytes;
+
+ /*
+ * the loop count register is 8-bit wide, so if we need
+ * a larger loop, we need to have nested loops
+ */
+ if (LoopCount > 256) {
+ LoopCount1 = LoopCount / 256;
+ if (LoopCount1 > 256) {
+ xil_printf("DMA operation cannot fit in a 2-level "
+ "loop for channel %d, please reduce the "
+ "DMA length or increase the burst size or "
+ "length",
+ Channel);
+ return 0;
+ }
+ LoopResidue = LoopCount % 256;
+
+ if (LoopCount1 > 1)
+ DmaProgBuf +=
+ XDmaPs_ConstructNestedLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount1,
+ 256);
+ else
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ 256);
+
+ /* there will be some that cannot be covered by
+ * nested loops
+ */
+ LoopCount = LoopResidue;
+ }
+
+ if (LoopCount > 0) {
+ DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount);
+ }
+
+ if (TailBytes) {
+ /* handle the tail */
+ TailWords = TailBytes / MemBurstSize;
+ TailBytes = TailBytes % MemBurstSize;
+
+ if (TailWords) {
+ WordChanCtrl = *ChanCtrl;
+ /*
+ * if we can transfer the tail in words, we will
+ * transfer words as much as possible
+ */
+ WordChanCtrl.SrcBurstSize = MemBurstSize;
+ WordChanCtrl.SrcBurstLen = 1;
+ WordChanCtrl.DstBurstSize = MemBurstSize;
+ WordChanCtrl.DstBurstLen = 1;
+
+
+ /*
+ * the burst length is 1
+ */
+ CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailWords);
+
+ }
+
+ if (TailBytes) {
+ /*
+ * for the rest, we'll tranfer in bytes
+ */
+ /*
+ * So far just to be safe, the tail bytes
+ * are transfered in a loop. We can optimize a little
+ * to perform a burst.
+ */
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailBytes);
+
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
+ DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
+
+ DmaProgBytes = DmaProgBuf - DmaProgStart;
+
+ Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
+
+ return DmaProgBytes;
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* Generate a DMA program based for the DMA command, the buffer will be pointed
+* by the GeneratedDmaProg field of the command.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+*
+* @return - XST_SUCCESS on success.
+* - XST_FAILURE if it fails
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+ void *Buf;
+ int ProgLen;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_ChanCtrl *ChanCtrl;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ ChanData = InstPtr->Chans + Channel;
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
+ != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * unaligned fixed address is not supported
+ */
+ if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
+ return XST_FAILURE;
+ }
+
+ if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
+ return XST_FAILURE;
+ }
+
+ Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
+ if (Buf == NULL) {
+ return XST_FAILURE;
+ }
+
+ Cmd->GeneratedDmaProg = Buf;
+ ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
+ InstPtr->CacheLength);
+ Cmd->GeneratedDmaProgLength = ProgLen;
+
+
+#ifdef XDMAPS_DEBUG
+ XDmaPs_Print_DmaProg(Cmd);
+#endif
+
+ if (ProgLen <= 0) {
+ /* something wrong, release the buffer */
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProgLength = 0;
+ Cmd->GeneratedDmaProg = NULL;
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+ * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
+ * of the command.
+ *
+ * @param InstPtr is then DMA instance.
+ * @param Channel is the DMA channel number.
+ * @param Cmd is the DMA command.
+ *
+ * @return XST_SUCCESS on success.
+ * XST_FAILURE if there is any error.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+
+ void *Buf;
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ Buf = (void *)Cmd->GeneratedDmaProg;
+ ChanData = InstPtr->Chans + Channel;
+
+ if (Buf) {
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProg = 0;
+ Cmd->GeneratedDmaProgLength = 0;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Start a DMA command. The command can only be invoked when the channel
+* is idle. The driver takes the command, generates DMA program if needed,
+* then pass the program to DMAC to execute.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+* @param HoldDmaProg is tag indicating whether the driver can release
+* the allocated DMA buffer or not. If a user wants to examine the
+* generated DMA program, the flag should be set to 1. After the
+* DMA program is finished, a user needs to explicity free the
+* buffer.
+*
+* @return
+* - XST_SUCCESS on success
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_FAILURE on other failures
+*
+* @note None.
+*
+****************************************************************************/
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg)
+{
+ int Status;
+ u32 DmaProg = 0;
+ u32 Inten;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ Cmd->DmaStatus = XST_FAILURE;
+
+ if (XDmaPs_IsActive(InstPtr, Channel))
+ return XST_DEVICE_BUSY;
+
+ if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
+ Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
+ if (Status)
+ return XST_FAILURE;
+ }
+
+ InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
+
+ if (Cmd->UserDmaProg)
+ DmaProg = (u32)Cmd->UserDmaProg;
+ else if (Cmd->GeneratedDmaProg)
+ DmaProg = (u32)Cmd->GeneratedDmaProg;
+
+ if (DmaProg) {
+ /* enable the interrupt */
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+ Inten |= 0x01 << Channel; /* set the correpsonding bit */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET,
+ Inten);
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+
+ InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
+
+ if (Cmd->ChanCtrl.SrcInc) {
+ Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
+ }
+ if (Cmd->ChanCtrl.DstInc) {
+ Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
+ Cmd->BD.Length);
+ }
+
+ Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
+ Channel, DmaProg);
+ }
+ else {
+ InstPtr->Chans[Channel].DmaCmdToHw = NULL;
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Checks whether the DMA channel is active or idle.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel number.
+*
+* @return 0: if the channel is idle
+* 1: otherwise
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ /* Need to assert Channel is in range */
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return 0;
+
+ return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Allocate a buffer of the DMA program buffer from the pool.
+*
+* @param Pool the DMA program pool.
+*
+* @return The allocated buffer, NULL if there is any error.
+*
+* @note None.
+*
+*****************************************************************************/
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
+{
+ int Index;
+
+ Xil_AssertNonvoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (!Pool[Index].Allocated) {
+ Pool[Index].Allocated = 1;
+ return Pool[Index].Buf;
+ }
+ }
+
+ return NULL;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 0. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 1. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 2. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 2);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 3. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 3);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 4. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 4);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 5. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 5);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 6. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 6);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 7. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 7);
+}
+
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+
+/****************************************************************************/
+/**
+* Use the debug registers to kill the DMA thread.
+*
+* @param BaseAddr is DMA device base address.
+* @param Channel is the DMA channel number.
+* @param Thread is Debug thread encoding.
+* 0: DMA manager thread, 1: DMA channel.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread)
+{
+ u32 DbgInst0;
+ int WaitCount;
+
+ DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ /* wait time out */
+ xil_printf("PL330 device at %x debug status busy time out\n",
+ BaseAddr);
+
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
+
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+/****************************************************************************/
+/**
+*
+*
+* Free a buffer of the DMA program buffer.
+* @param Pool the DMA program pool.
+* @param Buf the DMA program buffer to be release.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
+{
+ int Index;
+ Xil_AssertVoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (Pool[Index].Buf == Buf) {
+ if (Pool[Index].Allocated) {
+ Pool[Index].Allocated = 0;
+ }
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
+*
+* @param BaseAddr PL330 device base address
+* @param Channel Channel number for the device
+* @param DmaProg DMA program starting address, this should be DMA address
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+****************************************************************************/
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
+{
+ char DmaGoProg[8];
+ u32 DbgInst0;
+ u32 DbgInst1;
+
+ int WaitCount;
+
+ XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
+
+ DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
+ DbgInst1 = (u32)DmaProg;
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT)) {
+
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+ /* write debug instruction 1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
+
+
+ /* wait while the DMA Manager is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr,
+ XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
+ != XDMAPS_DS_DMA_STATUS_STOPPED
+ && WaitCount <= XDMAPS_MAX_WAIT) {
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+
+/****************************************************************************/
+/**
+*
+* It's the generic Done ISR.
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel numer.
+*
+* @return None.*
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
+{
+
+ void *DmaProgBuf;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_Cmd *DmaCmd;
+ //u32 Value;
+
+ ChanData = InstPtr->Chans + Channel;
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+ /* clear the interrupt status */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTCLR_OFFSET,
+ 1 << ChanData->ChanId);
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+
+ DmaCmd = ChanData->DmaCmdToHw;
+ if (DmaCmd) {
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ DmaCmd->DmaStatus = 0;
+ ChanData->DmaCmdToHw = NULL;
+ ChanData->DmaCmdFromHw = DmaCmd;
+
+ if (ChanData->DoneHandler)
+ ChanData->DoneHandler(Channel, DmaCmd,
+ ChanData->DoneRef);
+ }
+
+}
+
+
+/****************************************************************************/
+/**
+* Prints the content of the buffer in bytes
+* @param Buf is the buffer.
+* @param Length is the length of the DMA program.
+*
+* @return None.
+*
+* @note None.
+****************************************************************************/
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
+{
+ int Index;
+ for (Index = 0; Index < Length; Index++)
+ xil_printf("[%x] %x\r\n", Index, Buf[Index]);
+
+}
+/****************************************************************************/
+/**
+* Print the Dma Prog Contents.
+*
+* @param Cmd is the command buffer.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+ void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
+{
+ if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
+ xil_printf("Generated DMA program (%d):\r\n",
+ Cmd->GeneratedDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
+ Cmd->GeneratedDmaProgLength);
+ }
+
+ if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
+ xil_printf("User defined DMA program (%d):\r\n",
+ Cmd->UserDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
+ Cmd->UserDmaProgLength);
+ }
+}
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a0c1a28e3d1a6a35a13ffe728420c260da05f5b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_3
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..bab15561fba384acd5a50947b19fb91643dfab0f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
@@ -0,0 +1,59 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_DMA_NS_DEVICE_ID,
+ XPAR_PS7_DMA_NS_BASEADDR
+ },
+ {
+ XPAR_PS7_DMA_S_DEVICE_ID,
+ XPAR_PS7_DMA_S_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..4c0cfbfd216fa02e31d004cd2bd5e8e593c3a618
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_3
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* for XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given dmaps interface by
+* configuring the appropriate control bits in the dmaps specifc registers
+* the dmaps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the pending interrupts
+* Kill all the active channel threads
+* Kill the manager thread
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* dmaps controller
+******************************************************************************/
+void XDmaPs_ResetHw(u32 BaseAddress)
+{
+ u32 DbgInst;
+ u32 WaitCount = 0;
+ u32 ChanIndex;
+
+ /* Disable all the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
+ /* Clear the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
+ /* Kill the dma channel threads */
+ for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+ while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+ }
+ /* Kill the manager thread */
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+}
+
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..628f1ec4f92b9a685afcb900029ac9d3d41c89fa
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_3
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..daebd9903f1d438672b0354b46fac2a3ad827134
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_3
+* @{
+*
+* This file contains the self-test functions for the XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 hbm 03/29/2010 First Release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstPtr is a pointer to the XDmaPs instance
+*
+* @return
+*
+* - XST_SUCCESS if the test was successful
+* - XST_FAILURE if the test failed
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XDmaPs_SelfTest(XDmaPs *InstPtr)
+{
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+ int i;
+
+ if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ return XST_FAILURE;
+
+ for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
+ if (XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CSn_OFFSET(i)))
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..b92ee5311093796dfd0fbf6d8d41c1018a808c71
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_3
+* @{
+*
+* The implementation of the XDmaPs driver's static initialzation
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/13/10 First Release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+extern XDmaPs_Config XDmaPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return
+*
+* A pointer to the configuration structure or NULL if the specified device
+* is not in the system.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
+{
+ XDmaPs_Config *CfgPtr = NULL;
+
+ int i;
+
+ for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
+ if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XDmaPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
new file mode 100644
index 0000000000000000000000000000000000000000..c013c4946a7ac561d37d20a92e0dee47290ee764
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c
@@ -0,0 +1,492 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+* 64-bit changes.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
+* Disable extended mode. Perform all 64 bit changes under
+* check for arch64.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5 hk 08/14/17 Update cache coherency information of the interface in
+* its config structure.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void); /* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+* hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+* translation is not utilized, this parameter can be passed in using
+* CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+ UINTPTR EffectiveAddress)
+{
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Set device base address and ID */
+ InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+
+ /* Set callbacks to an initial stub routine */
+ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+ /* Reset the hardware and set default options */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ XEmacPs_Reset(InstancePtr);
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+* - Start the SG DMA send and receive channels and enable the device
+* interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Start DMA */
+ /* When starting the DMA channels, both transmit and receive sides
+ * need an initialized BD list.
+ */
+ if (InstancePtr->Version == 2) {
+ Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+ Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ InstancePtr->RxBdRing.BaseBdAddr);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ InstancePtr->TxBdRing.BaseBdAddr);
+ }
+
+ /* clear any existed int status */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Enable transmitter if not already enabled */
+ if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+ }
+ }
+
+ /* Enable receiver if not already enabled */
+ if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+ }
+ }
+
+ /* Enable TX and RX interrupts */
+ XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+ XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+ (u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+ /* Enable TX Q1 Interrupts */
+ if (InstancePtr->Version > 2)
+ XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+ /* Mark as started */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+* - Disable all interrupts from this device
+* - Stop DMA channels
+* - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Disable the receiver & transmitter */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Mark as stopped */
+ InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ u8 i;
+ s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Stop the device and reset hardware */
+ XEmacPs_Stop(InstancePtr);
+ InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+ InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+ InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+ InstancePtr->MaxMtuSize = XEMACPS_MTU;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+ XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+ /* Setup hardware with default values */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ (XEMACPS_NWCTRL_STATCLR_MASK |
+ XEMACPS_NWCTRL_MDEN_MASK) &
+ (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+ Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+ (u32)XEMACPS_NWCFG_FDEN_MASK |
+ (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+ XEMACPS_NWCFG_DWIDTH_64_MASK));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET,
+ (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+ (u32)XEMACPS_DMACR_RXSIZE_MASK |
+ (u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+ /* Single bursts */
+ /* FIXME: Why Single bursts? */
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#ifdef __aarch64__
+ (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+ (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, 0x0U);
+
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+ if (InstancePtr->Version > 2)
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, 0x0U);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ Reg);
+
+ XEmacPs_ClearHash(InstancePtr);
+
+ for (i = 1U; i < 5U; i++) {
+ (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+ (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+ }
+
+ /* clear all counters */
+ for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+ i++) {
+ (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+ }
+
+ /* Disable the receiver */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Sync default options with hardware but leave receiver and
+ * transmitter disabled. They get enabled with XEmacPs_Start() if
+ * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+ * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+ */
+ (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+ ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+ (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @QPtr Address of the Queue to be written
+* @QueueNum Buffer Queue Index
+* @Direction Transmit/Recive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction)
+{
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* If already started, then there is nothing to do */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ return;
+ }
+
+ if (QueueNum == 0x00U) {
+ if (Direction == XEMACPS_SEND) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ } else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+ }
+ else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQ1BASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+#ifdef __aarch64__
+ if (Direction == XEMACPS_SEND) {
+ /* Set the MSB of TX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_TXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ } else {
+ /* Set the MSB of RX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_RXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ }
+#endif
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
new file mode 100644
index 0000000000000000000000000000000000000000..6d4b15b24338a4618844512250528f0c1fc1897a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h
@@ -0,0 +1,809 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_7
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
new file mode 100644
index 0000000000000000000000000000000000000000..83f9a87fc1e6b6411f50a38931636c0a20f1144c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h
@@ -0,0 +1,804 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_7
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
new file mode 100644
index 0000000000000000000000000000000000000000..3536873dc9971f1572d48453363862fc92e66ed6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
@@ -0,0 +1,1102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+* Earlier it used to search in "BdLimit" number of BDs to
+* know which BDs are processed. Now one more check is
+* added. It looks for BDs till the current BD pointer
+* reaches HwTail. By doing this processing time is saved.
+* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+* xemacps_bdring.c is modified. Now start of packet is
+* searched for returning the number of BDs processed.
+* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+* removed. It is expected that all BDs are allocated in
+* from uncached area. Fix for CR #663885.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* pointers
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+ ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+ ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr += ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
+ { \
+ Addr -= (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
+ }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr -= ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
+ { \
+ Addr += (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
+ }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ * address translation is not being utilized, then VirtAddr should be
+ * equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ * will enforce a minimum alignment of 4 bytes with no maximum as long
+ * as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ * is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ * channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ * parameter.
+ * 2) Alignment parameter does not meet minimum requirements or is not a
+ * power of 2 value.
+ * 3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ * over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+ u32 i;
+ UINTPTR BdVirtAddr;
+ UINTPTR BdPhyAddr;
+ UINTPTR VirtAddrLoc = VirtAddr;
+
+ /* In case there is a failure prior to creating list, make sure the
+ * following attributes are 0 to prevent calls to other functions
+ * from doing anything.
+ */
+ RingPtr->AllCnt = 0U;
+ RingPtr->FreeCnt = 0U;
+ RingPtr->HwCnt = 0U;
+ RingPtr->PreCnt = 0U;
+ RingPtr->PostCnt = 0U;
+
+ /* Make sure Alignment parameter meets minimum requirements */
+ if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure Alignment is a power of 2 */
+ if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure PhysAddr and VirtAddr are on same Alignment */
+ if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is BdCount reasonable? */
+ if (BdCount == 0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Figure out how many bytes will be between the start of adjacent BDs */
+ RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+ /* Must make sure the ring doesn't span address 0x00000000. If it does,
+ * then the next/prev BD traversal macros will fail.
+ */
+ if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Initial ring setup:
+ * - Clear the entire space
+ * - Setup each BD's BDA field with the physical address of the next BD
+ */
+ (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+ BdVirtAddr = VirtAddrLoc;
+ BdPhyAddr = PhysAddr + RingPtr->Separation;
+ for (i = 1U; i < BdCount; i++) {
+ BdVirtAddr += RingPtr->Separation;
+ BdPhyAddr += RingPtr->Separation;
+ }
+
+ /* Setup and initialize pointers and counters */
+ RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+ RingPtr->BaseBdAddr = VirtAddrLoc;
+ RingPtr->PhysBaseAddr = PhysAddr;
+ RingPtr->HighBdAddr = BdVirtAddr;
+ RingPtr->Length =
+ ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+ RingPtr->AllCnt = (u32)BdCount;
+ RingPtr->FreeCnt = (u32)BdCount;
+ RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+ RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ * BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the list was modified.
+ * - XST_DMA_SG_NO_LIST if a list has not been created.
+ * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ * hardware or user control.
+ * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction)
+{
+ u32 i;
+ UINTPTR CurBd;
+
+ /* Can't do this function if there isn't a ring */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't do this function with the channel running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_DEVICE_IS_STARTED);
+ }
+
+ /* Can't do this function with some of the BDs in use */
+ if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Starting from the top of the ring, save BD.Next, overwrite the entire
+ * BD with the template, then restore BD.Next
+ */
+ CurBd = RingPtr->BaseBdAddr;
+ for (i = 0U; i < RingPtr->AllCnt; i++) {
+ memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+ CurBd += RingPtr->Separation;
+ }
+
+ CurBd -= RingPtr->Separation;
+
+ if (Direction == XEMACPS_RECV) {
+ XEmacPs_BdSetRxWrap(CurBd);
+ }
+ else {
+ XEmacPs_BdSetTxWrap(CurBd);
+ }
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ *
+ * NumBd = 2,
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ * if (Status != XST_SUCCESS)
+ * {
+ * *Not enough BDs available for the request*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ *
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ * parameter.
+ * - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ * parameter. Doing so will lead to data corruption and system
+ * instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ LONG Status;
+ /* Enough free BDs available for the request? */
+ if (RingPtr->FreeCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead forward */
+ *BdSetPtr = RingPtr->FreeHead;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+ RingPtr->FreeCnt -= NumBd;
+ RingPtr->PreCnt += NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ *
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ * ...
+ * if (Error)
+ * {
+ * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ * }
+ *
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ *
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the BDs were unallocated.
+ * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ * the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ (void) BdSetPtr;
+ Xil_AssertNonvoid(RingPtr != NULL);
+ Xil_AssertNonvoid(BdSetPtr != NULL);
+
+ /* Enough BDs in the free state for the request? */
+ if (RingPtr->PreCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead backward */
+ XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PreCnt -= NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ * did not have its "last" bit set.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 i;
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+ if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ CurBdPtr = BdSetPtr;
+ for (i = 0U; i < NumBd; i++) {
+ CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+ }
+ /* Adjust ring pointers & counters */
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+ RingPtr->PreCnt -= NumBd;
+ RingPtr->HwTail = CurBdPtr;
+ RingPtr->HwCnt += NumBd;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ * if (NumBd == 0)
+ * {
+ * * hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Sop = 0U;
+ u32 Status;
+ u32 BdLimitLoc = BdLimit;
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ if (BdLimitLoc > RingPtr->HwCnt){
+ BdLimitLoc = RingPtr->HwCnt;
+ }
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has not completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimitLoc) {
+ /* Read the status */
+ if(CurBdPtr != NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+
+ if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+ Sop = 1U;
+ }
+ if (Sop == 0x00000001U) {
+ BdCount++;
+ BdPartialCount++;
+ }
+
+ /* hardware has processed this BD so check the "last" bit.
+ * If it is clear, then there are more BDs for the current
+ * packet. Keep a count of these partial packet BDs.
+ */
+ if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+ Sop = 0U;
+ BdPartialCount = 0U;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ } else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ * if (NumBd == 0)
+ * {
+ * *hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Status;
+
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimit) {
+
+ /* Read the status */
+ if(CurBdPtr!=NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+ if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+ break;
+ }
+
+ BdCount++;
+
+ /* hardware has processed this BD so check the "last" bit. If
+ * it is clear, then there are more BDs for the current packet.
+ * Keep a count of these partial packet BDs.
+ */
+ if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+ BdPartialCount = 0U;
+ } else {
+ BdPartialCount++;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ }
+ else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+}
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0x00000000U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+ if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ /* Update pointers and counters */
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PostCnt -= NumBd;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ * - Is the BD ring linked correctly in physical address space.
+ * - Do the internal pointers point to BDs in the ring.
+ * - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_NO_LIST if the list has not been created.
+ * - XST_IS_STARTED if the channel is not stopped.
+ * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ * structures. If this value is returned, the channel should be reset to
+ * avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+ UINTPTR AddrV, AddrP;
+ u32 i;
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is the list created */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't check if channel is running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_IS_STARTED);
+ }
+
+ /* RunState doesn't make sense */
+ if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal pointers point to correct memory space */
+ AddrV = (UINTPTR) RingPtr->FreeHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PreHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwTail;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PostHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal counters add up */
+ if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+ RingPtr->PostCnt) != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify BDs are linked correctly */
+ AddrV = RingPtr->BaseBdAddr;
+ AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+ for (i = 1U; i < RingPtr->AllCnt; i++) {
+ /* Check BDA for this BD. It should point to next physical addr */
+ if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Move on to next BD */
+ AddrV += RingPtr->Separation;
+ AddrP += RingPtr->Separation;
+ }
+
+ /* Last BD should have wrap bit set */
+ if (XEMACPS_SEND == Direction) {
+ if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+ else { /* XEMACPS_RECV */
+ if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+
+ /* No problems found */
+ return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueRx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueRx = *TempPtr;
+ DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+ *TempPtr = DataValueRx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueTx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueTx = *TempPtr;
+ DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+ *TempPtr = DataValueTx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param VirtAddr is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+ RingPtr->FreeHead = virtaddrloc;
+ RingPtr->PreHead = virtaddrloc;
+ RingPtr->HwHead = virtaddrloc;
+ RingPtr->HwTail = virtaddrloc;
+ RingPtr->PostHead = virtaddrloc;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
new file mode 100644
index 0000000000000000000000000000000000000000..b89e89885b9109f3db432b7592b1d71dd8c6e88d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
@@ -0,0 +1,241 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
new file mode 100644
index 0000000000000000000000000000000000000000..8217a45218239110247292b1bcfac9b2001e3fda
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_7
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * register. Added a new API for setting the BURST length
+ * in DMACR register.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ *
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device. The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Aptr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ }
+ else{
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ /* Set the MAC bits [31:0] in BOT */
+ MacAddr = *(Aptr);
+ MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+ MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+ MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ /* There are reserved bits in TOP so don't affect them */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+ MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+ /* Set MAC bits [47:32] in TOP */
+ MacAddr |= (u32)(*(Aptr+4));
+ MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ * which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Aptr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *Aptr = (u8) MacAddr;
+ *(Aptr+1) = (u8) (MacAddr >> 8U);
+ *(Aptr+2) = (u8) (MacAddr >> 16U);
+ *(Aptr+3) = (u8) (MacAddr >> 24U);
+
+ /* Read MAC bits [47:32] in TOP */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *(Aptr+4) = (u8) MacAddr;
+ *(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ *
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ *
+ * 000 : divide pclk by 8 (pclk up to 20 MHz)
+ * 001 : divide pclk by 16 (pclk up to 40 MHz)
+ * 010 : divide pclk by 32 (pclk up to 80 MHz)
+ * 011 : divide pclk by 48 (pclk up to 120 MHz)
+ * 100 : divide pclk by 64 (pclk up to 160 MHz)
+ * 101 : divide pclk by 96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+ u32 Reg;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ /* clear these three bits, could be done with mask */
+ Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+ Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+* which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpReadTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpReadTemp = Ipisr;
+ } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ /* Read data */
+ *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY. Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+* status from the MAC on a write, the user should read the PHY to verify the
+* write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpWriteTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpWriteTemp = Ipisr;
+ } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+ u32 Reg;
+ u32 RegUpdateVal;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+ (BLength == XEMACPS_4BYTE_BURST) ||
+ (BLength == XEMACPS_8BYTE_BURST) ||
+ (BLength == XEMACPS_16BYTE_BURST));
+
+ switch (BLength) {
+ case XEMACPS_SINGLE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+ break;
+
+ case XEMACPS_4BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+ break;
+
+ case XEMACPS_8BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+ break;
+
+ case XEMACPS_16BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+ break;
+
+ default:
+ RegUpdateVal = 0x00000000U;
+ break;
+ }
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+
+ Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+ Reg |= RegUpdateVal;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ Reg);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..2554f27bafeddae61f0665f74e5f89544d688fcd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_ETHERNET_0_DEVICE_ID,
+ XPAR_PS7_ETHERNET_0_BASEADDR,
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..00e79a58d4366895b81d3efc6c47fff5c703b9a6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc 28/06/13 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status registers
+* Disable Rx and Tx engines
+* Update the Tx and Rx descriptor queue registers with reset values
+* Update the other relevant control registers with reset value
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+ u32 RegVal;
+
+ /* Disable the interrupts */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+ /* Stop transmission,disable loopback and Stop tx and Rx engines */
+ RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+ RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+ (u32)XEMACPS_NWCTRL_RXEN_MASK|
+ (u32)XEMACPS_NWCTRL_HALTTX_MASK|
+ (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+ /* Clear the statistic registers, flush the packets in DPRAM*/
+ RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+ XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+ /* Clear the interrupt status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+ /* Clear the tx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+ (u32)XEMACPS_TXSR_TXCOMPL_MASK|
+ (u32)XEMACPS_TXSR_TXGO_MASK));
+ /* Clear the rx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+ XEMACPS_RXSR_FRAMERX_MASK);
+ /* Clear the tx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+ /* Clear the rx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+ /* Update the network config register with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+ /* Update the hash address registers with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..e535470c2e5b0c663b26a7780c0e2c42ccdb5edb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
+ transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
+ */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c355a1637b433df11d1cc19a18bd6822163a74e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
+* Rx errors. Under heavy Rx traffic, there will be a large
+* number of errors related to receive buffer not available.
+* Because of a HW bug (SI #692601), under such heavy errors,
+* the Rx data path can become unresponsive. To reduce the
+* probabilities for hitting this HW bug, the SW writes to
+* bit 18 to flush a packet from Rx DPRAM immediately. The
+* changes for it are done in the function
+* XEmacPs_IntrHandler.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+* and 64-bit changes.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+* there is no error. CR# 869403
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ * XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ * when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef)
+{
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FuncPointer != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ switch (HandlerType) {
+ case XEMACPS_HANDLER_DMASEND:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->SendRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_DMARECV:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->RecvRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_ERROR:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+ InstancePtr->ErrorRef = CallBackRef;
+ break;
+ default:
+ Status = (LONG)(XST_INVALID_PARAM);
+ break;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+* interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+ u32 RegISR;
+ u32 RegSR;
+ u32 RegCtrl;
+ u32 RegQ1ISR = 0U;
+ XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* This ISR will try to handle as many interrupts as it can in a single
+ * call. However, in most of the places where the user's error handler
+ * is called, this ISR exits because it is expected that the user will
+ * reset the device in nearly all instances.
+ */
+ RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+
+ /* Read Transmit Q1 ISR */
+
+ if (InstancePtr->Version > 2)
+ RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET);
+
+ /* Clear the interrupt status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ RegISR);
+
+ /* Receive complete interrupt */
+ if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+ /* Clear RX status register RX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET,
+ ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+ (u32)XEMACPS_RXSR_BUFFNA_MASK));
+ InstancePtr->RecvHandler(InstancePtr->RecvRef);
+ }
+
+ /* Transmit Q1 complete interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET,
+ XEMACPS_INTQ1SR_TXCOMPL_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Transmit complete interrupt */
+ if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Receive error conditions interrupt */
+ if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+ /* Clear RX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, RegSR);
+
+ /* Fix for CR # 692702. Write to bit 18 of net_ctrl
+ * register to flush a packet out of Rx SRAM upon
+ * an error for receive buffer not available. */
+ if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+ RegCtrl =
+ XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, RegCtrl);
+ }
+
+ if(RegSR != 0) {
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+ XEMACPS_RECV, RegSR);
+ }
+ }
+
+ /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+ * will be asserted the same time.
+ * Have to distinguish this bit to handle the real error condition.
+ */
+ /* Transmit Q1 error conditions interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear Interrupt Q1 status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegQ1ISR);
+ }
+
+ /* Transmit error conditions interrupt */
+ if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+ (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, RegSR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegSR);
+ }
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..e2d2078af1a501356e901d70b9f38c8b013ff103
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 New
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+ XEmacPs_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+ if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XEmacPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b6fe2e46010b2aafc4eabe582176a2c5d8295e5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
@@ -0,0 +1,628 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device. The interrupts are disabled
+* for output pins on all banks during initialization.
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param ConfigPtr points to the XGpioPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address should be passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS always.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status = XST_SUCCESS;
+ u8 i;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->IsReady = 0U;
+ InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+ InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Handler = StubHandler;
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ /* Initialize the Bank data based on platform */
+ if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * Max pins in the ZynqMP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+ InstancePtr->MaxPinNum = (u32)174;
+ InstancePtr->MaxBanks = (u8)6;
+ } else {
+ /*
+ * Max pins in the GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+ InstancePtr->MaxPinNum = (u32)118;
+ InstancePtr->MaxBanks = (u8)4;
+ }
+
+ /*
+ * By default, interrupts are not masked in GPIO. Disable
+ * interrupts for all pins in all the 4 banks.
+ */
+ for (i=0;iMaxBanks;i++) {
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+ }
+
+ /* Indicate the component is now ready to use. */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Current value of the Data register.
+*
+* @note This function is used for reading the state of all the GPIO pins
+* of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the data has to be read.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return Current value of the Pin (0 or 1).
+*
+* @note This function is used for reading the state of the specified
+* GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Data is the value to be written to the Data register.
+*
+* @return None.
+*
+* @note This function is used for writing to all the GPIO pins of
+* the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Data is the data to be written to the specified pin (0 or 1).
+*
+* @return None.
+*
+* @note This function does a masked write to the specified pin of
+* the specified GPIO bank. The previous state of other pins
+* is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+ u32 RegOffset;
+ u32 Value;
+ u8 Bank;
+ u8 PinNumber;
+ u32 DataVar = Data;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ if (PinNumber > 15U) {
+ /* There are only 16 data bits in bit maskable register. */
+ PinNumber -= (u8)16;
+ RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+ } else {
+ RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+ }
+
+ /*
+ * Get the 32 bit value to be written to the Mask/Data register where
+ * the upper 16 bits is the mask and lower 16 bits is the data.
+ */
+ DataVar &= (u32)0x01;
+ Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+ RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Direction is the 32 bit mask of the Pin direction to be set for
+* all the pins in the Bank. Bits with 0 are set to Input mode,
+* bits with 1 are set to Output Mode.
+*
+* @return None.
+*
+* @note This function is used for setting the direction of all the pins
+* in the specified bank. The previous state of the pins is
+* not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Direction is the direction to be set for the specified pin.
+* Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 DirModeReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(Direction <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+
+ if (Direction!=(u32)0) { /* Output Direction */
+ DirModeReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Input Direction */
+ DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return Returns a 32 bit mask of the Direction register. Bits with 0 are
+* in Input mode, bits with 1 are in Output Mode.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Direction is to be
+* retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Direction of the specified pin.
+* - 0 for Input Direction
+* - 1 for Output Direction
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param OpEnable is the 32 bit mask of the Output Enables to be set for
+* all the pins in the Bank. The Output Enable of bits with 0 are
+* disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return None.
+*
+* @note This function is used for setting the Output Enables of all the
+* pins in the specified bank. The previous state of the Output
+* Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param OpEnable specifies whether the Output Enable for the specified
+* pin should be enabled.
+* Valid values are 0 for Disabling Output Enable,
+* 1 for Enabling Output Enable.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 OpEnableReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(OpEnable <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+
+ if (OpEnable != (u32)0) { /* Enable Output Enable */
+ OpEnableReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Disable Output Enable */
+ OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return Returns a a 32 bit mask of the Output Enable register.
+* Bits with 0 are in Disabled state, bits with 1 are in
+* Enabled State.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Output Enable status is to
+* be retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Output Enable of the specified pin.
+* - 0 if Output Enable is disabled for this pin
+* - 1 if Output Enable is enabled for this pin
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param PinNumber is the Pin number in the GPIO device.
+* @param BankNumber returns the Bank in which this GPIO pin is present.
+* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+ u32 XGpioPsPinTable[6] = {0};
+ u32 Platform = XGetPlatform_Info();
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * This structure defines the mapping of the pin numbers to the banks when
+ * the driver APIs are used for working on the individual pins.
+ */
+
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+ XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+ XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+ XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+ XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 6U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ } else {
+ XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+ XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+ XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+ XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 4U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ }
+ if (*BankNumber == (u8)0) {
+ *PinNumberInBank = PinNumber;
+ } else {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+ }
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
new file mode 100644
index 0000000000000000000000000000000000000000..fda562d9190651d7a655d00c57d930d13fad5232
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
@@ -0,0 +1,277 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_3
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..76e6947a8ffbf5ca07a703272a788f63a1f7fce1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_GPIO_0_DEVICE_ID,
+ XPAR_PS7_GPIO_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..8961c4287d45ebcc218a7c30b2674bc50d54bdb0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains low level GPIO functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk 08/22/13 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param Base address of GPIO module
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+ u32 BankCount;
+ u32 Platform,MaxBanks;
+
+ Platform = XGetPlatform_Info();
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ MaxBanks = (u32)6;
+ } else {
+ MaxBanks = (u32)4;
+ }
+ /* Write reset values to all mask data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+ }
+ /* Write reset values to all output data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET), 0x0U);
+ }
+
+ /* Reset all registers of all GPIO banks */
+ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET), 0x0U);
+ }
+
+ /* Bank 0 Int type */
+ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+ XGPIOPS_INTTYPE_BANK0_RESET);
+ /* Bank 1 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK1_RESET);
+ /* Bank 2 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK2_RESET);
+ /* Bank 3 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK3_RESET);
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /* Bank 4 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK4_RESET);
+ /* Bank 5 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK5_RESET);
+ }
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ff01906750193cf49b097c7921a0c38c516c4641
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8b0a5626d591b03ac9036b19ef788effaeeb175
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to API's. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are to
+* be enabled. Bit positions of 1 will be enabled. Bit positions
+* of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be enabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg = 0U;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are
+* to be disabled. Bit positions of 1 will be disabled. Bit
+* positions of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be disabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg = 0U;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+* indicate that the interrupt for that pin is enabled, bit
+* positions with 0 indicate that the interrupt for that pin is
+* disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+ u32 IntrMask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+ return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt is enabled.
+* - FALSE if the interrupt is disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return The value read from Interrupt Status Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt has occurred.
+* - FALSE if the interrupt has not occurred.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the mask of the interrupts to be cleared. Bit positions
+* of 1 will be cleared. Bit positions of 0 will not change the
+* previous interrupt status.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ /* Clear the currently pending interrupts. */
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt status is to be
+* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ /* Clear the specified pending interrupts. */
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ IntrReg &= ((u32)1 << PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType is the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
+* 0 means Active Low or Falling Edge and 1 means Active High or
+* Rising Edge.
+* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note This function is used for setting the interrupt related
+* properties of all the pins in the specified bank. The previous
+* state of the pins is not maintained.
+* To change the Interrupt properties of a single GPIO pin, use the
+* function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType returns the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity returns the 32 bit mask of the interrupt
+* polarity. 0 means Active Low or Falling Edge and 1 means
+* Active High or Rising Edge.
+* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be set.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+* defined in xgpiops.h to specify the IRQ type.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+ u32 IntrTypeReg;
+ u32 IntrPolReg;
+ u32 IntrOnAnyReg;
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+
+ switch (IrqType) {
+ case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ default:
+ /**< Default statement is added for MISRA C compliance. */
+ break;
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be obtained.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+* returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u32 IntrType;
+ u32 IntrPol;
+ u32 IntrOnAny;
+ u8 Bank;
+ u8 PinNumber;
+ u8 IrqType;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrType == ((u32)1 << PinNumber)) {
+
+ IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+ if (IntrOnAny == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+ } else if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+ }
+ } else {
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+ }
+ }
+
+ return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPtr is the pointer to the callback function.
+*
+*
+* @return None.
+*
+* @note The handler is called within interrupt context, so it should do
+* its work quickly and queue potentially time-consuming work to a
+* task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPointer != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = FuncPointer;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return None.
+*
+* @note This function does not save and restore the processor context
+* such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+ u8 Bank;
+ u32 IntrStatus;
+ u32 IntrEnabled;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+ IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+ if (IntrStatus != (u32)0) {
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+ Bank);
+ XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+ (IntrStatus & IntrEnabled));
+ InstancePtr->Handler(InstancePtr->
+ CallBackRef, Bank,
+ (IntrStatus & IntrEnabled));
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param Bank is the GPIO Bank in which an interrupt occurred.
+* @param Status is the Interrupt status of the GPIO bank.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+ (void) CallBackRef;
+ (void) Bank;
+ (void) Status;
+
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..378524c14311e14230df5b92c3d2fb0a4168919e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+* - XST_SUCCESS if the self-test passed.
+* - XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrEnabled;
+ u32 CurrentIntrType = 0U;
+ u32 CurrentIntrPolarity = 0U;
+ u32 CurrentIntrOnAny = 0U;
+ u32 IntrType = 0U;
+ u32 IntrPolarity = 0U;
+ u32 IntrOnAny = 0U;
+ u32 IntrTestValue = 0x22U;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable the Interrupts for Bank 0 . */
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+ XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ /*
+ * Get the Current Interrupt properties for Bank 0.
+ * Set them to a known value, read it back and compare.
+ */
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+ &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+ IntrTestValue, IntrTestValue);
+
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+ &IntrPolarity, &IntrOnAny);
+
+ if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+ (IntrOnAny != IntrTestValue)) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the contents of all the interrupt registers modified in this
+ * test.
+ */
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+ CurrentIntrPolarity, CurrentIntrOnAny);
+
+ XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..4cc0c390f29b76c680c9eb42dfd61fc09894c3c3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+ XGpioPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+ if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XGpioPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
new file mode 100644
index 0000000000000000000000000000000000000000..9546b5490216ff792e5afe9f38c957b99d30de90
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm 09/21/11 Updated the InstancePtr->Options in the
+* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1 hk 04/25/14 Explicitly reset CR and clear FIFO in Abort function
+* and state the same in the comments. CR# 784254.
+* Fix for CR# 761060 - provision for repeated start.
+* 2.3 sk 10/07/14 Repeated start feature removed.
+* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
+* in XIicPs_Reset.
+* 12/06/14 Implemented Repeated start feature.
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+* - Device is disabled
+* - Slave mode
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific IIC device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->BaseAddress for this parameter, passing the physical
+* address instead.
+*
+* @return The return value is XST_SUCCESS if successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+ InstancePtr->StatusHandler = StubHandler;
+ InstancePtr->CallBackRef = NULL;
+
+ InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+ /*
+ * Reset the IIC device to get it into its initial state. It is expected
+ * that device configuration will take place after this initialization
+ * is done, but before the device is started.
+ */
+ XIicPs_Reset(InstancePtr);
+
+ /*
+ * Keep a copy of what options this instance has.
+ */
+ InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+ /* Initialize repeated start flag to 0 */
+ InstancePtr->IsRepeatedStart = 0;
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* - TRUE if the bus is busy.
+* - FALSE if the bus is not busy.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+ u32 StatusReg;
+ s32 Status;
+
+ StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_SR_OFFSET);
+ if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+ Status = (s32)TRUE;
+ }else {
+ Status = (s32)FALSE;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference.
+* @param StatusEvent is the event that just occurred.
+* @param ByteCount is the number of bytes transferred up until the event
+* occurred.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+ (void) ((void *)CallBackRef);
+ (void) StatusEvent;
+ Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+ u32 IntrMaskReg;
+ u32 IntrStatusReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enter a critical section, so disable the interrupts while we clear
+ * the FIFO and the status register.
+ */
+ IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_IMR_OFFSET);
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+ /*
+ * Reset the settings in config register and clear the FIFOs.
+ */
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+ (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
+
+ /*
+ * Read, then write the interrupt status to make sure there are no
+ * pending interrupts.
+ */
+ IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Restore the interrupt state.
+ */
+ IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization. Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /*
+ * Abort any transfer that is in progress.
+ */
+ XIicPs_Abort(InstancePtr);
+
+ /*
+ * Reset any values so the software state matches the hardware device.
+ */
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+ XIICPS_CR_RESET_VALUE);
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+ XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return Number of bytes left for this instance.
+*
+* @note This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+ u8 AvailBytes;
+ s32 LoopCnt;
+ s32 NumBytesToSend;
+
+ /*
+ * Determine number of bytes to write to FIFO.
+ */
+ AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+ (u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_TRANS_SIZE_OFFSET);
+
+ if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+ NumBytesToSend = (s32)AvailBytes;
+ } else {
+ NumBytesToSend = InstancePtr->SendByteCount;
+ }
+
+ /*
+ * Fill FIFO with amount determined above.
+ */
+ for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+ XIicPs_SendByte(InstancePtr);
+ }
+
+ return InstancePtr->SendByteCount;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
new file mode 100644
index 0000000000000000000000000000000000000000..d3713de471faaa1242d156a58b25ab89ced025b7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
@@ -0,0 +1,425 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_7
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface. The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+* the static configuration structure defined in xiicps_g.c. This is
+* setup by the tools. For some operating systems the config structure
+* will be initialized by the software and this call is not needed.
+*
+* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a
+* system with address translation, the provided virtual memory base
+* address replaces the physical address in the configuration
+* structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*Repeated Start
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/08 First release
+* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
+* XIicPs_ClearOptions where the InstancePtr->Options
+* was not updated correctly.
+* Updated the InstancePtr->Options in the
+* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* Updated the XIicPs_SetupMaster to not check for
+* Bus Busy condition when the Hold Bit is set.
+* Removed some unused variables.
+* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+* check for transfer completion is added, which indicates
+* the completion of current transfer.
+* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
+* to achieve I2C clock with minimum error for
+* CR #674195
+* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
+* This is fix for CR#704398 to remove warning.
+* 2.0 hk 03/07/14 Added check for error status in the while loop that
+* checks for completion.
+* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+* Limited frequency set when 100KHz or 400KHz is
+* selected. This is a hardware limitation. CR#779290.
+* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+* Explicitly reset CR and clear FIFO in Abort function
+* and state the same in the comments. CR# 784254.
+* Fix for CR# 761060 - provision for repeated start.
+* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
+* read mode and clear transfer size register.
+* Disable NACK to avoid interrupts on each retry.
+* 2.3 sk 10/07/14 Repeated start feature deleted.
+* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
+* in XIicPs_Reset.
+* 12/06/14 Implemented Repeated start feature.
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 02/18/15 Implemented larger data transfer using repeated start
+* in Zynq UltraScale MP.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ask 04/17/18 Updated the Eeprom scanning mechanism
+* as per the other examples (CR#997545)
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIICPS_H /* prevent circular inclusions */
+#define XIICPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC. Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver. These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
+#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE 1 /**< Transfer direction is sending */
+#define RECVING_ROLE 0 /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* not important to the driver, so it is a void pointer.
+* @param StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XIicPs_Config Config; /* Configuration structure */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Options set in the device */
+
+ u8 *SendBufferPtr; /* Pointer to send buffer */
+ u8 *RecvBufferPtr; /* Pointer to recv buffer */
+ s32 SendByteCount; /* Number of bytes still expected to send */
+ s32 RecvByteCount; /* Number of bytes still expected to receive */
+ s32 CurrByteCount; /* No. of bytes expected in current transfer */
+
+ s32 UpdateTxSize; /* If tx size register has to be updated */
+ s32 IsSend; /* Whether master is sending or receiving */
+ s32 IsRepeatedStart; /* Indicates if user set repeated start */
+
+ XIicPs_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param InstancePtr is the instance of IIC
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr) \
+{ \
+ u8 Data; \
+ Data = *((InstancePtr)->SendBufferPtr); \
+ XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ + (u32)(XIICPS_DATA_OFFSET), \
+ (u32)(Data)); \
+ (InstancePtr)->SendBufferPtr += 1; \
+ (InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param InstancePtr is the instance of IIC
+*
+* @return None.
+*
+* @note C-Style signature:
+* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr) \
+{ \
+ u8 *Data, Value; \
+ Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ + (u32)XIICPS_DATA_OFFSET)); \
+ Data = &Value; \
+ *(InstancePtr)->RecvBufferPtr = *Data; \
+ (InstancePtr)->RecvBufferPtr += 1; \
+ (InstancePtr)->RecvByteCount --; \
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+ u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+ XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..64ac648119573eb70d7f18b1c29d04560d8f4bd1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_I2C_0_DEVICE_ID,
+ XPAR_PS7_I2C_0_BASEADDR,
+ XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..ce81d92ab9c8f67358ea4f28e57427789c455f95
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- --------------------------------------------
+* 1.04a kpc 11/07/13 First release
+* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status
+* Clear FIFO's and disable hold bit
+* Clear the line status
+* Update relevant config registers with reset values
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+
+ /* Disable all the interrupts */
+ XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+ /* Clear the interrupt status */
+ RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+ /* Clear the hold bit,master enable bit and ack bit */
+ RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+ RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+ /* Clear the fifos */
+ RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+ XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+ /* Clear the timeout register */
+ XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+ /* Clear the transfer size register */
+ XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+ /* Clear the status register */
+ RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+ XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+ /* Update the configuraqtion register with reset value */
+ XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9d63ec8f68e84d3d746dee4b0d7cabe4a6f9975
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_7
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.04a kpc 11/07/13 Added function prototype.
+* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H /* prevent circular inclusions */
+#define XIICPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
+#define XIICPS_SR_OFFSET 0x04U /**< Status */
+#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
+#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
+#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
+ 0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
+ Master receiver*/
+#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
+ 0=10 bit */
+#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
+ 0=Slave */
+#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
+ transfer 0=Transmitter,
+ 1=Receiver*/
+#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
+ register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists. Other flags are
+ * edge triggered, which means they are set one the interrupt condition occurs
+ * then remain set until they are cleared by software.
+ * The interrupts are cleared by writing a one to the interrupt bit position
+ * in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Disable Register
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
+ mask */
+#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
+ Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
+ Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
+ mask */
+#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
+ Interrupt mask */
+#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
+ Interrupt mask */
+#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
+ Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+* - Master transmitter mode: number of data bytes still not transmitted minus
+* one
+* - Master receiver mode: number of data bytes that are still expected to be
+* received
+* - Slave transmitter mode: number of bytes remaining in the FIFO after the
+* master terminates the transfer
+* - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+ XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to select the specific register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return Current bit mask that represents currently enabled interrupts.
+*
+* @note C-Style signature:
+* u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+ XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param IntrMask is the interrupts to be enabled.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+ XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param IntrMask is the interrupts to be disabled.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+ XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+ (IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..6dccff4c8820b184bab8ca32dc9dfd2a863a3a69
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FunctionPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+ XIicPs_IntrHandler FunctionPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FunctionPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = FunctionPtr;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
new file mode 100644
index 0000000000000000000000000000000000000000..5554209102455ce05b11f62b0bca2729dd89aaa3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
@@ -0,0 +1,999 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Handles master mode transfers.
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a jz 01/30/10 First release
+* 1.00a sdm 09/21/11 Updated the XIicPs_SetupMaster to not check for
+* Bus Busy condition when the Hold Bit is set.
+* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+* check for transfer completion is added, which indicates
+* the completion of current transfer.
+* 2.0 hk 03/07/14 Added check for error status in the while loop that
+* checks for completion. CR# 762244, 764875.
+* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+* Fix for CR# 761060 - provision for repeated start.
+* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
+* read mode and clear transfer size register.
+* Disable NACK to avoid interrupts on each retry.
+* 2.3 sk 10/06/14 Fill transmit fifo before address register when sending.
+* Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* Repeated start feature removed.
+* 3.0 sk 12/06/14 Implemented Repeated start feature.
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 02/18/15 Implemented larger data transfer using repeated start
+* in Zynq UltraScale MP.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
+* before slave address. Fix for CR996440.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the send buffer.
+* @param ByteCount is the number of bytes to be sent.
+* @param SlaveAddr is the address of the slave we are sending to.
+*
+* @return None.
+*
+* @note This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr)
+{
+ u32 BaseAddr;
+ u32 Platform = XGetPlatform_Info();
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsgPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->SendBufferPtr = MsgPtr;
+ InstancePtr->SendByteCount = ByteCount;
+ InstancePtr->RecvBufferPtr = NULL;
+ InstancePtr->IsSend = 1;
+
+ /*
+ * Set repeated start if sending more than FIFO of data.
+ */
+ if (((InstancePtr->IsRepeatedStart) != 0)||
+ ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+ (u32)XIICPS_CR_HOLD_MASK);
+ }
+
+ /*
+ * Setup as a master sending role.
+ */
+ (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+ (void)TransmitFifoFill(InstancePtr);
+
+ XIicPs_EnableInterrupts(BaseAddr,
+ (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+ (u32)XIICPS_IXR_ARB_LOST_MASK);
+ /*
+ * Do the address transfer to notify the slave.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+ /* Clear the Hold bit in ZYNQ if receive byte count is less than
+ * the FIFO depth to get the completion interrupt properly.
+ */
+ if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+ {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+ (u32)(~XIICPS_CR_HOLD_MASK));
+ }
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the receive buffer.
+* @param ByteCount is the number of bytes to be received.
+* @param SlaveAddr is the address of the slave we are receiving from.
+*
+* @return None.
+*
+* @note This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+ u16 SlaveAddr)
+{
+ u32 BaseAddr;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsgPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->RecvBufferPtr = MsgPtr;
+ InstancePtr->RecvByteCount = ByteCount;
+ InstancePtr->SendBufferPtr = NULL;
+ InstancePtr->IsSend = 0;
+
+ if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+ ((InstancePtr->IsRepeatedStart) !=0))
+ {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+ (u32)XIICPS_CR_HOLD_MASK);
+ }
+
+ /*
+ * Initialize for a master receiving role.
+ */
+ (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+ /*
+ * Setup the transfer size register so the slave knows how much
+ * to send to us.
+ */
+ if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+ InstancePtr->UpdateTxSize = 1;
+ }else {
+ InstancePtr->CurrByteCount = ByteCount;
+ XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+ (u32)ByteCount);
+ InstancePtr->UpdateTxSize = 0;
+ }
+
+ XIicPs_EnableInterrupts(BaseAddr,
+ (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+ (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+ (u32)XIICPS_IXR_ARB_LOST_MASK);
+ /*
+ * Do the address transfer to signal the slave.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the send buffer.
+* @param ByteCount is the number of bytes to be sent.
+* @param SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+* - XST_SUCCESS if everything went well.
+* - XST_FAILURE if timed out.
+*
+* @note This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+ s32 ByteCount, u16 SlaveAddr)
+{
+ u32 IntrStatusReg;
+ u32 StatusReg;
+ u32 BaseAddr;
+ u32 Intrs;
+ _Bool Value;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsgPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->SendBufferPtr = MsgPtr;
+ InstancePtr->SendByteCount = ByteCount;
+
+ if (((InstancePtr->IsRepeatedStart) != 0) ||
+ ((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+ (u32)XIICPS_CR_HOLD_MASK);
+ }
+
+ (void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+ /*
+ * Intrs keeps all the error-related interrupts.
+ */
+ Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+ (u32)XIICPS_IXR_NACK_MASK;
+
+ /*
+ * Clear the interrupt status register before use it to monitor.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Transmit first FIFO full of data.
+ */
+ (void)TransmitFifoFill(InstancePtr);
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+ /*
+ * Continue sending as long as there is more data and
+ * there are no errors.
+ */
+ Value = ((InstancePtr->SendByteCount > (s32)0) &&
+ ((IntrStatusReg & Intrs) == (u32)0U));
+ while (Value != FALSE) {
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ /*
+ * Wait until transmit FIFO is empty.
+ */
+ if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+ XIICPS_ISR_OFFSET);
+ Value = ((InstancePtr->SendByteCount > (s32)0) &&
+ ((IntrStatusReg & Intrs) == (u32)0U));
+ continue;
+ }
+
+ /*
+ * Send more data out through transmit FIFO.
+ */
+ (void)TransmitFifoFill(InstancePtr);
+ Value = ((InstancePtr->SendByteCount > (s32)0) &&
+ ((IntrStatusReg & Intrs) == (u32)0U));
+ }
+
+ /*
+ * Check for completion of transfer.
+ */
+ while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ /*
+ * If there is an error, tell the caller.
+ */
+ if ((IntrStatusReg & Intrs) != 0U) {
+ return (s32)XST_FAILURE;
+ }
+ }
+
+ if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the receive buffer.
+* @param ByteCount is the number of bytes to be received.
+* @param SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+* - XST_SUCCESS if everything went well.
+* - XST_FAILURE if timed out.
+*
+* @note This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+ s32 ByteCount, u16 SlaveAddr)
+{
+ u32 IntrStatusReg;
+ u32 Intrs;
+ u32 StatusReg;
+ u32 BaseAddr;
+ s32 Result;
+ s32 IsHold;
+ s32 UpdateTxSize = 0;
+ s32 ByteCountVar = ByteCount;
+ u32 Platform;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsgPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->RecvBufferPtr = MsgPtr;
+ InstancePtr->RecvByteCount = ByteCountVar;
+
+ Platform = XGetPlatform_Info();
+
+ if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+ ((InstancePtr->IsRepeatedStart) !=0))
+ {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+ (u32)XIICPS_CR_HOLD_MASK);
+ IsHold = 1;
+ } else {
+ IsHold = 0;
+ }
+
+ (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+ /*
+ * Clear the interrupt status register before use it to monitor.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+
+ /*
+ * Set up the transfer size register so the slave knows how much
+ * to send to us.
+ */
+ if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+ UpdateTxSize = 1;
+ }else {
+ XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+ ByteCountVar);
+ }
+
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+ /*
+ * Intrs keeps all the error-related interrupts.
+ */
+ Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+ (u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+ /*
+ * Poll the interrupt status register to find the errors.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ while ((InstancePtr->RecvByteCount > 0) &&
+ ((IntrStatusReg & Intrs) == 0U)) {
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+ if (((InstancePtr->RecvByteCount <
+ XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+ ((!InstancePtr->IsRepeatedStart) != 0) &&
+ (UpdateTxSize == 0)) {
+ IsHold = 0;
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,
+ XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ XIicPs_RecvByte(InstancePtr);
+ ByteCountVar --;
+
+ if (Platform == (u32)XPLAT_ZYNQ) {
+ if ((UpdateTxSize != 0) &&
+ (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+ break;
+ }
+ }
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ }
+ if (Platform == (u32)XPLAT_ZYNQ) {
+ if ((UpdateTxSize != 0) &&
+ (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+ /* wait while fifo is full */
+ while (XIicPs_ReadReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET) !=
+ (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+ }
+
+ if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+ (s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+ XIICPS_FIFO_DEPTH;
+ } else {
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ InstancePtr->RecvByteCount -
+ XIICPS_FIFO_DEPTH);
+ UpdateTxSize = 0;
+ ByteCountVar = InstancePtr->RecvByteCount;
+ }
+ }
+ } else {
+ if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+ /*
+ * Clear the interrupt status register before use it to
+ * monitor.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+ if ((InstancePtr->RecvByteCount) >
+ (s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+ } else {
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ InstancePtr->RecvByteCount);
+ UpdateTxSize = 0;
+ ByteCountVar = InstancePtr->RecvByteCount;
+ }
+ }
+ }
+
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ }
+
+ if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ if ((IntrStatusReg & Intrs) != 0x0U) {
+ Result = (s32)XST_FAILURE;
+ }
+ else {
+ Result = (s32)XST_SUCCESS;
+ }
+
+ return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param SlaveAddr is the address of the slave we want to contact.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+ u32 BaseAddr;
+ u32 ConfigReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ /* Clear transfer size register */
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+ /*
+ * Enable slave monitor mode in control register.
+ */
+ ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+ ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+ (u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+ ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Set up interrupt flag for slave monitor interrupt.
+ * Dont enable NACK.
+ */
+ XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+ /*
+ * Initialize the slave monitor register.
+ */
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+ /*
+ * Set the slave address to start the slave address transmission.
+ */
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+ return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+ u32 BaseAddr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ /*
+ * Clear slave monitor control bit.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+ & (~XIICPS_CR_SLVMON_MASK));
+
+ /*
+ * wait for slv monitor control bit to be clear
+ */
+ while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+ & XIICPS_CR_SLVMON_MASK);
+ /*
+ * Clear interrupt flag for slave monitor interrupt.
+ */
+ XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+ return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+*
+* The interrupts that are handled are:
+* - DATA
+* This case is handled only for master receive data.
+* The master has to request for more data (if there is more data to
+* receive) and read the data from the FIFO .
+*
+* - COMP
+* If the Master is transmitting data and there is more data to be
+* sent then the data is written to the FIFO. If there is no more data to
+* be transmitted then a completion event is signalled to the upper layer
+* by calling the callback handler.
+*
+* If the Master is receiving data then the data is read from the FIFO and
+* the Master has to request for more data (if there is more data to
+* receive). If all the data has been received then a completion event
+* is signalled to the upper layer by calling the callback handler.
+* It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+* This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+* These interrupts are marked as error. This is signalled to the upper
+* layer by calling the callback handler.
+*
+*
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+ u32 IntrStatusReg;
+ u32 StatusEvent = 0U;
+ u32 BaseAddr;
+ u16 SlaveAddr;
+ s32 ByteCnt;
+ s32 IsHold;
+ u32 Platform;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ Platform = XGetPlatform_Info();
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+ (u32)XIICPS_ISR_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so no events are
+ * missed while processing this interrupt.
+ */
+ XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Use the Mask register AND with the Interrupt Status register so
+ * disabled interrupts are not processed.
+ */
+ IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+ ByteCnt = InstancePtr->CurrByteCount;
+
+ IsHold = 0;
+ if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+ IsHold = 1;
+ }
+
+ /*
+ * Send
+ */
+ if (((InstancePtr->IsSend) != 0) &&
+ ((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+ if (InstancePtr->SendByteCount > 0) {
+ MasterSendData(InstancePtr);
+ } else {
+ StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+ }
+ }
+
+
+ /*
+ * Receive
+ */
+ if (((!(InstancePtr->IsSend))!= 0) &&
+ ((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+ (0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+ while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+ XIICPS_SR_RXDV_MASK) != 0U) {
+ if (((InstancePtr->RecvByteCount <
+ XIICPS_DATA_INTR_DEPTH)!= 0U) && (IsHold != 0) &&
+ ((!InstancePtr->IsRepeatedStart)!= 0) &&
+ (InstancePtr->UpdateTxSize == 0)) {
+ IsHold = 0;
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,
+ XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ XIicPs_RecvByte(InstancePtr);
+ ByteCnt--;
+
+ if (Platform == (u32)XPLAT_ZYNQ) {
+ if ((InstancePtr->UpdateTxSize != 0) &&
+ (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+ break;
+ }
+ }
+ }
+
+ if (Platform == (u32)XPLAT_ZYNQ) {
+ if ((InstancePtr->UpdateTxSize != 0) &&
+ (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+ /* wait while fifo is full */
+ while (XIicPs_ReadReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET) !=
+ (u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+ }
+
+ if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+ (s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+ XIICPS_FIFO_DEPTH;
+ } else {
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ InstancePtr->RecvByteCount -
+ XIICPS_FIFO_DEPTH);
+ InstancePtr->UpdateTxSize = 0;
+ ByteCnt = InstancePtr->RecvByteCount;
+ }
+ }
+ } else {
+ if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+ /*
+ * Clear the interrupt status register before use it to
+ * monitor.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+ if ((InstancePtr->RecvByteCount) >
+ (s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ XIICPS_MAX_TRANSFER_SIZE);
+ ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+ } else {
+ XIicPs_WriteReg(BaseAddr,
+ XIICPS_TRANS_SIZE_OFFSET,
+ InstancePtr->RecvByteCount);
+ InstancePtr->UpdateTxSize = 0;
+ ByteCnt = InstancePtr->RecvByteCount;
+ }
+ XIicPs_EnableInterrupts(BaseAddr,
+ (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+ (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+ (u32)XIICPS_IXR_ARB_LOST_MASK);
+ }
+ }
+ InstancePtr->CurrByteCount = ByteCnt;
+ }
+
+ if (((!(InstancePtr->IsSend)) != 0) &&
+ (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+ /*
+ * If all done, tell the application.
+ */
+ if (InstancePtr->RecvByteCount == 0){
+ if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,
+ XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+ }
+ }
+
+
+ /*
+ * Slave ready interrupt, it is only meaningful for master mode.
+ */
+ if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+ StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+ }
+
+ if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+ if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,
+ XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ StatusEvent |= XIICPS_EVENT_NACK;
+ }
+
+ /*
+ * Arbitration lost interrupt
+ */
+ if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+ StatusEvent |= XIICPS_EVENT_ARB_LOST;
+ }
+
+ /*
+ * All other interrupts are treated as error.
+ */
+ if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+ XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+ XIICPS_IXR_RX_OVR_MASK))) {
+ if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(BaseAddr,
+ XIICPS_CR_OFFSET) &
+ (~XIICPS_CR_HOLD_MASK));
+ }
+ StatusEvent |= XIICPS_EVENT_ERROR;
+ }
+
+ /*
+ * Signal application if there are any events.
+ */
+ if (StatusEvent != 0U) {
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ StatusEvent);
+ }
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @param Role specifies whether the device is sending or receiving.
+*
+* @return
+* - XST_SUCCESS if everything went well.
+* - XST_FAILURE if bus is busy.
+*
+* @note Interrupts are always disabled, device which needs to use
+* interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+ u32 ControlReg;
+ u32 BaseAddr;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+ /*
+ * Only check if bus is busy when repeated start option is not set.
+ */
+ if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+ if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+ return (s32)XST_FAILURE;
+ }
+ }
+
+ /*
+ * Set up master, AckEn, nea and also clear fifo.
+ */
+ ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+ (u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+ if (Role == RECVING_ROLE) {
+ ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+ }else {
+ ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+ }
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+ XIicPs_DisableAllInterrupts(BaseAddr);
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+ (void)TransmitFifoFill(InstancePtr);
+
+ /*
+ * Clear hold bit if done, so stop can be sent out.
+ */
+ if (InstancePtr->SendByteCount == 0) {
+
+ /*
+ * If user has enabled repeated start as an option,
+ * do not disable it.
+ */
+ if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ (u32)XIICPS_CR_OFFSET,
+ XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ (u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+ }
+ }
+
+ return;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..4ef69a1a0d0beff86be8068dd10a9a43164acb10
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
@@ -0,0 +1,497 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
+* to achieve I2C clock with minimum error.
+* This is a fix for CR #674195
+* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
+* This is fix for CR#704398 to remove warning.
+* 2.0 hk 03/07/14 Limited frequency set when 100KHz or 400KHz is
+* selected. This is a hardware limitation. CR#779290.
+* 2.1 hk 04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3 sk 10/07/14 Repeated start feature removed.
+* 3.0 sk 12/06/14 Implemented Repeated start feature.
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+ {XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+ {XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+ {XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+ {XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on. One or more bit
+* values may be contained in the mask. See the bit definitions
+* named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_IS_STARTED if the device is currently transferring
+* data. The transfer must complete or be aborted before setting
+* options.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+ u32 ControlReg;
+ u32 Index;
+ u32 OptionsVar = Options;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_CR_OFFSET);
+
+ /*
+ * If repeated start option is requested, set the flag.
+ * The hold bit in CR will be written by driver when the next transfer
+ * is initiated.
+ */
+ if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
+ InstancePtr->IsRepeatedStart = 1;
+ OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+ }
+
+ /*
+ * Loop through the options table, turning the option on.
+ */
+ for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+ if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+ /*
+ * 10-bit option is specially treated, because it is
+ * using the 7-bit option, so turning it on means
+ * turning 7-bit option off.
+ */
+ if ((OptionsTable[Index].Option &
+ XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+ /* Turn 7-bit off */
+ ControlReg &= ~OptionsTable[Index].Mask;
+ } else {
+ /* Turn 7-bit on */
+ ControlReg |= OptionsTable[Index].Mask;
+ }
+ }
+ }
+
+ /*
+ * Now write to the control register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+ ControlReg);
+
+ /*
+ * Keep a copy of what options this instance has.
+ */
+ InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param Options contains the specified options to be cleared. This is a
+* bit mask where a 1 means to turn the option off. One or more bit
+* values may be contained in the mask. See the bit definitions
+* named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_IS_STARTED if the device is currently transferring
+* data. The transfer must complete or be aborted before setting
+* options.
+*
+* @note None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+ u32 ControlReg;
+ u32 Index;
+ u32 OptionsVar = Options;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_CR_OFFSET);
+
+ /*
+ * If repeated start option is cleared, set the flag.
+ * The hold bit in CR will be cleared by driver when the
+ * following transfer ends.
+ */
+ if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+ InstancePtr->IsRepeatedStart = 0;
+ OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+ }
+
+ /*
+ * Loop through the options table and clear the specified options.
+ */
+ for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+ if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+ /*
+ * 10-bit option is specially treated, because it is
+ * using the 7-bit option, so clearing it means turning
+ * 7-bit option on.
+ */
+ if ((OptionsTable[Index].Option &
+ XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+ /* Turn 7-bit on */
+ ControlReg |= OptionsTable[Index].Mask;
+ } else {
+
+ /* Turn 7-bit off */
+ ControlReg &= ~OptionsTable[Index].Mask;
+ }
+ }
+ }
+
+
+ /*
+ * Now write the control register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+ ControlReg);
+
+ /*
+ * Keep a copy of what options this instance has.
+ */
+ InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return 32 bit mask of the options, where a 1 means the option is on,
+* and a 0 means to the option is off. One or more bit values may
+* be contained in the mask. See the bit definitions named
+* XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+ u32 OptionsFlag = 0U;
+ u32 ControlReg;
+ u32 Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read control register to find which options are currently set.
+ */
+ ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table to determine which options are set.
+ */
+ for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+ if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+ OptionsFlag |= OptionsTable[Index].Option;
+ }
+ if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+ OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+ }
+ }
+
+ if (InstancePtr->IsRepeatedStart != 0 ) {
+ OptionsFlag |= XIICPS_REP_START_OPTION;
+ }
+ return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param FsclHz is the clock frequency in Hz. The two most common clock
+* rates are 100KHz and 400KHz.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_IS_STARTED if the device is currently transferring
+* data. The transfer must complete or be aborted before setting
+* options.
+* - XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+ u32 Div_a;
+ u32 Div_b;
+ u32 ActualFscl;
+ u32 Temp;
+ u32 TempLimit;
+ u32 LastError;
+ u32 BestError;
+ u32 CurrentError;
+ u32 ControlReg;
+ u32 CalcDivA;
+ u32 CalcDivB;
+ u32 BestDivA;
+ u32 BestDivB;
+ u32 FsclHzVar = FsclHz;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(FsclHzVar > 0U);
+
+ if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+ XIICPS_TRANS_SIZE_OFFSET)) {
+ return (s32)XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+ */
+ Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+ /*
+ * If the answer is negative or 0, the Fscl input is out of range.
+ */
+ if ((u32)(0U) == Temp) {
+ return (s32)XST_FAILURE;
+ }
+
+ /*
+ * If frequency 400KHz is selected, 384.6KHz should be set.
+ * If frequency 100KHz is selected, 90KHz should be set.
+ * This is due to a hardware limitation.
+ */
+ if(FsclHzVar > (u32)384600U) {
+ FsclHzVar = (u32)384600U;
+ }
+
+ if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
+ FsclHzVar = (u32)90000U;
+ }
+
+ /*
+ * TempLimit helps in iterating over the consecutive value of Temp to
+ * find the closest clock rate achievable with divisors.
+ * Iterate over the next value only if fractional part is involved.
+ */
+ TempLimit = (((InstancePtr->Config.InputClockHz) %
+ ((u32)22 * FsclHzVar)) != (u32)0x0U) ?
+ Temp + (u32)1U : Temp;
+ BestError = FsclHzVar;
+
+ BestDivA = 0U;
+ BestDivB = 0U;
+ for ( ; Temp <= TempLimit ; Temp++)
+ {
+ LastError = FsclHzVar;
+ CalcDivA = 0U;
+ CalcDivB = 0U;
+
+ for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+ Div_a = Temp / (Div_b + 1U);
+
+ if (Div_a != 0U){
+ Div_a = Div_a - (u32)1U;
+ }
+ if (Div_a > 3U){
+ continue;
+ }
+ ActualFscl = (InstancePtr->Config.InputClockHz) /
+ (22U * (Div_a + 1U) * (Div_b + 1U));
+
+ if (ActualFscl > FsclHzVar){
+ CurrentError = (ActualFscl - FsclHzVar);}
+ else{
+ CurrentError = (FsclHzVar - ActualFscl);}
+
+ if (LastError > CurrentError) {
+ CalcDivA = Div_a;
+ CalcDivB = Div_b;
+ LastError = CurrentError;
+ }
+ }
+
+ /*
+ * Used to capture the best divisors.
+ */
+ if (LastError < BestError) {
+ BestError = LastError;
+ BestDivA = CalcDivA;
+ BestDivB = CalcDivB;
+ }
+ }
+
+
+ /*
+ * Read the control register and mask the Divisors.
+ */
+ ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ (u32)XIICPS_CR_OFFSET);
+ ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+ ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+ (BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+ ControlReg);
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return The value of the IIC clock to the nearest Hz based on the
+* control register settings. The actual value may not be exact to
+* to integer math rounding errors.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+ u32 ControlReg;
+ u32 ActualFscl;
+ u32 Div_a;
+ u32 Div_b;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_CR_OFFSET);
+
+ Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+ Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+ ActualFscl = (InstancePtr->Config.InputClockHz) /
+ (22U * (Div_a + 1U) * (Div_b + 1U));
+
+ return ActualFscl;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e68cb62ac11e58cae8dce66a1c57e71075eea1c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm 09/22/11 Removed unused code
+* 3.0 sk 11/03/14 Removed TimeOut Register value check
+* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE 0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_REGISTER_ERROR indicates a register did not read or write
+* correctly
+*
+* @note None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /*
+ * All the IIC registers should be in their default state right now.
+ */
+ if ((XIICPS_CR_RESET_VALUE !=
+ XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_CR_OFFSET)) ||
+ (XIICPS_IXR_ALL_INTR_MASK !=
+ XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_IMR_OFFSET))) {
+ return (s32)XST_FAILURE;
+ }
+
+ XIicPs_Reset(InstancePtr);
+
+ /*
+ * Write, Read then write a register
+ */
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+ if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XIICPS_SLV_PAUSE_OFFSET)) {
+ return (s32)XST_FAILURE;
+ }
+
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+ XIicPs_Reset(InstancePtr);
+
+ return (s32)XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..a5724c246a5cc6b99957cdf52a591b71a36017eb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return A pointer to the configuration found or NULL if the specified
+* device ID was not found. See xiicps.h for the definition of
+* XIicPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+ XIicPs_Config *CfgPtr = NULL;
+ s32 Index;
+
+ for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+ if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XIicPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XIicPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
new file mode 100644
index 0000000000000000000000000000000000000000..fb891920120edee398a98827118d1b48d0d1736e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
@@ -0,0 +1,595 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Handles slave transfers
+*
+*
MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -- -------- ---------------------------------------------
+* 1.00a jz 01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param SlaveAddr is the address of the slave we are receiving from.
+*
+* @return None.
+*
+* @note
+* Interrupt is always enabled no matter the tranfer is interrupt-
+* driven or polled mode. Whether device will be interrupted or not
+* depends on whether the device is connected to an interrupt
+* controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+ u32 ControlReg;
+ u32 BaseAddr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+ /*
+ * Set up master, AckEn, nea and also clear fifo.
+ */
+ ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+ ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+ ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+ XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+ ControlReg);
+
+ XIicPs_DisableAllInterrupts(BaseAddr);
+
+ XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+ return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the send buffer.
+* @param ByteCount is the number of bytes to be sent.
+*
+* @return None.
+*
+* @note This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+ u32 BaseAddr;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsgPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->SendBufferPtr = MsgPtr;
+ InstancePtr->SendByteCount = ByteCount;
+ InstancePtr->RecvBufferPtr = NULL;
+
+ XIicPs_EnableInterrupts(BaseAddr,
+ (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+ (u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+ (u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the receive buffer.
+* @param ByteCount is the number of bytes to be received.
+*
+* @return None.
+*
+* @note This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(MsgPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+ InstancePtr->RecvBufferPtr = MsgPtr;
+ InstancePtr->RecvByteCount = ByteCount;
+ InstancePtr->SendBufferPtr = NULL;
+
+ XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+ (u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+ (u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+ (u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends a buffer in polled mode as a slave.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the send buffer.
+* @param ByteCount is the number of bytes to be sent.
+*
+* @return
+* - XST_SUCCESS if everything went well.
+* - XST_FAILURE if master sends us data or master terminates the
+* transfer before all data has sent out.
+*
+* @note This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+ u32 IntrStatusReg;
+ u32 StatusReg;
+ u32 BaseAddr;
+ s32 Tmp;
+ s32 BytesToSend;
+ s32 Error = 0;
+ s32 Status = (s32)XST_SUCCESS;
+ _Bool Value;
+ _Bool Result;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsgPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->SendBufferPtr = MsgPtr;
+ InstancePtr->SendByteCount = ByteCount;
+
+ /*
+ * Use RXRW bit in status register to wait master to start a read.
+ */
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+ (Error == 0));
+ while (Result != FALSE) {
+
+ /*
+ * If master tries to send us data, it is an error.
+ */
+ if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+ Error = 1;
+ }
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+ (Error == 0));
+ }
+
+ if (Error != 0) {
+ Status = (s32)XST_FAILURE;
+ } else {
+
+ /*
+ * Clear the interrupt status register.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Send data as long as there is more data to send and
+ * there are no errors.
+ */
+ Value = (InstancePtr->SendByteCount > (s32)0) &&
+ ((Error == 0));
+ while (Value != FALSE) {
+
+ /*
+ * Find out how many can be sent.
+ */
+ BytesToSend = InstancePtr->SendByteCount;
+ if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+ BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+ }
+
+ for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+ XIicPs_SendByte(InstancePtr);
+ }
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ /*
+ * Wait for master to read the data out of fifo.
+ */
+ while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+ (Error == 0)) {
+
+ /*
+ * If master terminates the transfer before all data is
+ * sent, it is an error.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+ XIICPS_ISR_OFFSET);
+ if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+ Error = 1;
+ }
+
+ /* Clear ISR.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+ IntrStatusReg);
+
+ StatusReg = XIicPs_ReadReg(BaseAddr,
+ XIICPS_SR_OFFSET);
+ }
+ Value = ((InstancePtr->SendByteCount > (s32)0) &&
+ (Error == 0));
+ }
+ }
+ if (Error != 0) {
+ Status = (s32)XST_FAILURE;
+ }
+
+ return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+* @param MsgPtr is the pointer to the receive buffer.
+* @param ByteCount is the number of bytes to be received.
+*
+* @return
+* - XST_SUCCESS if everything went well.
+* - XST_FAILURE if timed out.
+*
+* @note This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+ u32 IntrStatusReg;
+ u32 StatusReg;
+ u32 BaseAddr;
+ s32 Count;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(MsgPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+ InstancePtr->RecvBufferPtr = MsgPtr;
+ InstancePtr->RecvByteCount = ByteCount;
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ /*
+ * Clear the interrupt status register.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Clear the status register.
+ */
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ Count = InstancePtr->RecvByteCount;
+ while (Count > (s32)0) {
+
+ /* Wait for master to put data */
+ while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ /*
+ * If master terminates the transfer before we get all
+ * the data or the master tries to read from us,
+ * it is an error.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+ XIICPS_ISR_OFFSET);
+ if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+ XIICPS_IXR_COMP_MASK))!=0x0U) &&
+ ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+ ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+ return (s32)XST_FAILURE;
+ }
+
+ /*
+ * Clear the interrupt status register.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+ IntrStatusReg);
+ }
+
+ /*
+ * Read all data from FIFO.
+ */
+ while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+ ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+ XIicPs_RecvByte(InstancePtr);
+
+ StatusReg = XIicPs_ReadReg(BaseAddr,
+ XIICPS_SR_OFFSET);
+ }
+ Count = InstancePtr->RecvByteCount;
+ }
+
+ return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+*
+*
+* The interrupts that are handled are:
+* - DATA
+* If the instance is sending, it means that the master wants to read more
+* data from us. Send more data, and check whether we are done with this
+* send.
+*
+* If the instance is receiving, it means that the master has writen
+* more data to us. Receive more data, and check whether we are done with
+* with this receive.
+*
+* - COMP
+* This marks that stop sequence has been sent from the master, transfer
+* is about to terminate. However, for receiving, the master may have
+* written us some data, so receive that first.
+*
+* It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+* This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+* These interrupts are marked as error.
+*
+*
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+ u32 IntrStatusReg;
+ u32 IsSend = 0U;
+ u32 StatusEvent = 0U;
+ s32 LeftOver;
+ u32 BaseAddr;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so no events are missed
+ * while processing this interrupt.
+ */
+ XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+ /*
+ * Use the Mask register AND with the Interrupt Status register so
+ * disabled interrupts are not processed.
+ */
+ IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+ /*
+ * Determine whether the device is sending.
+ */
+ if (InstancePtr->RecvBufferPtr == NULL) {
+ IsSend = 1U;
+ }
+
+ /* Data interrupt
+ *
+ * This means master wants to do more data transfers.
+ * Also check for completion of transfer, signal upper layer if done.
+ */
+ if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+ if (IsSend != 0x0U) {
+ LeftOver = TransmitFifoFill(InstancePtr);
+ /*
+ * We may finish send here
+ */
+ if (LeftOver == 0) {
+ StatusEvent |=
+ XIICPS_EVENT_COMPLETE_SEND;
+ }
+ } else {
+ LeftOver = SlaveRecvData(InstancePtr);
+
+ /* We may finish the receive here */
+ if (LeftOver == 0) {
+ StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+ }
+ }
+ }
+
+ /*
+ * Complete interrupt.
+ *
+ * In slave mode, it means the master has done with this transfer, so
+ * we signal the application using completion event.
+ */
+ if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+ if (IsSend != 0x0U) {
+ if (InstancePtr->SendByteCount > 0) {
+ StatusEvent |= XIICPS_EVENT_ERROR;
+ }else {
+ StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+ }
+ } else {
+ LeftOver = SlaveRecvData(InstancePtr);
+ if (LeftOver > 0) {
+ StatusEvent |= XIICPS_EVENT_ERROR;
+ } else {
+ StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+ }
+ }
+ }
+
+ /*
+ * Nack interrupt, pass this information to application.
+ */
+ if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+ StatusEvent |= XIICPS_EVENT_NACK;
+ }
+
+ /*
+ * All other interrupts are treated as error.
+ */
+ if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+ XIICPS_IXR_RX_UNF_MASK |
+ XIICPS_IXR_TX_OVR_MASK |
+ XIICPS_IXR_RX_OVR_MASK))){
+
+ StatusEvent |= XIICPS_EVENT_ERROR;
+ }
+
+ /*
+ * Signal application if there are any events.
+ */
+ if ((u32)0U != StatusEvent) {
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ StatusEvent);
+ }
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param InstancePtr is a pointer to the XIicPs instance.
+*
+* @return Number of bytes still expected by the instance.
+*
+* @note None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+ u32 StatusReg;
+ u32 BaseAddr;
+
+ BaseAddr = InstancePtr->Config.BaseAddress;
+
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+ while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+ ((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+ XIicPs_RecvByte(InstancePtr);
+ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+ }
+
+ return InstancePtr->RecvByteCount;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
new file mode 100644
index 0000000000000000000000000000000000000000..c33322c73a3a6b80f888f41aecd78b16e520134e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
@@ -0,0 +1,1571 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added logic to XQspiPs_GetReadData to handle data
+* shift for normal data reads and instruction/status
+* reads differently based on the ShiftReadData flag.
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* This version of the driver fixes CRs 670197/663787.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+* function
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+ u8 OpCode; /**< Operational code of the instruction */
+ u8 InstSize; /**< Size of the instruction including address bytes */
+ u8 TxOffset; /**< Register address where instruction has to be
+ written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+ { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+ /* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+* - Master mode
+* - Active high clock polarity
+* - Clock phase 0
+* - Baud rate divisor 2
+* - Transfer width 32
+* - Master reference clock = pclk
+* - No chip select active
+* - Manual CS and Manual Start disabled
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific QSPI device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is busy, disallow the initialize and return a status
+ * indicating it is already started. This allows the user to stop the
+ * device and re-initialize, but prevents a user from inadvertently
+ * initializing. This assumes the busy flag is cleared at startup.
+ */
+ if (InstancePtr->IsBusy == TRUE) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->StatusHandler = StubStatusHandler;
+
+ InstancePtr->SendBufferPtr = NULL;
+ InstancePtr->RecvBufferPtr = NULL;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+ /*
+ * Reset the QSPI device to get it into its initial state. It is
+ * expected that device configuration will take place after this
+ * initialization is done, but before the device is started.
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Abort any transfer that is in progress
+ */
+ XQspiPs_Abort(InstancePtr);
+
+ /*
+ * Write default value to configuration register.
+ * Do not modify reserved bits.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+ u32 IsLock;
+
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * QSPI Software Reset
+ */
+ IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+ SLCR_UNLOCK_MASK);
+ }
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+ LQSPI_RST_CTRL_MASK);
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+ SLCR_LOCK_MASK);
+ }
+
+ /*
+ * Set the RX and TX FIFO threshold to reset value (one)
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+*
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+*
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ unsigned int Index;
+ u8 TransCount = 0;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+
+ CurrInst = &NewInst[0];
+
+ /*
+ * The RecvBufPtr argument can be null
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared in the ISR when the
+ * transfer is entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ /*
+ * Clear all the interrrupts.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3) ) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used
+ * The InstSize mentioned in case of instructions greater than
+ * 4 bytes is not the actual size, but is indicative of
+ * the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch(ByteCount%4)
+ {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if( CurrInst->InstSize != 4 ) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ TransCount++;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if(SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Fill the Tx FIFO with as many bytes as it takes (or as many as
+ * we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ TransCount++;
+ }
+
+ /*
+ * Enable QSPI interrupts (connecting to the interrupt controller and
+ * enabling interrupts should have been done by the caller).
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If, in Manual Start mode, Start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+*
+*
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ u8 TransCount;
+ unsigned int Index;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+ u8 IsManualStart = FALSE;
+ u32 RxCount = 0;
+
+ CurrInst = &NewInst[0];
+ /*
+ * The RecvBufPtr argument can be NULL.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared when the transfer is
+ * entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3) ) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used.
+ * The InstSize mentioned in case of instructions greater than 4 bytes
+ * is not the actual size, but is indicative of the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch(ByteCount%4)
+ {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if(ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if( CurrInst->InstSize != 4 ) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+ TransCount = 0;
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ ++TransCount;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if(SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Check if manual start is selected and store it in a
+ * local varibale for reference. This is to avoid reading
+ * the config register everytime.
+ */
+ IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+ /*
+ * Fill the DTR/FIFO with as many bytes as it will take (or as
+ * many as we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ while((InstancePtr->RemainingBytes > 0) ||
+ (InstancePtr->RequestedBytes > 0)) {
+
+ /*
+ * Fill the TX FIFO with RX threshold no. of entries (or as
+ * many as we have to send, in case that's less).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (IsManualStart == TRUE) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Reset TransCount - this is only used to fill TX FIFO
+ * in the above loop;
+ * RxCount is used to keep track of data received
+ */
+ TransCount = 0;
+
+ /*
+ * Wait for RX FIFO to reach threshold (or)
+ * TX FIFO to become empty.
+ * The latter check is required for
+ * small transfers (<32 words) and
+ * when the last chunk in a large data transfer is < 32 words.
+ */
+
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+ ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
+
+ /*
+ * A transmit has just completed. Process received data
+ * and check for more data to transmit.
+ * First get the data received as a result of the
+ * transmit that just completed. Receive data based on the
+ * count obtained while filling tx fifo. Always get
+ * the received data, but only fill the receive
+ * buffer if it points to something (the upper layer
+ * software may not care to receive data).
+ */
+ while ((InstancePtr->RequestedBytes > 0) &&
+ (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
+ u32 Data;
+
+ RxCount++;
+
+ if (InstancePtr->RecvBufferPtr != NULL) {
+ if (InstancePtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(InstancePtr, Data,
+ InstancePtr->RequestedBytes);
+ } else {
+ (*(u32 *)InstancePtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RecvBufferPtr += 4;
+ InstancePtr->RequestedBytes -= 4;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RequestedBytes -= 4;
+ }
+ }
+ RxCount = 0;
+ }
+
+ /*
+ * If the Slave select lines are being manually controlled, disable
+ * them because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* @param Address is the starting address within the flash from
+* from where data needs to be read.
+* @param ByteCount contains the number of bytes to receive.
+*
+* @return
+* - XST_SUCCESS if read is performed
+* - XST_FAILURE if Linear mode is not set
+*
+* @note None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(RecvBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+ XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+ memcpy((void*)RecvBufPtr,
+ (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+ Address),
+ (size_t)ByteCount);
+ return XST_SUCCESS;
+ } else {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Disable the controller
+ */
+ XQspiPs_Disable(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if the slave is selected or deselected
+* successfully.
+* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+* changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Select the slave
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+*
+*
+* XST_SPI_TRANSFER_DONE The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
+* but there were none available in the transmit
+* register/FIFO. This typically means the slave
+* application did not issue a transfer request
+* fast enough, or the processor/driver could not
+* fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
+* but the receive data register/FIFO was full.
+*
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = FuncPtr;
+ InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param StatusEvent is the event that just occurred.
+* @param ByteCount is the number of bytes transferred up until the event
+* occurred.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount)
+{
+ (void) CallBackRef;
+ (void) StatusEvent;
+ (void) ByteCount;
+
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+* transmit register or FIFO is empty. The driver uses this interrupt during a
+* transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+* the QSPI device, when configured as a slave, attempts to read an empty
+* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
+* device data in a timely manner. No action is taken by the driver other than
+* to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+* QSPI device attempts to write a received byte to an already full DRR/FIFO.
+* A full DRR/FIFO usually means software is not emptying the data in a timely
+* manner. No action is taken by the driver other than to inform the upper
+* layer software of the error.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+ XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+ u32 IntrStatus;
+ u32 ConfigReg;
+ u32 Data;
+ u32 TransCount;
+ u32 Count = 0;
+ unsigned BytesDone; /* Number of bytes done so far. */
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Immediately clear the interrupts in case the ISR causes another
+ * interrupt to be generated. If we clear at the end of the ISR,
+ * we may miss newly generated interrupts. This occurs because we
+ * transmit from within the ISR, which could potentially cause another
+ * TX_EMPTY interrupt.
+ */
+ IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+ if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+ (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+ /*
+ * Rx FIFO has just reached threshold no. of entries.
+ * Read threshold no. of entries from RX FIFO
+ * Another possiblity of entering this loop is when
+ * the last byte has been transmitted and TX FIFO is empty,
+ * in which case, read all the data from RX FIFO.
+ * Always get the received data, but only fill the
+ * receive buffer if it is not null (it can be null when
+ * the device does not care to receive data).
+ */
+ TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ if (TransCount % 4) {
+ TransCount = TransCount/4 + 1;
+ } else {
+ TransCount = TransCount/4;
+ }
+
+ while ((Count < TransCount) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+ if (QspiPtr->RecvBufferPtr != NULL) {
+ if (QspiPtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(QspiPtr, Data,
+ QspiPtr->RequestedBytes);
+ } else {
+ (*(u32 *)QspiPtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RecvBufferPtr += 4;
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+
+ }
+ Count++;
+ }
+ Count = 0;
+ /*
+ * Interrupt asserted as TX_OW got asserted
+ * See if there is more data to send.
+ * Fill TX FIFO with RX threshold no. of entries or
+ * remaining entries (in case that is less than threshold)
+ */
+ while ((QspiPtr->RemainingBytes > 0) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ /*
+ * Send more data.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)QspiPtr->SendBufferPtr));
+ QspiPtr->SendBufferPtr += 4;
+ QspiPtr->RemainingBytes -= 4;
+ if (QspiPtr->RemainingBytes < 0) {
+ QspiPtr->RemainingBytes = 0;
+ }
+
+ Count++;
+ }
+
+ if ((QspiPtr->RemainingBytes == 0) &&
+ (QspiPtr->RequestedBytes == 0)) {
+ /*
+ * No more data to send. Disable the interrupt
+ * and inform the upper layer software that the
+ * transfer is done. The interrupt will be re-enabled
+ * when another transfer is initiated.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If the Slave select is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSFER_DONE,
+ QspiPtr->RequestedBytes);
+ } else {
+ /*
+ * Enable the TXOW interrupt.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(QspiPtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ }
+ }
+
+ /*
+ * Check for overflow and underflow errors.
+ */
+ if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_RECEIVE_OVERRUN, BytesDone);
+ }
+
+ if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+ QspiPtr->IsBusy = FALSE;
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Data is the data which needs to be copied to the Rx buffer.
+* @param Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+ u8 DataByte3;
+
+ if (InstancePtr->RecvBufferPtr) {
+ switch (Size) {
+ case 1:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0xFF000000) >> 24);
+ } else {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFF);
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ case 2:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0xFFFF0000) >> 16);
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ }
+ InstancePtr->RecvBufferPtr += 2;
+ break;
+ case 3:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0x00FFFF00) >> 8);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0xFF000000) >> 24);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0x00FF0000) >> 16);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ default:
+ /* This will never execute */
+ break;
+ }
+ }
+ InstancePtr->ShiftReadData = 0;
+ InstancePtr->RequestedBytes -= Size;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
new file mode 100644
index 0000000000000000000000000000000000000000..139ce4d3801b49f191a9b96ba36fa8f84a89f290
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
@@ -0,0 +1,799 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_4
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Linear Mode
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..d739e6218692f83914b733716e9b04a38fa64ac1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_QSPI_0_DEVICE_ID,
+ XPAR_PS7_QSPI_0_BASEADDR,
+ XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+ XPAR_PS7_QSPI_0_QSPI_MODE
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..1817b078069edce176d03884829b38f8da3d0c0c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk 09/17/13 First release
+* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+ u32 ConfigReg;
+
+ /*
+ * Disable interrupts
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_DISABLE_ALL);
+
+ /*
+ * Disable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ 0);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write default value to RX and TX threshold registers
+ * RX threshold should be set to 1 here because the corresponding
+ * status bit is used next to clear the RXFIFO
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+ (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+ (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+ /*
+ * Clear RXFIFO
+ */
+ while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+ XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+ }
+
+ /*
+ * Clear status register by reading register and
+ * writing 1 to clear the write to clear bits
+ */
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ /*
+ * Write default value to configuration register
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * De-select linear mode
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ 0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+ u32 BaudRateDiv;
+ u32 LinearCfg;
+ u32 ConfigReg;
+
+ /*
+ * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+ * should be set to 0x001; hence shift the value and use the mask.
+ */
+ BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+ XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+ /*
+ * Write configuration register with default values, slave selected &
+ * pre-scaler value for divide by 4
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+ ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write linear configuration register with default value -
+ * enable linear mode and use fast read.
+ */
+
+ if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_STACKED){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+ }
+
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ LinearCfg);
+
+ /*
+ * Enable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..96c867ad3383fe4303731581d63f41db1ffb9231
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_4
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Disable Register
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..1cd43f48c24d8ad0c3f8d9a58110eb01c74d1e32
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode. The driver doesnot support
+* Slave mode or the legacy mode.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+ {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+ {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+ {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+ {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+ {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on, and a 0 means to
+* turn the option off. One or more bit values may be contained in
+* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+* the file xqspips.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+ u32 ConfigReg;
+ unsigned int Index;
+ u32 QspiOptions;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow to modify the Control Register while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+ Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (Options & OptionsTable[Index].Option) {
+ /* Turn it on */
+ ConfigReg |= OptionsTable[Index].Mask;
+ } else {
+ /* Turn it off */
+ ConfigReg &= ~(OptionsTable[Index].Mask);
+ }
+ }
+
+ /*
+ * Now write the control register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+
+ if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET,
+ XQSPIPS_LQSPI_CR_RST_STATE);
+ XQspiPs_SetSlaveSelect(InstancePtr);
+ } else {
+ ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+ u32 OptionsFlag = 0;
+ u32 ConfigReg;
+ unsigned int Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the current options from QSPI configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table to grab options
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (ConfigReg & OptionsTable[Index].Mask) {
+ OptionsFlag |= OptionsTable[Index].Option;
+ }
+ }
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+ if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+ OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+ }
+
+ return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Prescaler is the value that determine how much the clock should
+* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+* in xqspips.h for this setting.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Read the configuration register, mask out the interesting bits, and set
+ * them with the shifted value passed into the function. Write the
+ * results back to the configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+ ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+ XQSPIPS_CR_PRESC_SHIFT;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+ return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is the delay to de-assert slave select between
+* two word transfers.
+* @param DelayBtwn is the delay between one Slave Select being
+* de-activated and the activation of another slave. The delay is
+* the number of master clock periods given by DelayBtwn + 2.
+* @param DelayAfter define the delay between the last bit of the current
+* byte transfer and the first bit of the next byte transfer.
+* The delay in number of master clock periods is given as:
+* CHPA=0:DelayInit+DelayAfter+3
+* CHPA=1:DelayAfter+1
+* @param DelayInit is the delay between asserting the slave select signal
+* and the first bit transfer. The delay int number of master clock
+* periods is DelayInit+1.
+*
+* @return
+* - XST_SUCCESS if delays are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the delays to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /* Shift, Mask and OR the values to build the register settings */
+ DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+ DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+ DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+ DelayRegister |= (u32) DelayInit;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET, DelayRegister);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is a pointer to the Delay to de-assert slave select
+* between two word transfers.
+* @param DelayBtwn is a pointer to the Delay Between transfers value.
+* This is a return parameter.
+* @param DelayAfter is a pointer to the Delay After transfer value.
+* This is a return parameter.
+* @param DelayInit is a pointer to the Delay Initially value. This is
+* a return parameter.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET);
+
+ *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+ *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+ XQSPIPS_DR_AFTER_SHIFT);
+
+ *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+ XQSPIPS_DR_BTWN_SHIFT);
+
+ *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+ XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..4c44cdff228c339490fde5308e2e63b7ee951cad
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
+* reset in the previous step.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if successful
+* - XST_REGISTER_ERROR indicates a register did not read or write
+* correctly.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+ int Status;
+ u8 DelayTestNss;
+ u8 DelayTestBtwn;
+ u8 DelayTestAfter;
+ u8 DelayTestInit;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ DelayTestNss = 0x5A;
+ DelayTestBtwn = 0xA5;
+ DelayTestAfter = 0xAA;
+ DelayTestInit = 0x55;
+
+ /*
+ * Write and read the delay register, just to be sure there is some
+ * hardware out there.
+ */
+ Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+ DelayTestAfter, DelayTestInit);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+ &DelayTestAfter, &DelayTestInit);
+ if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+ (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+ return XST_REGISTER_ERROR;
+ }
+
+ Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..929ecd8328692a24509cb53e7f8d7f44835712b3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+ XQspiPs_Config *CfgPtr = NULL;
+ int Index;
+
+ for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+ if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XQspiPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
new file mode 100644
index 0000000000000000000000000000000000000000..f6afc0e5ac381a97a898c16ffbd302341dd0b155
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
@@ -0,0 +1,1020 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+* "Config" entry is now made as pointer in the XScuGic
+* structure, necessary changes are made.
+* The HandlerTable can now be populated through the low
+* level routine XScuGic_RegisterHandler added in this
+* release. Hence necessary checks are added not to
+* overwrite the HandlerTable entriesin function
+* XScuGic_CfgInitialize.
+* 1.03a srt 02/27/13 Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* Removed Offset calculation macros, defined in _hw.h
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+* in function XScuGic_CfgInitialize is removed as it was
+* a bug.
+* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+* target CPU mapping
+* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
+* the current cpu to interrupt processor targets registers
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+* to interrupt target register to fix CR#951848
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+* for single core zynq-7000s
+* 3.5 mus 10/05/16 Modified DistributorInit function to avoid re-initialization of
+* distributor,If it is already initialized by other CPU.
+* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+* and properly mask interrupt target processor value to modify
+* interrupt target processor register for a given interrupt ID
+* and cpu ID
+* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+* interrupts in case they are being used only by current cpu.
+* It also removes current cpu from interrupt target registers
+* for all interrupts.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU. It fixes CR#992490.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for
+ * non-secure interrupts
+ * All are secure, so leave at the default. Set to 1 for non-secure
+ * interrupts.
+ */
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_IdBaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
+ XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ u32 Int_Id;
+ u32 Cpu_Id = CpuId + (u32)1;
+ (void) EffectiveAddr;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ /*
+ * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+ * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+ */
+#ifdef ARMA9
+ if ( XPAR_CPU_ID == 0x01 )
+ {
+ Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+ & EFUSE_STATUS_CPU_MASK ) == 0);
+ }
+#endif
+
+ if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+ InstancePtr->IsReady = 0U;
+ InstancePtr->Config = ConfigPtr;
+
+
+ for (Int_Id = 0U; Int_IdConfig->HandlerTable[Int_Id].Handler == NULL)) {
+ InstancePtr->Config->HandlerTable[Int_Id].Handler =
+ StubHandler;
+ }
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+ InstancePtr;
+ }
+ XScuGic_Stop(InstancePtr);
+ DistributorInit(InstancePtr, Cpu_Id);
+ CPUInitialize(InstancePtr);
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param Handler to the handler for that interrupt.
+* @param CallBackRef is the callback reference, usually the instance
+* pointer of the connecting driver.
+*
+* @return
+*
+* - XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef)
+{
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertNonvoid(Handler != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used as an index into the table to select the proper
+ * handler
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param Int_Id contains the ID of the interrupt source and should
+* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the interrupt such that it won't occur while disconnecting
+ * the handler, only disable the specified interrupt id without modifying
+ * the other interrupt ids
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+
+ /*
+ * Disconnect the handler and connect a stub, the callback reference
+ * must be set to this instance to allow unhandled interrupts to be
+ * tracked
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Enable the selected interrupt source by setting the
+ * corresponding bit in the Enable Set register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the selected interrupt source by setting the
+ * corresponding bit in the IDR.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller. This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode. A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id is the software interrupt ID to simulate an interrupt.
+* @param Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Int_Id <= 15U) ;
+ Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired interrupt. Int_Id currently limited to 0 - 15
+ * Use the target list for the Cpu ID.
+ */
+ Mask = ((Cpu_Id << 16U) | Int_Id) &
+ (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+ /*
+ * Write to the Software interrupt trigger register. Use the appropriate
+ * CPU Int_Id.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+ /* Indicate the interrupt was successfully simulated */
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+ /*
+ * verify that the inputs are valid
+ */
+ Xil_AssertVoid(CallBackRef != NULL);
+
+ /*
+ * Indicate another unhandled interrupt for stats
+ */
+ ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8 (248) is lowest. There are 32 priority levels
+* supported with a step of 8. Hence the supported priorities are
+* 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority;
+ LocalPriority = Priority;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue, Offset;
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+ RegValue |= ((Cpu_Id) << (Offset*8U));
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~ ( 1U << BitPos ));
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_IdInterrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..6765fd57e44d4f2e0997d399229d86ef463a2276
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUGIC_0_DEVICE_ID,
+ XPAR_PS7_SCUGIC_0_BASEADDR,
+ XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+ {{0}} /**< Initialize the HandlerTable to 0 */
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..6604e3a551d1baa7dfab473c5a6642b085aa6465
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
@@ -0,0 +1,649 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device. The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm 07/18/11 First release
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* Added support to direct interrupts to the appropriate CPU.
+* Earlier interrupts were directed to CPU1 (hard coded). Now
+* depending upon the CPU selected by the user (xparameters.h),
+* interrupts will be directed to the relevant CPU.
+* This fixes CR 699688.
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+*
+*
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+extern u32 CpuId;
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+ #warning "Building GIC for AMP"
+
+ /*
+ * The distrubutor should not be initialized by FreeRTOS in the case of
+ * AMP -- it is assumed that Linux is the master of this device in that
+ * case.
+ */
+ return;
+#endif
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for non-secure
+ * interrupts. All are secure, so leave at the default. Set to 1 for
+ * non-secure interrupts.
+ */
+
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_IdDistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_IdDistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_IdDistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+ }
+
+ for (Int_Id = 0U; Int_IdDistBaseAddress,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+
+ }
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param ConfigPtr is a pointer to a config table for the particular
+* device this driver is associated with.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask
+ * register
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+ 0xF0U);
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+ * interrupts Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+* this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+* space. The caller is responsible for keeping the address mapping
+* from EffectiveAddr to the device physical base address unchanged
+* once this function is invoked. Unexpected errors may occur if the
+* address mapping changes after this function is called. If address
+* translation is not used, use Config->BaseAddress for this parameters,
+* passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+ XScuGic_Config *Config;
+ u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
+
+ Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+ DistInit(Config, Cpu_Id);
+
+ CPUInit(Config);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param DeviceId is the unique identifier for the ScuGic device.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry *TablePtr;
+ XScuGic_Config *CfgPtr;
+
+ CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+ IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+ if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are
+ * multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on
+ * the IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+ if(TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains could happen
+ * here.
+ */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID. The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param BaseAddress is the CPU Interface Register base address of the
+* interrupt controller whose vector table will be modified.
+* @param InterruptId is the interrupt ID to be associated with the input
+* handler.
+* @param Handler is the function pointer that will be added to
+* the vector table for the given interrupt ID.
+* @param CallBackRef is the argument that will be passed to the new
+* handler function when it is called. This is user-specific.
+*
+* @return None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+ XScuGic_Config *CfgPtr;
+ CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+ if(CfgPtr != NULL) {
+ if( IntrHandler != NULL) {
+ CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+ }
+ if( CallBackRef != NULL) {
+ CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return A pointer to the configuration structure for the specified
+* device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+ CpuBaseAddress) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param BaseAddr is the device base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8 (248) is lowest. There are 32 priority levels
+* supported with a step of 8. Hence the supported priorities are
+* 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_SetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority = Priority;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param BaseAddr is the device base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_GetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~ ( 1U << BitPos ));
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
+}
+
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..d82a60b9e0f3b1cabc70e099deb86751a56f06a2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller. The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing. This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported. This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system. The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
+* since the HandlerTable has now moved to XScuGic_Config.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry *TablePtr;
+
+ /* Assert that the pointer to the instance is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the int_ack register to identify the highest priority interrupt ID
+ * and make sure it is valid. Reading Int_Ack will clear the interrupt
+ * in the GIC.
+ */
+ IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+ if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are multiple
+ * processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on the
+ * IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+ if(TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+ IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains could happen here.
+ */
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b1028f9f5208c3a72e8bc682a622472a4f80deb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUGIC_PCELL_ID 0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* - XST_SUCCESS if self-test is successful.
+* - XST_FAILURE if the self-test is not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+ u32 RegValue1 = 0U;
+ u32 Index;
+ s32 Status;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the ID registers.
+ */
+ for(Index=0U; Index<=3U; Index++) {
+ RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+ ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+ }
+
+ if(XSCUGIC_PCELL_ID != RegValue1){
+ Status = XST_FAILURE;
+ } else {
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..842f3181254b60ce05e2af821d73e801c6ab3e2a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique identifier for a device.
+*
+* @return A pointer to the XScuGic configuration structure for the
+* specified device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000000000000000000000000000000000000..9d477d971eac89fe821b93f90e85ca9565a44965
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function must be called
+* before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param ConfigPtr points to the XScuTimer configuration structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+ /*
+ * Copy configuration into the instance structure.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+ InstancePtr->IsStarted = (u32)0;
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ Status =(s32)XST_SUCCESS;
+ }
+ else {
+ Status = (s32)XST_DEVICE_IS_STARTED;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Set the 'timer enable' bit in the register.
+ */
+ Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'timer enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register.
+ */
+ ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+ /*
+ * Set the prescaler value.
+ */
+ ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+ /*
+ * Write the register with the new values.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+ return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..6ccfa915bcbdb81c3c2873eec700de5a3c610c57
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+ XPAR_PS7_SCUTIMER_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac7b42934796aa41e49adfc510057e951e0b2e0d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e37fef3bb77005e3111e97a5b15830ce42d30e0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if self test was not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+ s32 Status;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Save the contents of the Control Register and stop the timer.
+ */
+ CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Save the contents of the Load Register.
+ * Load a new test value in the Load Register, read it back and
+ * compare it with the written value.
+ */
+ LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+ XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+ Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+
+ /*
+ * Restore the contents of the Load Register and Control Register.
+ */
+ XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+ /*
+ * Return a Failure if the contents of the Load Register do not
+ * match with the value written to it.
+ */
+ if (Register != XSCUTIMER_SELFTEST_VALUE) {
+ Status = (s32)XST_FAILURE;
+ }
+ else {
+ Status = (s32)XST_SUCCESS;
+ }
+
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..3bcc57ebde32600b754f7a01d71ece0fb0eecbdb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+ XScuTimer_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+ if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuTimer_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..cd9e15d2c1b68de39483e33b9654894cfbdc1718
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,217 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 CfgStatus;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+ }
+ else {
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0U;
+
+ /*
+ * Put the watchdog timer in Watchdog mode.
+ */
+ XScuWdt_SetWdMode(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ CfgStatus =(s32)XST_SUCCESS;
+ }
+ return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note User needs to select the appropriate mode (watchdog/timer)
+* before using this API.
+* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+* xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Set the 'watchdog enable' bit in the register.
+ */
+ Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'watchdog enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..372bbc3439aadbb94cf3fe04b97535757d4d1107
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..5d6307d3408ae3e0a65c85aa9343bc5d4d1c7bfe
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUWDT_0_DEVICE_ID,
+ XPAR_PS7_SCUWDT_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2067d3a531870de0fe1851b65a2f653f58aa73f8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..95d50651030e1886a6bc176623c74ae986aeff68
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if the WDT is not decrementing.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+ s32 SelfTestStatus;
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Stop the watchdog timer.
+ */
+ CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+ LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_LOAD_OFFSET);
+ XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+ /*
+ * Start the watchdog timer and check if the watchdog counter is
+ * decrementing.
+ */
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_COUNTER_OFFSET);
+
+ XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+ XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+ if (Register == 0xFFFFFFFFU) {
+ SelfTestStatus = (s32)XST_FAILURE;
+ }
+ else {
+ SelfTestStatus = (s32)XST_SUCCESS;
+ }
+
+ return SelfTestStatus;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..c63eb9af03395e6ab4294af62a380205bba1c58f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+ XScuWdt_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+ if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuWdt_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
new file mode 100644
index 0000000000000000000000000000000000000000..8b1f11382d0c470d6837b306a17c851725d875d0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
@@ -0,0 +1,1763 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 07/17/17 Add support for running SD at 200MHz
+* mn 07/26/17 Fixed compilation warnings
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4 mn 10/17/17 Use different commands for single and multi block
+* transfers
+* mn 03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
+#define XSDPS_RESPOCR_READY 0x80000000U
+#define XSDPS_ACMD41_HCS 0x40000000U
+#define XSDPS_ACMD41_3V3 0x00300000U
+#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
+#define HIGH_SPEED_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define WIDTH_4_BIT_SUPPORT 0x4U
+#define SD_CLK_25_MHZ 25000000U
+#define SD_CLK_19_MHZ 19000000U
+#define SD_CLK_26_MHZ 26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE 196U
+#define EXT_CSD_SEC_COUNT_BYTE1 212U
+#define EXT_CSD_SEC_COUNT_BYTE2 213U
+#define EXT_CSD_SEC_COUNT_BYTE3 214U
+#define EXT_CSD_SEC_COUNT_BYTE4 215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
+#define CSD_SPEC_VER_3 0x3U
+#define SCR_SPEC_VER_3 0x80U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+u16 TransferMode;
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific SD device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note This function initializes the host controller.
+* Initial clock of 400KHz is set.
+* Voltage of 3.3V is selected as that is supported by host.
+* Interrupts status is enabled and signal disabled by default.
+* Default data direction is card to host and
+* 32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ u8 PowerLevel;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /* Set some default values. */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
+ InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
+ InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+ InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+ InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+ InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+ InstancePtr->SectorCount = 0;
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+ InstancePtr->Config_TapDelay = NULL;
+
+ /* Disable bus power and issue emmc hw reset */
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+ XSDPS_HC_SPEC_V3)
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+ else
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+ /* Delay to poweroff card */
+ (void)usleep(1000U);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_ALL_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ /* Host Controller version is read. */
+ InstancePtr->HC_Version =
+ (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+ /*
+ * Read capabilities register and update it in Instance pointer.
+ * It is sufficient to read this once on power on.
+ */
+ InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_CAPS_OFFSET);
+
+ /* Select voltage and enable bus power. */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+ ~XSDPS_PC_EMMC_HW_RST_MASK);
+ else
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+ /* Delay before issuing the command after emmc reset */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+ XSDPS_CAPS_EMB_SLOT)
+ usleep(200);
+
+ /* Change the clock frequency to 400 KHz */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH ;
+ }
+
+ if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+ } else {
+ PowerLevel = 0U;
+ }
+
+ /* Select voltage based on capability and enable bus power. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+#ifdef __aarch64__
+ /* Enable ADMA2 in 64bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_64_MASK);
+#else
+ /* Enable ADMA2 in 32bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_32_MASK);
+#endif
+
+ /* Enable all interrupt status except card interrupt initially */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_EN_OFFSET,
+ XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_EN_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* Disable all interrupt signals by default. */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+ /*
+ * Transfer mode register - default value
+ * DMA enabled, block count enabled, data direction card to host(read)
+ */
+ TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ /* Set block size to 512 by default */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+ initialization cycle failed
+*
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD8 and ACDM41 are sent to identify voltage and
+* high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 Arg;
+ u8 ReadReg;
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef UHS_MODE_ENABLE
+ InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * CMD8; response expected
+ * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+ */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+ XSDPS_CMD8_VOL_PATTERN, 0U);
+ if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (Status == XSDPS_CT_ERROR) {
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ }
+
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+ InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+ }
+ else {
+ InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+ }
+
+ RespOCR = 0U;
+ /* Send ACMD41 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+ /*
+ * There is no support to switch to 1.8V and use UHS mode on
+ * 1.0 silicon
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ Arg |= XSDPS_OCR_S18;
+ }
+
+ /* 0x40300000 - Host High Capacity support & 3.3V window */
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+ Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+ InstancePtr->Switch1v8 = 1U;
+ Status = XSdPs_Switch_Voltage(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+ do {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Relative card address is stored as the upper 16 bits
+ * This is to avoid shifting when sending commands
+ */
+ InstancePtr->RelCardAddr =
+ XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+ } while (InstancePtr->RelCardAddr == 0U);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+ BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+ } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+ InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+ 1U) * 1024U;
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+* initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static u8 ExtCsd[512];
+ u8 SCR[8] = { 0U };
+#pragma data_alignment = 4
+#else
+ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+ u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
+#endif
+ u8 ReadBuff[64] = { 0U };
+ s32 Status;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Default settings */
+ InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ InstancePtr->Switch1v8 = 0U;
+ InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ == XSDPS_CAPS_EMB_SLOT)) {
+ InstancePtr->CardType = XSDPS_CHIP_EMMC;
+ } else {
+ Status = XSdPs_IdentifyCard(InstancePtr);
+ if (Status == XST_FAILURE) {
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+ (InstancePtr->CardType != XSDPS_CARD_MMC) &&
+ (InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_SdCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Change clock to default clock 25MHz */
+ /*
+ * SD default speed mode timing should be closed at 19 MHz.
+ * The reason for this is SD requires a voltage level shifter.
+ * This limitation applies to ZynqMPSoC.
+ */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+ else
+ InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+ || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+ Status = XSdPs_MmcCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ /* Change clock to default clock 26MHz */
+ InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Select_Card(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ /* Pull-up disconnected during data transfer */
+ Status = XSdPs_Pullup(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Get speed supported by device */
+ Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+ (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Switch1v8 == 0U)) {
+ u16 CtrlReg, ClockReg;
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ InstancePtr->Switch1v8 = 1U;
+ }
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ if (InstancePtr->Switch1v8 != 0U) {
+
+ /* Identify the UHS mode supported by card */
+ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+ /* Set UHS-I SDR104 mode */
+ Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ } else {
+#endif
+ /*
+ * card supports CMD6 when SD_SPEC field in SCR register
+ * indicates that the Physical Layer Specification Version
+ * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+ */
+ if (SCR[0] != 0U) {
+ /* Check for high speed support */
+ if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ }
+#endif
+
+ } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+ (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+ (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+ /* Change bus width to 8-bit */
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Get Extended CSD */
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ /* Check for card supported speed */
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+ EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+ EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+ } else
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+
+ if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+ InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+ }
+
+ /* Enable Rst_n_Fun bit if it is disabled */
+ if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+ Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+ Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+ if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+ (InstancePtr->CardType == XSDPS_CARD_SD)) {
+ Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* 74 CLK delay after card is powered up, before the first command. */
+ usleep(XSDPS_INIT_DELAY);
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Host High Capacity support & High voltage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ } else {
+ InstancePtr->CardType = XSDPS_CARD_MMC;
+ }
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 CtrlReg;
+ u32 ReadReg, ClockReg;
+
+ /* Send switch voltage command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ }
+
+ /* Wait for CMD and DATA line to go low */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+ XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ /* Wait for CMD and DATA line to go high */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+ != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cmd is the command to be sent.
+* @param Arg is the argument to be sent along with the command.
+* This could be address or any other information
+* @param BlkCnt - Block count passed by the user.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+ u32 PresentStateReg;
+ u32 CommandReg;
+ u32 StatusReg;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check the command inhibit to make sure no other
+ * command transfer is in progress
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Write block count register */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+ /* Write argument register */
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSDPS_ARGMT_OFFSET, Arg);
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ /* Command register is set to trigger transfer of command */
+ CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+ /*
+ * Mask to avoid writing to reserved bits 31-30
+ * This is necessary because 0x80000000 is used by this software to
+ * distinguish between ACMD and CMD of same number
+ */
+ CommandReg = CommandReg & 0x3FFFU;
+
+ /*
+ * Check for data inhibit in case of command using DAT lines.
+ * For Tuning Commands DAT lines check can be ignored.
+ */
+ if ((Cmd != CMD21) && (Cmd != CMD19)) {
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+ XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+ ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+ (CommandReg << 16) | TransferMode);
+
+ /* Polling for response for now */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((Cmd == CMD21) || (Cmd == CMD19)) {
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+ break;
+ }
+ }
+
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET);
+ if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+ Status = XSDPS_CT_ERROR;
+ }
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET,
+ XSDPS_INTR_CC_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param Command to be sent.
+*
+* @return Command register value complete with response type and
+* data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+ u32 RetVal;
+
+ RetVal = Cmd;
+
+ switch(Cmd) {
+ case CMD0:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD1:
+ RetVal |= RESP_R3;
+ break;
+ case CMD2:
+ RetVal |= RESP_R2;
+ break;
+ case CMD3:
+ RetVal |= RESP_R6;
+ break;
+ case CMD4:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD5:
+ RetVal |= RESP_R1B;
+ break;
+ case CMD6:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ } else {
+ RetVal |= RESP_R1B;
+ }
+ break;
+ case ACMD6:
+ RetVal |= RESP_R1;
+ break;
+ case CMD7:
+ RetVal |= RESP_R1;
+ break;
+ case CMD8:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1;
+ } else {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ }
+ break;
+ case CMD9:
+ RetVal |= RESP_R2;
+ break;
+ case CMD11:
+ case CMD10:
+ case CMD12:
+ case ACMD13:
+ case CMD16:
+ RetVal |= RESP_R1;
+ break;
+ case CMD17:
+ case CMD18:
+ case CMD19:
+ case CMD21:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD23:
+ case ACMD23:
+ case CMD24:
+ case CMD25:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case ACMD41:
+ RetVal |= RESP_R3;
+ break;
+ case ACMD42:
+ RetVal |= RESP_R1;
+ break;
+ case ACMD51:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD52:
+ case CMD55:
+ RetVal |= RESP_R1;
+ break;
+ case CMD58:
+ break;
+ default :
+ RetVal |= Cmd;
+ break;
+ }
+
+ return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+ XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
+
+ /* Send multiple blocks read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ }
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send multiple blocks write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+ s32 Status = 0;
+
+ /* Send CMD7 - Select card */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+* @param Buff pointer to data buffer.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+ u32 TotalDescLines = 0U;
+ u32 DescNum = 0U;
+ u32 BlkSize = 0U;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET);
+ BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+ TotalDescLines = 1U;
+
+ }else {
+
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+#ifdef __aarch64__
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+ InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ /* This will write '0' to length field which indicates 65536 */
+ InstancePtr->Adma2_DescrTbl[DescNum].Length =
+ (u16)XSDPS_DESC_MAX_LENGTH;
+ }
+
+#ifdef __aarch64__
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+#ifdef __aarch64__
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+ (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
+#endif
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor) * 32U);
+ }
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) MMC is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the initialization
+* cycle failed
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD1 sent to identify voltage and high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ RespOCR = 0U;
+ /* Send CMD1 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+ /* Host High Capacity support & High volage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ /* Set relative card address */
+ InstancePtr->RelCardAddr = 0x12340000U;
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+ /* Calculating the memory capacity */
+ BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8d979d1d768214c5986d7899cbaa81ba5369c0d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+#ifdef __aarch64__
+ u64 Address; /**< Address of current dma transfer */
+#else
+ u32 Address; /**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
+ /**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..c427bed193ab214a1601c26b4a6bb41f61e6fb56
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
@@ -0,0 +1,62 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SD_0_DEVICE_ID,
+ XPAR_PS7_SD_0_BASEADDR,
+ XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+ XPAR_PS7_SD_0_HAS_CD,
+ XPAR_PS7_SD_0_HAS_WP,
+ XPAR_PS7_SD_0_BUS_WIDTH,
+ XPAR_PS7_SD_0_MIO_BANK,
+ XPAR_PS7_SD_0_HAS_EMIO,
+ XPAR_PS7_SD_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c63d8f62afe518b28b3a3fadbeb820a323d9ee81
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
@@ -0,0 +1,1301 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+*
+*
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * Normal and Error Interrupt Status Register
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * Normal and Error Interrupt Status Enable Register
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * Normal and Error Interrupt Signal Enable Register
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD0_ITAPDLYSEL_SD50 0x00000014U
+#define SD0_OTAPDLYSEL_SD50 0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD0_ITAPDLYSEL_HSD 0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
+#define SD1_ITAPDLYSEL_SD50 0x00140000U
+#define SD1_OTAPDLYSEL_SD50 0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
+#define SD1_ITAPDLYSEL_HSD 0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..4894754ad9c829e47c411d85cf3050fce92d1e16
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
@@ -0,0 +1,1760 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* vns 03/13/17 Fixed MISRAC mandatory violation
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
+* settings
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT 0x1U
+#define UHS_SDR25_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define UHS_SDR104_SUPPORT 0x8U
+#define UHS_DDR50_SUPPORT 0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+extern u16 TransferMode;
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param BlkSize - Block size passed by the user.
+*
+* @return None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+ s32 Status;
+ u32 PresentStateReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+
+ if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+ (u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+ (u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ /* Set block size to the value passed */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize & XSDPS_BLK_SIZE_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SCR - buffer to store SCR register returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+ s32 Status;
+ u32 StatusReg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+ SCR[LoopCnt] = 0U;
+ }
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ BlkCnt = XSDPS_SCR_BLKCNT;
+ BlkSize = XSDPS_SCR_BLKSIZE;
+
+ /* Set block size to the value passed */
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * check for bus width for 3.0 controller and return if
+ * bus width is <4
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+ Status = XST_SUCCESS;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+ 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+ Arg = ((u32)InstancePtr->BusWidth);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ && (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ /* in case of eMMC data width 8-bit */
+ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+ } else {
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+ }
+
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+ Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+ else
+ Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+ } else {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+ Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+ else
+ Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+
+ /* Width setting in controller */
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+ } else {
+ StatusReg |= XSDPS_HC_WIDTH_MASK;
+ }
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ (u8)StatusReg);
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+ StatusReg |= InstancePtr->Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, StatusReg);
+ }
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store function group support data
+* returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 50 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 52 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Arg = XSDPS_MMC_HS200_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+ } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+ } else {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+ StatusReg |= XSDPS_HC_SPEED_MASK;
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SelFreq - Clock frequency in Hz.
+*
+* @return None
+*
+* @note This API will change clock frequency to the value less than
+* or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+ u16 ClockReg;
+ u16 DivCnt;
+ u16 Divisor = 0U;
+ u16 ExtDivisor;
+ s32 Status;
+ u16 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+ (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+ /* Program the Tap delays */
+ XSdPs_SetTapDelay(InstancePtr);
+#endif
+ /* Calculate divisor */
+ for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt >> 1;
+ break;
+ }
+ }
+
+ if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ /* Calculate divisor */
+ DivCnt = 0x1U;
+ while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt / 2U;
+ break;
+ }
+ DivCnt = DivCnt << 1U;
+ }
+
+ if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Set clock divisor */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+ XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+ ExtDivisor = Divisor >> 8;
+ ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+ ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ } else {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ }
+
+ /* Wait for internal clock to stabilize */
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);;
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store EXT_CSD
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg = 0U;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+ BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send SEND_EXT_CSD command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Arg is the argument to be sent along with the command
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+ s32 Status;
+ u32 StatusReg;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff contains the response for CMD6
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+ InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+ InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+ InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+ }
+ else
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Mode UHS-I mode
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+ s32 Status;
+ u16 StatusReg;
+ u16 CtrlReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Drive strength */
+
+ /* Bus speed mode selection */
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ switch (Mode) {
+ case 0U:
+ Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+ break;
+ case 1U:
+ Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+ break;
+ case 2U:
+ Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+ break;
+ case 3U:
+ Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+ break;
+ case 4U:
+ Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+ break;
+ default:
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ break;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+ /* Current limit */
+
+ /* Set UHS mode in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+ CtrlReg |= Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /* Change the clock frequency */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+ (Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+ /* Send tuning pattern */
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 BlkSize;
+ u16 CtrlReg;
+ u8 TuningCount;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+ if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+ {
+ BlkSize = BlkSize*2U;
+ }
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /*
+ * workaround which can work for 1.0/2.0 silicon for auto tuning.
+ * This can be revisited for 3.0 silicon if necessary.
+ */
+ /* Wait for ~60 clock cycles to reset the tap values */
+ (void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+
+ for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+ } else {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+ }
+
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+ break;
+ }
+
+ if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+ }
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for ~12 clock cycles to synchronize the new tap values */
+ (void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (Bank == 2)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (Bank == 2)
+ TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (Bank == 2)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (Bank == 2)
+ TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+ (void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+ ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
+ 0, 0, 0, 0, 0);
+#else
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ TapDelay |= SD0_OTAPDLYSEL_SD50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+ ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
+ 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ TapDelay |= SD1_OTAPDLYSEL_SD50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ if (CardType== XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+ (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+ (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD0_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ if (CardType== XSDPS_CARD_SD)
+ TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ if (CardType== XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+ (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+ (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD1_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD0_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= SD0_ITAPDLYSEL_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD1_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= SD1_ITAPDLYSEL_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+ u32 DllCtrl, BankNum, DeviceId, CardType;
+
+ BankNum = InstancePtr->Config.BankNumber;
+ DeviceId = InstancePtr->Config.DeviceId ;
+ CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ DllCtrl |= SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#endif
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ DllCtrl |= SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+ u32 ClockReg, DllCtrl;
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+ /* Issue DLL Reset to load zero tap values */
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl |= SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl |= SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ }
+
+ /* Wait for 2 micro seconds */
+ (void)usleep(2U);
+
+ /* Release the DLL out of reset */
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..62bbfc0dd970b829313ac73dc643376893e025a5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+ XSdPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+ if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XSdPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf598882be91ac2d785f8bd8d3dc757b308ac775
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+ (void)status;
+ while (1) {
+ ;
+ }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
new file mode 100644
index 0000000000000000000000000000000000000000..a108b771620def28d60cda4cd26204429a2a9a18
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
new file mode 100644
index 0000000000000000000000000000000000000000..967bdfc5b0cca4d2143f41a804cdc5a716e75edd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+ static u8 *heap = NULL;
+ u8 *prev_heap;
+ static u8 *HeapEndPtr = (u8 *)&_heap_end;
+ caddr_t Status;
+
+ if (heap == NULL) {
+ heap = (u8 *)&_heap_start;
+ }
+ prev_heap = heap;
+
+ if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
+ heap += incr;
+ Status = (caddr_t) ((void *)prev_heap);
+ } else {
+ Status = (caddr_t) -1;
+ }
+
+ return Status;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
new file mode 100644
index 0000000000000000000000000000000000000000..e8988c04818685c56287b2de514e6c96cc2d6cb4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+ _exit(1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..9427ad0547683bdeaeddbeb91e26143b45d7811d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
@@ -0,0 +1,45 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0dab3e943010e6772ebd9511da2c5988a4b81dcf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
@@ -0,0 +1,549 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------
+ * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ * cacheable regions
+ * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ * generated by the cpu driver, for enabling caches
+ * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
+ * write-thru caches
+ * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
+ * Updated the MMU table to mark OCM in high address space
+ * as inner cacheable and reserved space as Invalid
+ * 3.03a sdm 08/20/11 Changes to support FreeRTOS
+ * Updated the MMU table to mark upper half of the DDR as
+ * non-cacheable
+ * Setup supervisor and abort mode stacks
+ * Do not initialize/enable L2CC in case of AMP
+ * Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ * in case of AMP
+ * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
+ * counters
+ * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
+ * xparameters.h file for CR630532 - Xil_DCacheFlush()/
+ * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ * for MicroBlaze will invalidate data in the cache instead
+ * of flushing it for writeback caches
+ * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+ * Remove redundant dsb/dmb instructions in cache maintenance
+ * APIs
+ * Remove redundant dsb in mcr instruction
+ * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
+ * driver tcl in xparameters.h. Update the gcc/translationtable.s
+ * for the QSPI complete address range - DT644567
+ * Removed profile directory for armcc compiler and changed
+ * profiling setting to false in standalone_v2_1_0.tcl file
+ * Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ * invalidate the caches before enabling back the MMU and
+ * D cache.
+ * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
+ * xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ * array, flush the D-cache before changing the attributes
+ * in translation table. The user need not call Xil_DisableMMU
+ * before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ * sgd initialization is present. Changes for this were done in
+ * uart.c and xil-crt0.s.
+ * Made changes in xil_io.c to use volatile pointers.
+ * Made changes in xil_mmu.c to correct the function
+ * Xil_SetTlbAttributes.
+ * Changes are made xil-crt0.s to initialize the static
+ * C++ constructors.
+ * Changes are made in boot.s, to fix the TTBR settings,
+ * correct the L2 Cache Auxiliary register settings, L2 cache
+ * latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ * sgd usleep.c to use global timer intstead of CP15.
+ * Made changes in cortexa9/gcc/translation_table.s to map
+ * the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/boot.S to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/translation_table.s to
+ * map the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/boot.S to optimize the
+ * L2 cache settings. Changes the section properties for
+ * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ * and cortexa9/gcc/translation_table.S.
+ * Made changes in cortexa9/xil_cache.c to change the
+ * cache invalidation order.
+ * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
+ * compilation/linking issues for C++ compiler.
+ * Made changes in mb_interface.h to remove compilation/
+ * linking issues for C++ compiler.
+ * Added macros for swapb and swaph microblaze instructions
+ * mb_interface.h
+ * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ * for CortexA9.
+ * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa 08/31/12 Added xil_printf.h include
+ * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
+ * Corrected L2 cache sequence disable sequence
+ * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
+ * irq/fiq handling.
+ * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ * fixes the CR #692094.
+ * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt 04/18/13 Implemented ARM Erratas.
+ * Cortex A9 Errata - 742230, 743622, 775420, 794073
+ * L2Cache PL310 Errata - 588369, 727915, 759370
+ * Please refer to file 'xil_errata.h' for errata
+ * description.
+ * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ * cache APIs were corresponding to only Layer 1 cache
+ * memories. New APIs were now added and the existing cache
+ * related APIs were changed to provide a uniform interface
+ * to flush/invalidate/enable/disable the complete cache
+ * system which includes both L1 and L2 caches. The changes
+ * for these were done in:
+ * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ * files.
+ * Four new files were added for supporting L2 cache. They are:
+ * microblaze_flush_cache_ext.S-> Flushes L2 cache
+ * microblaze_flush_cache_ext_range.S -> Flushes a range of
+ * memory in L2 cache.
+ * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ * microblaze_invalidate_cache_ext_range -> Invalidates a
+ * range of memory in L2 cache.
+ * These changes are done to implement PR #697214.
+ * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ * fix the CR #706464. L2 cache disabling happens independent
+ * of L1 data cache disable operation. Changes are done in the
+ * same file in cache handling APIs to do a L2 cache sync
+ * (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
+ * interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ * sync operation. This fixes the CR# 716781.
+ * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
+ * for armcc toolchain.
+ * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ * fix issues related to NEON context saving. The assembly
+ * routines for IRQ and FIQ handling are modified.
+ * Deprecated the older BSP (3.10a).
+ * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ * various potential issues. Made changes in the function
+ * Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ * in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ * L2 cache sync operation and to fix issues around complete
+ * L2 cache flush/invalidation by ways.
+ * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ * to fix linking issues with armcc/DS-5. Modified the armcc
+ * makefile to fix issues.
+ * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ * src\cortexa9\armcc\) to fix CR#767251
+ * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ * Few cache lines were missed to invalidate when unaligned address
+ * invalidation was accommodated in Xil_DCacheInvalidateRange.
+ * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ * stack memory (which contains return address) was invalidated. So
+ * stack memory is flushed first and then L1D cache is invalidated.
+ * This is done to fix CR #763829
+ * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ * mblaze_nt_types.h file and replace uint32_t with u32 in the
+ * profile_hist.c to fix the above CR.
+ * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * instead of libxil.a and added prototypes for
+ * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ * mb_interface.h
+ * 4.1 hk 04/18/14 Add sleep function.
+ * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ * some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
+ * CR#794205
+ * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ * common/xil_testcache.c
+ * Fix for CR#764881.
+ * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
+ * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ * cortexa9/armcc/boot.s. Added default exception handlers for data
+ * abort and prefetch abort using handlers called
+ * DataAbortHandler and PrefetchAbortHandler respectively in
+ * cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
+ * issue of improper linking of translation_table.s
+ * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
+ * in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+ * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
+ * containing type def u32 defined in xil_types.g to resolve issue of
+ * CR#805869
+ * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ * it is not possible to generate timer in nanosecond due to limited
+ * cpu frequency
+ * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
+ * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ * removed function definition of XSmc_NorInit and XSmc_NorInit from
+ * cortexa9/smc.h
+ * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ * cache_ext_range declarations in mb_interface.h CR#783821.
+ * Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
+ * cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
+ * armcc/translation_table.s and iccarm/translation_table.s
+ * to properly defined reserved entries according to address map for
+ * fixing CR#820146
+ * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
+ * and cortexa9/armcc/translation_table.s to resolve compilation
+ * error for solving CR#822897
+ * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
+ * MISRA-C:2012 compliance.
+ * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
+ * adding src/common/xplatform_info.*s
+ * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
+ * removed incorrect initialization of TLB lockdown register to fix
+ * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ * and iccarm/boot.s
+ * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ * for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ * of L2Cache is done later.
+ * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ * taking long time to fix CR#853097. L2CacheSync is added into
+ * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ * instead of just System Stack
+ * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS and also take the compiler and archiver as specified
+ * in settings instead of hardcoding it.
+ * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
+ * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ * accordingly generate the translation table
+ * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS to fix a bug introduced during new version creation
+ * of BSP.
+ * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ * functionalities are avoided for the OpenAMP slave application(when
+ * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ * cache for its operation. Also file operations such as read, write,
+ * close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ * defined for BSP) because XilOpenAMP library contains own file operation.
+ * The xil-crt0.S file is modified for not initializing global timer for
+ * OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ * definition for dsb, isb and dmb to fix the compilation error when used
+ * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ * R5 deadlock for errata 780125
+ * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ * 32 bit BSP in the initialization
+ * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
+ * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
+ * required for MISRA-C:2012 Compliance.
+ * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ * in cortexa9/xil_mmu.h
+ * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
+ * checking the current executing platform
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ * to initialize global constructor for C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ * C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ * translation_table.S to update the translation table according to proper
+ * address map
+ * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
+ * address map
+ * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ * equivalent to vector table base address
+ * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ * as per the toolchain update
+ * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
+ * for Cortex-A53 32bit mode
+ * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ * and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ * instead take it from xparameters.h to properly configure the timestamp
+ * clock frequency
+ * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
+ * new instructions for MB address extension feature
+ * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
+ * system monitor.
+ * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ * use set of assembly instructions to provide required delay to fix
+ * CR#913249.
+ * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ * _exit with exit. We should not be directly calling _exit and should
+ * always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
+ * registers, banked registers for various modes and enabled
+ * the cache ECC check before enabling the fault log for lock step mode
+ * Also modified the cortexr5/gcc/Makefile to support floating point
+ * registers initialization in boot code.
+ * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ * logic in case of lock-step mode when fault log is enabled to fix
+ * CR#938281
+ * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ * header file instrinsics.h which contains assembly instructions
+ * definitions which can be used by C
+ * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ * proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ * interrupts when sleep/usleep is being executed using assembly
+ * instructions to fix CR#913249.
+ * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ * instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ * value and compare it with previous value to detect the overflow
+ * to fix CR#940209.
+ * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ * the fault log to avoid intervention for lock-step mode and cortexr5/
+ * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ * to fix CR#947335
+ * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ * in lock-step to avoid resetting the debug logic which restricts the
+ * access for debugger and removed enabling back of debug modules in
+ * cortexr5/_exit.c
+ * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ * to return correct number of bytes when read buffer is filled and
+ * removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ * instruction macros to disable certain optimizations which may move
+ * code out of loops if optimizers believe that the code will always
+ * return the same result or discard asm statements if optimizers
+ * determine there is no need for the output variables
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * Xil_DCacheInvalidateRange functions description for proper
+ * explaination to fix CR#949801
+ * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
+ * file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
+ * memory is not included for MicroBlaze.
+ * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+ * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ * section since it is part of boot process to fix CR#949555
+ * hk 07/12/16 Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
+ * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
+ * the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
+ * Source code directories specific to ARM processor's are moved to src/arm
+ * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ * into common file each and consolidated files are kept at src/arm/common directory.
+ * GCC source files related to file operations are consolidated and kept
+ * at src/arm/common/gcc directory.
+ * All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ * are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ * xil_io.h must be included as a header file to access io interfacing functions.
+ * Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ * TTC counter value register is read only.
+ * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
+ * the CR#956899.
+ * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ * in cortexr5/xparameters_ps.h
+ * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
+ * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ * these APIs and modifications are done on top of it to handle stdout/stdin
+ * parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ * and rest of the memory in that 32GB region is marked as reserved to avoid
+ * any speculative access
+ * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ * asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ * access is enabled if there is any floating point operation, it is disabled by
+ * default. Also FPU is initally disabled for IRQ and none of the floating point
+ * registers are saved during normal context saving. If IRQ handler does not require
+ * floating point operation, the floating point registers are untouched and no need
+ * for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ * point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ * registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ * target.It fixes the CR#966900
+ * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ * as false i.e. default bsp is EL3.
+ * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ * contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ * when bss sections are not cleared, it may contain previously updated value which
+ * does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
+ * D caches and then disables it. The problem with that is,
+ * potentially there will be a small window after the cache
+ * flush operation and before the we disable D caches where
+ * we might have valid data in cache lines. In such a
+ * scenario disabling the D cache can lead to unknown behavior.
+ * The ideal solution to this is to use assembly code for
+ * the complete API and avoid any memory accesses. But with
+ * that we will end up having a huge amount on assembly code
+ * which is not maintainable. Changes are done to use a mix
+ * of assembly and C code. All local variables are put in
+ * registers. Also function calls are avoided in the API to
+ * avoid using stack memory.
+ * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ * scenarios when an invalidated cache line can get pre fetched to cache.
+ * If that happens, the coherency between cache and memory is lost
+ * resulting in lost data. To avoid this kind of issue either
+ * user has to use dsb() or disable pre-fetching for L1 cache
+ * or else reduce maximum number of outstanding data prefetches allowed.
+ * Using dsb() while comparing data costing more performance compared to
+ * disabling pre-fetching/reducing maximum number of outstanding data
+ * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ * to disable pre-fetching/configure maximum number of outstanding data
+ * prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ * used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn 03/03/17 Added support thumb mode
+ * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ * It fixes CR#970543
+ * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ * profiling we see a crash. That is because the the tcl uses invalid
+ * HSI command. This change fixes it.
+ * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ * any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ * the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ * L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ * of ARM 32 bit processor's.
+ * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
+ * snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ * XGetPSVersion_Info function for PMUFW.
+ * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ * function for PMUFW.
+ * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ * operations.Now,VFP is being enabled in FPEXC register, through boot code
+ * and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * if h/w design configured with HPC port.
+ * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
+ * EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ * CR#982209.
+ * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ * make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ * version register through SMC call, over EL1 NS mode. This change has been done to
+ * support these APIs over EL1 NS mode.
+ * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ * it fixes CR#987464.
+ * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ * It fixes CR#989132.
+ * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ * will use the timer specified by the user to provide delay. A9 and A53 can use
+ * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ * to support the sleep configuration Added new API's for the Axi timer in
+ * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
+ * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ * after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ * disabling/enabling of floating-point unit, before any subsequent
+ * instruction.
+ * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ * support. Now, xil_printf would use PV console instead of UART in case of
+ * hypervisor enabled BSP.
+ * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
+ * configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ * CR#995014.
+ * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+* non-JTAG boot mode, when processor is in lockstep configuration.
+* This behavior is restricting application debugging in non-JTAG boot
+* mode. To get rid of this restriction, added new mld parameter
+* "lockstep_mode_debug", to enable/disable debug logic from BSP
+* settings. Now, debug logic can be enabled through BSP settings,
+* by modifying value of parameter "lockstep_mode_debug" as "true".
+* It fixes CR#993896.
+ * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
+* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
+* in handling upper DDR addresses.It fixes CR#995581.
+* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+* in the list of include paths. This change allows applications/BSP
+* files to include .h files in include_ps directory.
+* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
+* results into abort if accessed from EL1 non secure privilege
+* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+* to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
+* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
+* use UART console, PV console can be enabled by appending
+ "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
+ *
+* 6.7 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
+* floating point register would be done through newly introduced flag
+* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
+* the -mfpu-abi option in extra compiler flags.. This change has
+* been done to avoid saving/restoring of HW floating point registers,
+* when BSP is not compiled with HW floating point configuration.
+* 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
+* on an already registered exception vector.
+* 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
+*
+ *****************************************************************************************/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
new file mode 100644
index 0000000000000000000000000000000000000000..dbbe0d4fd06f59e1cdd29e8bfa7f6d87db119537
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+ (void)fd;
+ return (0);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
new file mode 100644
index 0000000000000000000000000000000000000000..df0218e865194a13e2fec8e1bca030fb2d8574ad
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure. This
+ function returns its address for use by the macro errno defined in
+ errno.h. */
+
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+ return &_REENT->_errno;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
new file mode 100644
index 0000000000000000000000000000000000000000..e58221a14039f3333e6512081f8e69b9f0e7ab6d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ * We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+ (void)fd;
+ (void)cmd;
+ (void)arg;
+ return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
new file mode 100644
index 0000000000000000000000000000000000000000..c5a31f31ba16956a039eb9f88817541bf55d76a1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+ (void)fd;
+ buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+ return (0);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
new file mode 100644
index 0000000000000000000000000000000000000000..d02df5ce2eaaf24db17fc25ec219bb53ec1cc625
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+ return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+ return 1;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
new file mode 100644
index 0000000000000000000000000000000000000000..a5a6448d41d84e0c82291d6fa7320cab641993c3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif
+
+char inbyte(void) {
+ return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
new file mode 100644
index 0000000000000000000000000000000000000000..f142515110adffb71ef1c92aa10925066ce61ef5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ * returns 0 if not. Since we're hooked up to a
+ * serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
new file mode 100644
index 0000000000000000000000000000000000000000..fc2f89d6cc6c9f6194a1a950f7f9e30219c1ea9c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
new file mode 100644
index 0000000000000000000000000000000000000000..106c45c891d86912e4c527e4a735773c0a829a08
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek -- Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
new file mode 100644
index 0000000000000000000000000000000000000000..85e9ce4022c5e8dff64f391e7c2a3cadc6d4515e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c6430886790dbd4c6cdb36d3cbddcc7ab112e23
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c);
+
+#ifdef __cplusplus
+}
+#endif
+
+void outbyte(char c) {
+ XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
new file mode 100644
index 0000000000000000000000000000000000000000..da7e768d0667a158de947e22a46333fa3e146c4f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
@@ -0,0 +1,36 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ XPVXenConsole_Write(ptr);
+#else
+#ifdef STDOUT_BASEADDRESS
+ while (*ptr != (char8)0) {
+ outbyte (*ptr);
+ ptr++;
+ }
+#else
+(void)ptr;
+#endif
+#endif
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
new file mode 100644
index 0000000000000000000000000000000000000000..1d8aada04d7e1eec3fd97fe7cbfc1d23772a39b2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+ Xil_ExceptionDisable();
+ disable_timer();
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ac51b1750e1149011f0c50c6372ab707bbbbb9d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+* Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ * Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* print("Gmon Init called....\r\n") */
+/* putnum(n_gmon_sections) , print("\r\n") */
+/* if( _gmonparam == 0xffffffff ) */
+/* printf("Gmonparam is NULL !!\r\n") */
+/* for( i = 0, i < n_gmon_sections, i++ )[ */
+/* putnum( _gmonparam[i].lowpc) , print("\t") */
+/* putnum( _gmonparam[i].highpc) , print("\r\n") */
+/* putnum( _gmonparam[i].textsize ), print("\r\n") */
+/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
+/* ] */
+
+#ifdef PROC_MICROBLAZE
+ (void)microblaze_init();
+#elif defined PROC_PPC
+ powerpc405_init();
+#else
+ (void)cortexa9_init();
+#endif
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..e85fb5c2d3cea521c419b5600530173448694702
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.c:
+* Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif /* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif /* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif /* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif /* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+* Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set PIT Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_PITSetInterval( timer_clk_ticks ) ;
+ XTime_PITEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+* For PowerPC, PIT and opb_timer can be used for Profiling. This
+* is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+ Xil_ExceptionInit() ;
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+ * PowerPC440 Target - Timer related functions
+ * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ * Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set DEC Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_DECSetInterval( timer_clk_ticks ) ;
+ XTime_DECEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ * For PowerPC, DEC and opb_timer can be used for Profiling. This
+ * is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+ Xil_ExceptionInit();
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting */
+ XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+ /* reset the timers, and clear interrupts */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+ (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+ /* start the timers */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+ | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ * For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ * connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+ /* Register profile_intr_handler
+ * 1. If timer is connected to Interrupt Controller, register the handler
+ * to Interrupt Controllers vector table.
+ * 2. If timer is directly connected to MicroBlaze, register the handler
+ * as Interrupt handler */
+ Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL) ;
+#endif
+
+ /* Initialize the timer with Timer Ticks */
+ (void)opb_timer_init() ;
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+ XIntc_MasterEnable((u32)INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+ Xil_ExceptionEnable();
+
+ return 0;
+
+}
+
+#endif /* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ * The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting
+ * scu timer runs at half the cpu clock */
+ XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+ /* clear any pending interrupts */
+ XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+ /* enable interrupts, auto-reload mode and start the timer */
+ XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(0);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ NULL);
+
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+ PROFILE_TIMER_INTR_ID,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL);
+
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+ /*
+ * Enable interrupts in the Processor.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+ /*
+ * Initialize the timer with Timer Ticks
+ */
+ (void)scu_timer_init() ;
+
+ Xil_ExceptionEnable();
+
+ return 0;
+}
+
+#endif /* PROC_CORTEXA9 */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2cee66b09ec02849f667a2e6731e44e6ab6163e4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..7096a92d804e8cbd2a660b78a32d5ea3a7256862
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
new file mode 100644
index 0000000000000000000000000000000000000000..4cb07a7d3e230e647f9e6c5dbcb1447be4bfed5a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
new file mode 100644
index 0000000000000000000000000000000000000000..2539ce61aa9c4aac388d3cbf0c6dea0621752add
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include
+#include
+#include
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+ s32 index = 0 ;
+
+ while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == cgtable_size ) {
+ return -1 ;
+ } else {
+ return index ;
+ }
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+ s32 index = 0 ;
+ s32 Status;
+
+ while( (index < fromssize) && (froms[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == fromssize ) {
+ Status = -1 ;
+ } else {
+ Status = index ;
+ }
+ return Status;
+}
+#endif /* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+ register struct gmonparam *p = NULL;
+ register s32 toindex, fromindex;
+ s32 j;
+
+ disable_timer();
+
+ /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+ * check that frompcindex is a reasonable pc value.
+ * for example: signal catchers get called from the stack,
+ * not from text space. too bad.
+ */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+ p = &_gmonparam[j];
+ break;
+ }
+ }
+ if( j == n_gmon_sections ) {
+ goto done;
+ }
+
+#ifdef PROFILE_NO_FUNCPTR
+ fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = p->cgtable_size ;
+ p->cgtable_size++ ;
+ p->cgtable[fromindex].frompc = frompc ;
+ p->cgtable[fromindex].selfpc = selfpc ;
+ p->cgtable[fromindex].count = 1 ;
+ goto done ;
+ }
+ p->cgtable[fromindex].count++ ;
+#else
+ fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = (s32)p->fromssize ;
+ p->fromssize++ ;
+ /*if( fromindex >= N_FROMS ) {
+ * print("Error : From PC table overflow\r\n")
+ * goto overflow
+ *}*/
+ p->froms[fromindex].frompc = frompc ;
+ p->froms[fromindex].link = -1 ;
+ }else {
+ toindex = ((s32)(p->froms[fromindex].link));
+ while(toindex != -1) {
+ toindex = (((s32)p->tossize) - toindex)-1 ;
+ if( p->tos[toindex].selfpc == selfpc ) {
+ p->tos[toindex].count++ ;
+ goto done ;
+ }
+ toindex = ((s32)(p->tos[toindex].link)) ;
+ }
+ }
+
+ /*if( toindex == -1 ) { */
+ p->tos-- ;
+ p->tossize++ ;
+ /* if( toindex >= N_TOS ) {
+ * print("Error : To PC table overflow\r\n")
+ * goto overflow
+ *} */
+ p->tos[0].selfpc = selfpc ;
+ p->tos[0].count = 1 ;
+ p->tos[0].link = p->froms[fromindex].link ;
+ p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+ p->state = GMON_PROF_ON;
+ goto enable_timer_label ;
+ /* overflow: */
+ /*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+ enable_timer();
+ return ;
+}
+
+
+#endif /* PROFILE_NO_GRAPH */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..550c60b449b990de20009d14b095b2331274547e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8ee9cef91928d58505b1bc1d22b54bedd2694f3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+ s32 j;
+
+#ifdef PROC_MICROBLAZE
+ asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+ prof_pc = mfspr(SPR_SRR0);
+#else
+ /* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+ /* print("PC: "), putnum(prof_pc), print("\r\n"), */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+ _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+ break;
+ }
+ }
+ /* Ack the Timer Interrupt */
+ timer_ack();
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
new file mode 100644
index 0000000000000000000000000000000000000000..aaf9edee7e1d66620949e3d97c75e989eaced499
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+ char8 buf[9];
+ s32 cnt;
+ s32 i;
+ char8 *ptr;
+ u32 digit;
+ for(i = 0; i<9; i++) {
+ buf[i] = '0';
+ }
+
+ ptr = buf;
+ for (cnt = 7 ; cnt >= 0 ; cnt--) {
+ digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+ if ((digit <= 9U) && (ptr != NULL)) {
+ digit += (u32)'0';
+ *ptr = ((char8) digit);
+ ptr += 1;
+ } else if (ptr != NULL) {
+ digit += ((u32)'a' - (u32)10);
+ *ptr = ((char8)digit);
+ ptr += 1;
+ } else {
+ /*Made for MisraC Compliance*/;
+ }
+ }
+
+ if(ptr != NULL) {
+ *ptr = (char8) 0;
+ }
+ print (buf);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f7b7d26152c6f8eab88ea49ec886e949580d9e6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read -- read bytes from the serial port. Ignore fd, since
+ * we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
new file mode 100644
index 0000000000000000000000000000000000000000..87a753d4906486b9ce256e2c03341d0743cbed50
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+ char8 *base;
+ static char8 *heap_ptr = HeapBase;
+
+ base = heap_ptr;
+ if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
+ heap_ptr += nbytes;
+ return base;
+ } else {
+ errno = ENOMEM;
+ return ((char8 *)-1);
+ }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
new file mode 100644
index 0000000000000000000000000000000000000000..f85743b47d858386f68dd48822c7fd8af9fe3fe0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Updated sleep function to make use Global
+* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
+*
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param seconds requested
+*
+* @return 0 always
+*
+* @note None.
+*
+****************************************************************************/
+unsigned sleep_A9(unsigned int seconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
new file mode 100644
index 0000000000000000000000000000000000000000..f53b2d8c8e2c4c3d68702d7780654fc60e1950ea
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+*
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a4d33608256f53d59b1c6470b9627803ea20b55
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0cc6807ba9061e8a1fa85e632587d23880980fe
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ * we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+ (void) path;
+ errno = EIO;
+ return (-1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
new file mode 100644
index 0000000000000000000000000000000000000000..65eea28cfacfd1aa76d1dded45c9f0f98743ee98
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
+* possible to generate timer in nanosecond due to
+* limited cpu frequency
+* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/**************************** Constant Definitions ************************/
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param useconds requested
+*
+* @return 0 if the delay can be achieved, -1 if the requested delay
+* is out of range
+*
+* @note None.
+*
+****************************************************************************/
+int usleep_A9(unsigned long useconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
new file mode 100644
index 0000000000000000000000000000000000000000..0a3616328f7dee51d1eceb7a780938a8a8e18dd6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
+* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
+* and added UndefinedException for a53 32 bit and r5
+* processor
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb599b5602601d799de56541046a0530075fedff
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
new file mode 100644
index 0000000000000000000000000000000000000000..9389f610a8db20c8a8cf5bffafc1995f826b23af
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ * stdout and stderr are the same. Since we have no filesystem,
+ * open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ sint32 length;
+
+ (void)fd;
+ (void)nbytes;
+ length = XPVXenConsole_Write(buf);
+ return length;
+#else
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..787212ca75ff368e405799266b103f095b0b22a1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+*
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
new file mode 100644
index 0000000000000000000000000000000000000000..650946bd01f4555daaeaf12db9919130e4aecf7d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
new file mode 100644
index 0000000000000000000000000000000000000000..3d97bebd450eda76d8221c8a9b012bb723c9b6ca
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+*
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
new file mode 100644
index 0000000000000000000000000000000000000000..f18601874bb5b8a84f10954730b4aca1bc988598
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
new file mode 100644
index 0000000000000000000000000000000000000000..59b3c1c98be72a13c998fb13b2ea66892d4dbc88
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 Initial release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief Implement assert. Currently, it calls a user-defined callback
+* function if one has been set. Then, it potentially enters an
+* infinite loop depending on the value of the Xil_AssertWait
+* variable.
+*
+* @param file: filename of the source
+* @param line: linenumber within File
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait != 0) {
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Set up a callback function to be invoked when an assert occurs.
+* If a callback is already installed, then it will be replaced.
+*
+* @param routine: callback to be invoked when an assert is taken
+*
+* @return None.
+*
+* @note This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Null handler function. This follows the XInterruptHandler
+* signature for interrupt handlers. It can be used to assign a null
+* handler (a stub) to an interrupt controller vector table.
+*
+* @param NullParameter: arbitrary void pointer and not used.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
new file mode 100644
index 0000000000000000000000000000000000000000..add4124e2c0c48a8844dfb3aad307c8ec5ae6e38
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accomodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
new file mode 100644
index 0000000000000000000000000000000000000000..259c3b1f104987f101ae74450cae7474d0918ba2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
@@ -0,0 +1,1641 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+* to xil_cache_mach.h to give access to sophisticated users
+* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+* L1 and L2 caches in a single loop and used dsb, L2 sync
+* at the end of the loop.
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+* operation was being done with L1 Data cache disabled. This is
+* fixed so that L2 cache disable operation happens independent of
+* L1 cache disable operation. This fixes CR #706464.
+* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+* This is done to fix the CR #700542.
+* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+* relevant cache APIs to disable and enable back the interrupts.
+* This fixes CR #663885.
+* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
+* out that for L2 cache flush/clean/invalidation by cache lines
+* does not need a cache sync as these are atomic nature. Similarly
+* figured out that for complete L2 cache flush/invalidation by way
+* we need to wait for some more time in a loop till the status
+* shows that the cache operation is completed.
+* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+* cache lines were missed to invalidate when unaligned address
+* invalidation was accommodated. That fixes CR #766768.
+* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+* stack memory which contains return address was invalidated. So
+* stack memory was flushed first and then L1D cache is invalidated.
+* This is done to fix CR #763829
+* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+* explanation of CR#785243
+* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+* has stack memory which has return address. Before invalidating
+* cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+* to remove unnecessary dsb in the APIs. Instead of using dsb
+* for L2 Cache, L2CacheSync has been used for each L2 cache line
+* and single dsb has been used for L1 cache. Also L2CacheSync is
+* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+* and Xil_L2CacheInvalidate APIs are modified to flush the complete
+* stack instead of just System Stack
+* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+* application(when USE_AMP flag is defined for BSP) as master CPU
+* would be utilizing L2 cache for its operation
+* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+* version r0p2, which is present in zynq. So,removed the handling
+* related to same.It fixes CR#989132.
+* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+* routines to ensure the stack data flushed only when the respective
+* caches are enabled. This fixes CR-992023.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+ extern s32 _stack_end;
+ extern s32 __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param Value, value to be written to Debug Control Register.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+ (void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+}
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+ Xil_L1DCacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1DCacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a Data cache line. If the byte specified by the address
+* (adr) is cached by the Data cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* modified contents are lost and are NOT written to the system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1DCacheInvalidateLine(adr);
+
+ mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If
+* the cachelines are modified (dirty), the modified contents are lost
+* and NOT written to the system memory before the lines are
+* invalidated.
+*
+* In this function, if start address or end address is not aligned to
+* cache-line, particular cache-line containing unaligned start or end
+* address is flush first and then invalidated the others as
+* invalidating the same unaligned cache line may result into loss of
+* data. This issue raises few possibilities.
+*
+* If the address to be invalidated is not cache-line aligned, the
+* following choices are available:
+* 1. Invalidate the cache line when required and do not bother much
+* for the side effects. Though it sounds good, it can result in
+* hard-to-debug issues. The problem is, if some other variable are
+* allocated in the same cache line and had been recently updated
+* (in cache), the invalidation would result in loss of data.
+* 2. Flush the cache line first. This will ensure that if any other
+* variable present in the same cache line and updated recently are
+* flushed out to memory. Then it can safely be invalidated. Again it
+* sounds good, but this can result in issues. For example, when the
+* invalidation happens in a typical ISR (after a DMA transfer has
+* updated the memory), then flushing the cache line means, loosing
+* data that were updated recently before the ISR got invoked.
+*
+* Linux prefers the second one. To have uniform implementation
+* (across standalone and Linux), the second option is implemented.
+* This being the case, follwoing needs to be taken care of:
+* 1. Whenever possible, the addresses must be cache line aligned.
+* Please nore that, not just start address, even the end address must
+* be cache line aligned. If that is taken care of, this will always
+* work.
+* 2. Avoid situations where invalidation has to be done after the
+* data is updated by peripheral/DMA directly into the memory. It is
+* not tough to achieve (may be a bit risky). The common use case to
+* do invalidation is when a DMA happens. Generally for such use
+* cases, buffers can be allocated first and then start the DMA. The
+* practice that needs to be followed here is, immediately after
+* buffer allocation and before starting the DMA, do the invalidation.
+* With this approach, invalidation need not to be done after the DMA
+* transfer is over.
+*
+* This is going to always work if done carefully.
+* However, the concern is, there is no guarantee that invalidate has
+* not needed to be done after DMA is complete. For example, because
+* of some reasons if the first cache line or last cache line
+* (assuming the buffer in question comprises of multiple cache lines)
+* are brought into cache (between the time it is invalidated and DMA
+* completes) because of some speculative prefetching or reading data
+* for a variable present in the same cache line, then we will have to
+* invalidate the cache after DMA is complete.
+*
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 tempadr = adr;
+ u32 tempend;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ end = tempadr + len;
+ tempend = end;
+ /* Select L1 Data cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ if ((tempadr & (cacheline-1U)) != 0U) {
+ tempadr &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempadr);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ tempadr += cacheline;
+ }
+ if ((tempend & (cacheline-1U)) != 0U) {
+ tempend &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempend);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ }
+
+ while (tempadr < tempend) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = tempadr;
+ Xil_L2CacheSync();
+#endif
+
+ /* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = tempadr; }
+#endif
+ tempadr += cacheline;
+ }
+ }
+
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlush();
+#ifndef USE_AMP
+ Xil_L2CacheFlush();
+#endif
+ mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_L2CacheFlushLine(adr);
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the
+* data cache, the cachelines containing those bytes are invalidated.
+* If the cachelines are modified (dirty), they are written to the
+* system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr &= ~(cacheline - 1U);
+
+ while (LocalAddr < end) {
+
+ /* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+ /* Flush L2 cache line */
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+ dsb();
+ mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param adr: 32bit address of the data to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+ Xil_L2CacheStoreLine(adr);
+#endif
+ mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief Enable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+ Xil_L1ICacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1ICacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate an instruction cache line. If the instruction specified
+* by the address is cached by the instruction cache, the cacheline
+* containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1ICacheInvalidateLine(adr);
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the instruction cache for the given address range.
+* If the instructions specified by the address range are cached by
+* the instrunction cache, the cachelines containing those
+* instructions are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = LocalAddr;
+ dsb();
+#endif
+
+ /* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 and L2 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ return;
+ }
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheInvalidate();
+
+ /* enable the Data cache */
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+ /* disable the Data cache */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for invalidating
+* the whole D-cache. This function invalidates each line by
+* set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way, WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+#ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 CtrlReg;
+#endif
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ * */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+#endif
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+ /* Determine Cache Size */
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+
+ /* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+ /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set=0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 Data cache line. If the byte specified by the
+* address (Addr) is cached by the Data cache, the cacheline
+* containing that byte is invalidated. If the cacheline is modified
+* (dirty), the modified contents are lost and are NOT written to
+* system memory before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* NOT written to the system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for flushing
+* the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way;
+ u32 WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+
+ /* Determine Cache Size */
+
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+ /* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set = 0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 flush to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to system memory
+* before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache and the cacheline is
+* modified (dirty), the entire contents of the cacheline are written
+* to system memory. After the store completes, the cacheline is
+* marked as unmodified (not dirty).
+*
+* @param Address to be stored.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 store to complete */
+ dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+ return;
+ }
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* enable the instruction cache */
+ CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Disable level 1 the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ dsb();
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* disable the instruction cache */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 instruction cache line. If the instruction
+* specified by the address is cached by the instruction cache, the
+* cacheline containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 instruction cache for the given address
+* range. If the instrucions specified by the address range are cached
+* by the instruction cache, the cacheline containing those bytes are
+* invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief Enable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ /* only enable if L2CC is currently disabled */
+ if ((L2CCReg & 0x01U) == 0U) {
+ /* set up the way size and latencies */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_AUX_CNTRL_OFFSET);
+ L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+ L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+ L2CCReg);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+ XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+ XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+ /* Clear the pending interrupts */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_ISR_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+ Xil_L2CacheInvalidate();
+ /* Enable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg | (0x01U)));
+
+ Xil_L2CacheSync();
+ /* synchronize the processor */
+ dsb();
+
+ }
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ if((L2CCReg & 0x1U) != 0U) {
+
+ /* Clean and Invalidate L2 Cache */
+ Xil_L2CacheFlush();
+
+ /* Disable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg & (~0x01U)));
+ /* Wait for the cache operations to complete */
+
+ dsb();
+ }
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+ #ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 L2CCReg;
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ if ((L2CCReg & 0x01U) != 0U) {
+ /*Flush stack memory to save return address*/
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+
+ #endif
+ u32 ResultDCache;
+ /* Invalidate the caches */
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ while(ResultDCache != (u32)0U) {
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ /* Wait for the invalidate to complete */
+ Xil_L2CacheSync();
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a level 2 cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty),
+* the modified contents are lost and are NOT written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* are NOT written to system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+ u32 ResultL2Cache;
+
+ /* Flush the caches */
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+
+ while(ResultL2Cache != (u32)0U) {
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ Xil_L2CacheSync();
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to the system
+* memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache and the cacheline is modified
+* (dirty), the entire contents of the cacheline are written to
+* system memory. After the store completes, the cacheline is marked
+* as unmodified (not dirty).
+*
+* @param adr: 32bit address of the data/instruction to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ /* synchronize the processor */
+ dsb();
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6614d5f992709379ce97da6e8be0cfb9eb80d8b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..fa92c6b1c4087b05b80e256770a5c0d023d99fe2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
new file mode 100644
index 0000000000000000000000000000000000000000..490aebeabe7f0d17ed05105a8bfe9433f74515fd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+*
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
new file mode 100644
index 0000000000000000000000000000000000000000..d34fd2199c5aff7e3295d8df847b01338262d086
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
+* processors and added Xil_UndefinedExceptionHandler
+* for a53 32 bit and r5 as well.
+* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
+* fix the warnings.
+* 6.7 mna 26/04/18 Add an API to obtain a corresponding
+* Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SyncAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_UndefinedExceptionHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_PrefetchAbortHandler, NULL},
+ {Xil_DataAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr; /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
+ exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param Data is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+ (void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief The function is a common API used to initialize exception handlers
+* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+* and Cortex-A9, the exception handlers are being initialized
+* statically and this function does not do anything.
+* However, it is still present to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to
+* initialize exception handlers).
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+ return;
+}
+
+/*****************************************************************************/
+/**
+* @brief Register a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data)
+{
+ XExc_VectorTable[Exception_id].Handler = Handler;
+ XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+* @brief Get a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler,
+ void **Data)
+{
+ *Handler = XExc_VectorTable[Exception_id].Handler;
+ *Data = XExc_VectorTable[Exception_id].Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Removes the Handler for a specific exception Id. The stub Handler
+* is then registered for this exception Id.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+ Xil_ExceptionRegisterHandler(Exception_id,
+ Xil_ExceptionNullHandler,
+ NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
+ while(1) {
+ ;
+ }
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
new file mode 100644
index 0000000000000000000000000000000000000000..83303875d43a0de16324293bade2e2050e7d1370
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
@@ -0,0 +1,260 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
new file mode 100644
index 0000000000000000000000000000000000000000..d4434d07fa748457f2f476ebf82f9f8b20c93c91
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
new file mode 100644
index 0000000000000000000000000000000000000000..90bfc81dc190a506078fa5ec12c27db7c466a0a1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 16-bit endian converion.
+*
+* @param Data: 16 bit value to be converted
+*
+* @return 16 bit Data with converted endianess
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 32-bit endian converion.
+*
+* @param Data: 32 bit value to be converted
+*
+* @return 32 bit data with converted endianess
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c5aa43c7ecbc506145d0aaf5f409992bb08036e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebafde87d7ff8a38bd28724a08ecca7701ea4f58
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
new file mode 100644
index 0000000000000000000000000000000000000000..0929a6878ff746123ebbd285804913712a1ba879
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief This function copies memory from once location to other.
+*
+* @param dst: pointer pointing to destination memory
+*
+* @param src: pointer pointing to source memory
+*
+* @param cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+ char *d = (char*)(void *)dst;
+ const char *s = src;
+
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int);
+ s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+ while ((cnt) > 0U){
+ *d = *s;
+ d += 1U;
+ s += 1U;
+ cnt -= 1U;
+ }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
new file mode 100644
index 0000000000000000000000000000000000000000..a2d5e6681d9b82f40e81baa106789d512da27f6b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000000000000000000000000000000000000..e114d142d2a9c1bfafa4060fea861721afc2fce7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
@@ -0,0 +1,524 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release
+* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
+*
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert and deassert the ddr softreset bit */
+ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
+ RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+ RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Map the ocm region to postbootrom state */
+ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+ RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+ Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+
+ /* Clear the interuupts */
+ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+ RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+ Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+ /* Clear the idle counter registers */
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+ /* Update the ecc registers with reset values */
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+ XSMC_ECC_MEMCFG1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+ XSMC_ECC_MEMCMD1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+ XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+ u32 i;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Update all the MIO registers with reset values */
+ for (i=0U; i<=1U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+ for (; i<=8U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_02_RESET_VAL);
+ }
+ for (; i<=53U ;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+ /* update the pll control registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+ /* update the pll config registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+ /* update the clock control registers with reset values */
+ Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Disable the level shifters */
+ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+ Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000000000000000000000000000000000000..c228c988eb3035912db6e0d906d41609afac4b38
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
new file mode 100644
index 0000000000000000000000000000000000000000..1f58d906b88a3de11364214191ffe89be161486e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+* before enabling back.
+* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
+* translation table and branch predictor arrays are
+* invalidated, D-cache flushed before the attribute
+* change is applied. This is done so that the user
+* need not call Xil_DisableMMU before calling
+* Xil_SetTlbAttributes.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+* D cache after the translation table update. Removed the
+* redundant TLB invalidation in the same API at the beginning.
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief This function sets the memory attributes for a section covering 1MB
+* of memory in the translation table.
+*
+* @param Addr: 32-bit address for which memory attributes need to be set.
+* @param attrib: Attribute for the given memory region. xil_mmu.h contains
+* definitions of commonly used memory attributes which can be
+* utilized for this function.
+*
+*
+* @return None.
+*
+* @note The MMU or D-cache does not need to be disabled before changing a
+* translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+ u32 *ptr;
+ u32 section;
+
+ section = Addr / 0x100000U;
+ ptr = &MMUTable;
+ ptr += section;
+ if(ptr != NULL) {
+ *ptr = (Addr & 0xFFF00000U) | attrib;
+ }
+
+ Xil_DCacheFlush();
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ /* Invalidate all branch predictors */
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+ dsb(); /* ensure completion of the BP and TLB invalidation */
+ isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief Enable MMU for cortex A9 processor. This function invalidates the
+* instruction and data caches, and then enables MMU.
+*
+* @param None.
+* @return None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+ u32 Reg;
+ Xil_DCacheInvalidate();
+ Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg |= (u32)0x05U;
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+ dsb();
+ isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Disable MMU for Cortex A9 processors. This function invalidates
+* the TLBs, Branch Predictor Array and flushed the D Caches before
+* disabling the MMU.
+*
+* @param None.
+*
+* @return None.
+*
+* @note When the MMU is disabled, all the memory accesses are treated as
+* strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+ u32 Reg;
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+ Xil_DCacheFlush();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+ /* Disable Branch Prediction */
+ Reg &= (u32)(~0x800U);
+#endif
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd14b63b7057e38c5df9eadbab636379d684e30e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
new file mode 100644
index 0000000000000000000000000000000000000000..dc0897f0d3c65b253cd018bd96766ddf08d4863c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
@@ -0,0 +1,443 @@
+/*---------------------------------------------------*/
+/* Modified from : */
+/* Public Domain version of printf */
+/* Rud Merriam, Compsult, Inc. Houston, Tx. */
+/* For Embedded Systems Programming, 1991 */
+/* */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include
+#include
+#include
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+ s32 len;
+ s32 num1;
+ s32 num2;
+ char8 pad_character;
+ s32 do_padding;
+ s32 left_flag;
+ s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/* */
+/* This routine puts pad characters into the output */
+/* buffer. */
+/* */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+ s32 i;
+
+ if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+ i=(par->len);
+ for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( par->pad_character);
+#endif
+ }
+ }
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a string to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+static void outs(const charptr lp, struct params_s *par)
+{
+ charptr LocalPtr;
+ LocalPtr = lp;
+ /* pad on left if needed */
+ if(LocalPtr != NULL) {
+ par->len = (s32)strlen( LocalPtr);
+ }
+ padding( !(par->left_flag), par);
+
+ /* Move string to the buffer */
+ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+ (par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*LocalPtr);
+#endif
+ LocalPtr += 1;
+}
+
+ /* Pad on right if needed */
+ /* CR 439175 - elided next stmt. Seemed bogus. */
+ /* par->len = strlen( lp) */
+ padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a number to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[32];
+ const char8 digits[] = "0123456789ABCDEF";
+ u32 num;
+ for(i = 0; i<32; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = n;
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( outbuf[i] );
+#endif
+ i--;
+}
+ padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a 64-bit number to the output */
+/* buffer as directed by the padding and positioning */
+/* flags. */
+/* */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[64];
+ const char8 digits[] = "0123456789ABCDEF";
+ u64 num;
+ for(i = 0; i<64; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = (n);
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+ outbyte( outbuf[i] );
+ i--;
+}
+ padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/* */
+/* This routine gets a number from the format */
+/* string. */
+/* */
+static s32 getnum( charptr* linep)
+{
+ s32 n;
+ s32 ResultIsDigit = 0;
+ charptr cptr;
+ n = 0;
+ cptr = *linep;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ while (ResultIsDigit != 0) {
+ if(cptr != NULL){
+ n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+ cptr += 1;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ }
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ *linep = ((charptr )(cptr));
+ return(n);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine operates just like a printf/sprintf */
+/* routine. It outputs a set of data under the */
+/* control of a formatting string. Not all of the */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded */
+/* systems work. Primarily the floating point */
+/* routines are omitted. Other formats could be */
+/* added easily by following the examples shown for */
+/* the supported formats. */
+/* */
+
+/* void esp_printf( const func_ptr f_ptr,
+ const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+ XPVXenConsole_Printf(ctrl1);
+}
+#else
+void xil_printf( const char8 *ctrl1, ...)
+{
+ s32 Check;
+#if defined (__aarch64__)
+ s32 long_flag;
+#endif
+ s32 dot_flag;
+
+ params_t par;
+
+ char8 ch;
+ va_list argp;
+ char8 *ctrl = (char8 *)ctrl1;
+
+ va_start( argp, ctrl1);
+
+ while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+ /* move format string chars to buffer until a */
+ /* format control is found. */
+ if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*ctrl);
+#endif
+ ctrl += 1;
+ continue;
+ }
+
+ /* initialize all the flags for this format. */
+ dot_flag = 0;
+#if defined (__aarch64__)
+ long_flag = 0;
+#endif
+ par.unsigned_flag = 0;
+ par.left_flag = 0;
+ par.do_padding = 0;
+ par.pad_character = ' ';
+ par.num2=32767;
+ par.num1=0;
+ par.len=0;
+
+ try_next:
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ if(ctrl != NULL) {
+ ch = *ctrl;
+ }
+ else {
+ ch = *ctrl;
+ }
+
+ if (isdigit((s32)ch) != 0) {
+ if (dot_flag != 0) {
+ par.num2 = getnum(&ctrl);
+ }
+ else {
+ if (ch == '0') {
+ par.pad_character = '0';
+ }
+ if(ctrl != NULL) {
+ par.num1 = getnum(&ctrl);
+ }
+ par.do_padding = 1;
+ }
+ if(ctrl != NULL) {
+ ctrl -= 1;
+ }
+ goto try_next;
+ }
+
+ switch (tolower((s32)ch)) {
+ case '%':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( '%');
+#endif
+ Check = 1;
+ break;
+
+ case '-':
+ par.left_flag = 1;
+ Check = 0;
+ break;
+
+ case '.':
+ dot_flag = 1;
+ Check = 0;
+ break;
+
+ case 'l':
+ #if defined (__aarch64__)
+ long_flag = 1;
+ #endif
+ Check = 0;
+ break;
+
+ case 'u':
+ par.unsigned_flag = 1;
+ /* fall through */
+ case 'i':
+ case 'd':
+ #if defined (__aarch64__)
+ if (long_flag != 0){
+ outnum1((s64)va_arg(argp, s64), 10L, &par);
+ }
+ else {
+ outnum( va_arg(argp, s32), 10L, &par);
+ }
+ #else
+ outnum( va_arg(argp, s32), 10L, &par);
+ #endif
+ Check = 1;
+ break;
+ case 'p':
+ #if defined (__aarch64__)
+ par.unsigned_flag = 1;
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ Check = 1;
+ break;
+ #endif
+ case 'X':
+ case 'x':
+ par.unsigned_flag = 1;
+ #if defined (__aarch64__)
+ if (long_flag != 0) {
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ }
+ else {
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ }
+ #else
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ #endif
+ Check = 1;
+ break;
+
+ case 's':
+ outs( va_arg( argp, char *), &par);
+ Check = 1;
+ break;
+
+ case 'c':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( va_arg( argp, s32));
+#endif
+ Check = 1;
+ break;
+
+ case '\\':
+ switch (*ctrl) {
+ case 'a':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x07));
+#endif
+ break;
+ case 'h':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x08));
+#endif
+ break;
+ case 'r':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+#endif
+ break;
+ case 'n':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+ outbyte( ((char8)0x0A));
+#endif
+ break;
+ default:
+#ifdef STDOUT_BASEADDRESS
+ outbyte( *ctrl);
+#endif
+ break;
+ }
+ ctrl += 1;
+ Check = 0;
+ break;
+
+ default:
+ Check = 1;
+ break;
+ }
+ if(Check == 1) {
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ continue;
+ }
+ goto try_next;
+ }
+ va_end( argp);
+}
+#endif
+/*---------------------------------------------------*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
new file mode 100644
index 0000000000000000000000000000000000000000..016ae3b2f6b40423b9efe6063e2282dc1d9ffb74
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
new file mode 100644
index 0000000000000000000000000000000000000000..972a310a8d2cc3c3e586e549ae321eeaff4639f4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 srm 11/02/17 First release
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param seconds - delay time in seconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+ sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+ sleep_MB(seconds);
+#else
+ sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param useconds - delay time in useconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+ usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+ usleep_MB(useconds);
+#else
+ usleep_A9(useconds);
+#endif
+
+ }
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
new file mode 100644
index 0000000000000000000000000000000000000000..5bf30ccb4537843d0c04fc19d1b9d436db9125cf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+*
+*
+*****************************************************************************/
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param delay - delay time in seconds/micro seconds
+*
+* @param frequency - Number of counts per second/micro second
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+ u64 tEnd = 0U;
+ u64 tCur = 0U;
+ XCntrVal TimeHighVal = 0U;
+ XCntrVal TimeLowVal1 = 0U;
+ XCntrVal TimeLowVal2 = 0U;
+
+ TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
+ do
+ {
+ TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ if (TimeLowVal2 < TimeLowVal1) {
+ TimeHighVal++;
+ }
+ TimeLowVal1 = TimeLowVal2;
+ tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+ (u64)TimeLowVal2;
+ }while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+ u32 TimerPrescalar;
+ u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ u32 LpdRst;
+
+ LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+ /* check if the timer is reset */
+ if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE)) != 0 )) {
+ LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE));
+ Xil_Out32(RST_LPD_IOU2, LpdRst);
+ } else {
+#endif
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ /* check if Timer is disabled */
+ if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ /* check if Timer is configured with proper functionalty for sleep */
+ if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+ return;
+ }
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ }
+#endif
+ /* Disable the timer to configure */
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+ /* Disable the prescalar */
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+ TimerPrescalar);
+ /* Enable the Timer */
+ TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..4bfac0ac46f7d9516516cb2c0dbc6c85977e2cac
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+*
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
new file mode 100644
index 0000000000000000000000000000000000000000..157ad08369f66a3a1d68212c5204e77713d4dfd3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
@@ -0,0 +1,371 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
+* cache line.
+*
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
+* and Xil_DCacheInvalidateRange. This test function writes a constant
+* value to the Data array, flushes the range, writes a new value, then
+* invalidates the corresponding range.
+* @param None
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+ s32 Index;
+ s32 Status = 0;
+ u32 CtrlReg;
+ INTPTR Value;
+
+ xil_printf("-- Cache Range Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A00505;
+
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" flush range done\r\n");
+
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A00505) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush worked\r\n");
+ }
+ else {
+ xil_printf("Error: flush dcache range not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0C505;
+
+
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" invalidate dcache range done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0A05;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A0A05) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+
+ if (!Status) {
+ xil_printf(" Invalidate worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache range not working\r\n");
+ }
+ xil_printf("-- Cache Range Test Complete --\r\n");
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value,
+* then invalidates the DCache.
+*
+* @return
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+ s32 Index;
+ s32 Status;
+ INTPTR Value;
+ u32 CtrlReg;
+
+ xil_printf("-- Cache All Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50500A0A;
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlush();
+ xil_printf(" flush all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+
+ if (Value != 0x50500A0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Flush dcache all not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x505FFA0A;
+
+ Xil_DCacheFlush();
+
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidate();
+
+ xil_printf(" invalidate all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50CFA0A;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0x50CFA0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Invalidate all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache all not working\r\n");
+ }
+
+ xil_printf("-- DCache all Test Complete --\n\r");
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+ xil_printf("-- Invalidate icache range done --\r\n");
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+ Xil_ICacheInvalidate();
+ xil_printf("-- Invalidate icache all done --\r\n");
+ return 0;
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
new file mode 100644
index 0000000000000000000000000000000000000000..c35e9a463f05d7fa7e176b96369f5af1493d3127
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+*
Cache test
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
new file mode 100644
index 0000000000000000000000000000000000000000..e6a36807b3795050909953e93beffd87b0e4c1d3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
@@ -0,0 +1,299 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param Data is the 16-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+ return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param Data is the 32-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+ u16 Lo16;
+ u16 Hi16;
+
+ u16 Swap16Lo;
+ u16 Swap16Hi;
+
+ Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+ Lo16 = (u16)(Data & 0x0000FFFFU);
+
+ Swap16Lo = Swap16(Lo16);
+ Swap16Hi = Swap16(Hi16);
+
+ return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide register IO test where the
+* register is accessed using Xil_Out8 and Xil_In8, and comparing
+* the written values by reading them back.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+ u8 ValueIn;
+ s32 Index;
+ s32 Status = 0;
+
+ for (Index = 0; Index < Length; Index++) {
+ Xil_Out8((INTPTR)Addr, Value);
+
+ ValueIn = Xil_In8((INTPTR)Addr);
+
+ if ((Value != ValueIn) && (Status == 0)) {
+ Status = -1;
+ break;
+ }
+ }
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide register IO test. Each location
+* is tested by sequentially writing a 16-bit wide register, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register
+* IO, and big-endian register IO. When testing little/big-endian IO,
+* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+* Compare In-Out values. Whether to swap the read-in value before
+* comparing is controlled by the 5th argument.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+* @param Kind: Type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+ u16 *TempAddr16;
+ u16 ValueIn = 0U;
+ s32 Index;
+ TempAddr16 = Addr;
+ Xil_AssertNonvoid(TempAddr16 != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out16LE((INTPTR)TempAddr16, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out16BE((INTPTR)TempAddr16, Value);
+ break;
+ default:
+ Xil_Out16((INTPTR)TempAddr16, Value);
+ break;
+ }
+
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out16((INTPTR)TempAddr16, Value);
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+ break;
+ default:
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+ break;
+ }
+
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr16 += sizeof(u16);
+ }
+ return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide register IO test. Each location
+* is tested by sequentially writing a 32-bit wide regsiter, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register IO,
+* and big-endian register IO. When testing little/big-endian IO,
+* the function perform the following sequence, Xil_Out32LE/
+* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+* Whether to swap the read-in value *before comparing is controlled
+* by the 5th argument.
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+* @param Kind: type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+ u32 *TempAddr;
+ u32 ValueIn = 0U;
+ s32 Index;
+ TempAddr = Addr;
+ Xil_AssertNonvoid(TempAddr != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out32LE((INTPTR)TempAddr, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out32BE((INTPTR)TempAddr, Value);
+ break;
+ default:
+ Xil_Out32((INTPTR)TempAddr, Value);
+ break;
+ }
+
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out32((INTPTR)TempAddr, Value);
+
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In32LE((INTPTR)TempAddr);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In32BE((INTPTR)TempAddr);
+ break;
+ default:
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+ break;
+ }
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr += sizeof(u32);
+ }
+ return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad68ead6430fef3b1a961165119aca5b8c557652
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+*
I/O test
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
new file mode 100644
index 0000000000000000000000000000000000000000..87426d17aa6312ce77ec592ad582e56f17d68d84
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
@@ -0,0 +1,868 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: test type selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - 0 is returned for a pass
+* - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u32 Val;
+ u32 FirtVal;
+ u32 WordMem32;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ *(Addr+I) = Val;
+ Val++;
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (1U << j);
+
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u32) RotateLeft(Val, 32U);
+ }
+
+ /*
+ * Restore the reference 'val' to the
+ * initial value
+ */
+ Val = 1U << j;
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = (u32)RotateLeft(Val, 32U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible
+ * initial test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = ~(1U << j);
+
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+
+ Val = ~(1U << j);
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* Read the location */
+ WordMem32 = *(Addr+I);
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+
+ if ((WordMem32 ^ Val) != 0x00000000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u32)0) {
+ Val = 0xDEADBEEFU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant Pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u16 Val;
+ u16 FirtVal;
+ u16 WordMem16;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * selectthe proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (u16)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u16)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones
+ * test to test for bad
+ * data bits
+ */
+
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u16) (~((INTPTR)(&Addr[I])));
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ Val = (u16) (~((INTPTR) (&Addr[I])));
+ if ((WordMem16 ^ Val) != 0x0000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+ if (Pattern == (u16)0) {
+ Val = 0xDEADU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u8 Val;
+ u8 FirtVal;
+ u8 WordMem8;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * select the proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+ Val = (u8)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u8)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test to test
+ * for bad data bits
+ */
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ if ((WordMem8 ^ Val) != 0x00U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u8)0) {
+ Val = 0xA5U;
+ }
+ else {
+ Val = Pattern;
+ }
+ /*
+ * Fill the memory with fixed Pattern
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the left one bit position
+*
+* @param Input is value to be rotated to the left
+* @param Width is the number of bits in the input data
+*
+* @return
+* The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+ u32 Msb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+ /*
+ * set the Width of the Input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ Msb = LocalInput & MsbMask;
+
+ ReturnVal = LocalInput << 1U;
+
+ if (Msb != 0x00000000U) {
+ ReturnVal = ReturnVal | (u32)0x00000001;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the right one bit position
+*
+* @param Input: value to be rotated to the right
+* @param Width: number of bits in the input data
+*
+* @return
+* The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+ u32 Lsb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << 1U) - 1U;
+
+ /*
+ * set the width of the input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ ReturnVal = LocalInput >> 1U;
+
+ Lsb = LocalInput & 0x00000001U;
+
+ if (Lsb != 0x00000000U) {
+ ReturnVal = ReturnVal | MsbMask;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
new file mode 100644
index 0000000000000000000000000000000000000000..c204728223b2c15e57d4e9f8afc944ad02a40c76
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+*
Memory test
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..8143aff1ea4481ade21acf41eba4c361096081a9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include
+#include
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
new file mode 100644
index 0000000000000000000000000000000000000000..735e26dd4df8663a93b4f22ce5eb5cd712bc6653
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
new file mode 100644
index 0000000000000000000000000000000000000000..d6b88cb3960871015e280d99552a83aedb857522
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function initializes the event counters in L2 Cache controller
+* with a set of event codes specified by the user.
+*
+* @param Event0: Event code for counter 0.
+* @param Event1: Event code for counter 1.
+*
+* @return None.
+*
+* @note The definitions for event codes XL2CC_* can be found in
+* xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+ /* Write event code into cnt1 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+ /* Write event code into cnt0 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+ /* Reset counters */
+ XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief This function starts the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+ u32 *LocalPtr;
+ LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+ XL2cc_EventCtrReset();
+
+ /* Enable counter */
+ /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+ *LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters in L2 Cache controller,
+* saves the counter values and resets the counters.
+*
+* @param EveCtr0: Output parameter which is used to return the value
+* in event counter 0.
+* EveCtr1: Output parameter which is used to return the value
+* in event counter 1.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+ /* Disable counter */
+ *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+ /* Save counter values */
+ *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+ *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+ XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d0a61f07d193f41dc887b73052a3be9b1b5b78f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+*
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
new file mode 100644
index 0000000000000000000000000000000000000000..0fa77710d14ea0476deb274aaa458285bfb8cf84
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
@@ -0,0 +1,338 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c08e5f2eacdaed8f0a9eeaf2f9e7e2c81408a79
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00 pkp 12/15/14 Initial release
+* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
+* mode
+* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* ms 06/13/17 Added PSU_PMU macro to provide support of
+* XGetPlatform_Info function for PMUFW.
+* mus 08/17/17 Add EL1 NS mode support for
+* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+* APIs.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about platform
+*
+* @param None.
+*
+* @return The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+ return XPLAT_MICROBLAZE;
+#else
+ return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about zynq ultrascale MP platform
+*
+* @param None.
+*
+* @return The information about zynq ultrascale MP platform defined in
+* xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+#if EL1_NONSECURE
+ XSmc_OutVar reg;
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
+ u32 reg;
+ reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+ return reg;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about PS Silicon version
+*
+* @param None.
+*
+* @return The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info()
+{
+#if EL1_NONSECURE
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ XSmc_OutVar reg;
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK);
+#else
+ u32 reg;
+ reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+ & XPS_VERSION_INFO_MASK);
+ return reg;
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..0582222bc9d6b07a08f87199fc8f7622c6c3f6cb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+*
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0765b60076862a675c91d72797f82b86783d86f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
@@ -0,0 +1,297 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+* Xpm_ResetEventCounters to fix CR#796275
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+ /* Disable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function enables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+ /* Enable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+ u32 Reg;
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+ { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+ Reg = C15Reg; }
+#endif
+ Reg |= (1U << 1U); /* reset event counters */
+ mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief This function configures the Cortex A9 event counters controller,
+* with the event codes, in a configuration selected by the user and
+* enables the counters.
+*
+* @param PmcrCfg: Configuration value based on which the event counters
+* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+* be utilized for setting configuration.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+ u32 Counter;
+ static PmcrEventCfg32 PmcrEvents[] = {
+ {
+ XPM_EVENT_SOFTINCR,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ {
+ XPM_EVENT_DATA_READS,
+ XPM_EVENT_DATA_WRITE,
+ XPM_EVENT_EXCEPTION,
+ XPM_EVENT_EXCEPRETURN,
+ XPM_EVENT_CHANGECONTEXT,
+ XPM_EVENT_SW_CHANGEPC
+ },
+ {
+ XPM_EVENT_IMMEDBRANCH,
+ XPM_EVENT_UNALIGNEDACCESS,
+ XPM_EVENT_BRANCHMISS,
+ XPM_EVENT_CLOCKCYCLES,
+ XPM_EVENT_BRANCHPREDICT,
+ XPM_EVENT_JAVABYTECODE
+ },
+ {
+ XPM_EVENT_SWJAVABYTECODE,
+ XPM_EVENT_JAVABACKBRANCH,
+ XPM_EVENT_COHERLINEMISS,
+ XPM_EVENT_COHERLINEHIT,
+ XPM_EVENT_INSTRSTALL,
+ XPM_EVENT_DATASTALL
+ },
+ {
+ XPM_EVENT_MAINTLBSTALL,
+ XPM_EVENT_STREXPASS,
+ XPM_EVENT_STREXFAIL,
+ XPM_EVENT_DATAEVICT,
+ XPM_EVENT_NODISPATCH,
+ XPM_EVENT_ISSUEEMPTY
+ },
+ {
+ XPM_EVENT_INSTRRENAME,
+ XPM_EVENT_PREDICTFUNCRET,
+ XPM_EVENT_MAINEXEC,
+ XPM_EVENT_SECEXEC,
+ XPM_EVENT_LDRSTR,
+ XPM_EVENT_FLOATRENAME
+ },
+ {
+ XPM_EVENT_NEONRENAME,
+ XPM_EVENT_PLDSTALL,
+ XPM_EVENT_WRITESTALL,
+ XPM_EVENT_INSTRTLBSTALL,
+ XPM_EVENT_DATATLBSTALL,
+ XPM_EVENT_INSTR_uTLBSTALL
+ },
+ {
+ XPM_EVENT_DATA_uTLBSTALL,
+ XPM_EVENT_DMB_STALL,
+ XPM_EVENT_INT_CLKEN,
+ XPM_EVENT_DE_CLKEN,
+ XPM_EVENT_INSTRISB,
+ XPM_EVENT_INSTRDSB
+ },
+ {
+ XPM_EVENT_INSTRDMB,
+ XPM_EVENT_EXTINT,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_PLE_OVFL,
+ XPM_EVENT_PLE_PROG,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_DATASTALL,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ };
+ const u32 *ptr = PmcrEvents[PmcrCfg];
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ /* Selecet event counter */
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+ /* Set the event */
+ mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+ }
+
+ Xpm_ResetEventCounters();
+ Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters and returns the counter
+* values.
+*
+* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+* It is an output parameter which is used to return the PM
+* counter values.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+ u32 Counter;
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+ { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+ PmCtrValue[Counter] = Cp15Reg; }
+#endif
+ }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..45f091982497d96d757ce80559712dbd227905e6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+*
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
new file mode 100644
index 0000000000000000000000000000000000000000..4ad9e5d73cf6aa041462b24325df210f40a23bd4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..37971bc59d96983f89152b26e5bb97bdb58e62a5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc9a4ebd2c36ac3f03ad6816b05610129a6a7943
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
new file mode 100644
index 0000000000000000000000000000000000000000..993747588d94aa9364dfacd1f14cd5970331d66a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
new file mode 100644
index 0000000000000000000000000000000000000000..e81643f90b96461dbffec7b7a27dfdd234bd7dc5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+*
+*
+* @note None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief Set the time in the Global Timer Counter Register.
+*
+* @param Xtime_Global: 64-bit Value to be written to the Global Timer
+* Counter Register.
+*
+* @return None.
+*
+* @note When this function is called by any one processor in a multi-
+* processor environment, reference time will reset/lost for all
+* processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+ /* Disable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+ /* Updating Global Timer Counter Register */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+ (u32)((u32)(Xtime_Global>>32U)));
+
+ /* Enable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief Get the time from the Global Timer Counter Register.
+*
+* @param Xtime_Global: Pointer to the 64-bit location which will be
+* updated with the current timer value.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+ u32 low;
+ u32 high;
+
+ /* Reading Global Timer Counter Register */
+ do
+ {
+ high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+ low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+ } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+ *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b872b6cb696a54594707facec1b228bd9facc42
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+*
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c
new file mode 100644
index 0000000000000000000000000000000000000000..88f96d74d61ce0c212afc99019a0d1ec5c4da2b6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c
@@ -0,0 +1,448 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+* to stop the timer before configuring
+* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+* 32 bit interval count for zynq ultrascale+mpsoc
+* 3.5 srm 10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue
+* APIs to use correct match register width for zynq
+* (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit).
+* It fixes CR# 986617
+* 3.6 srm 04/25/18 Corrected the Match register initialization in
+ XTtcPs_CfgInitialize API.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+* - Overflow Mode
+* - Internal (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific TTC device.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, then use
+* ConfigPtr->BaseAddress for this parameter, passing the physical
+* address instead.
+*
+* @return
+*
+* - XST_SUCCESS if the initialization is successful.
+* - XST_DEVICE_IS_STARTED if the device is started. It must be
+* stopped to re-initialize.
+*
+* @note Device has to be stopped first to call this function to
+* initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ u32 IsStartResult;
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * Set some default values
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+ IsStartResult = XTtcPs_IsStarted(InstancePtr);
+ /*
+ * If the timer counter has already started, return an error
+ * Device should be stopped first.
+ */
+ if(IsStartResult == (u32)TRUE) {
+ Status = XST_DEVICE_IS_STARTED;
+ } else {
+
+ /*
+ * stop the timer before configuring
+ */
+ XTtcPs_Stop(InstancePtr);
+ /*
+ * Reset the count control register to it's default value.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET,
+ XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+ /*
+ * Reset the rest of the registers to the default values.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_0_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_1_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_MATCH_2_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_IER_OFFSET, 0x00U);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Reset the counter value
+ */
+ XTtcPs_ResetCounterValue(InstancePtr);
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param MatchIndex is the index to the match register to be set.
+* Valid values are 0, 1, or 2.
+* @param Value is the 16-bit value to be set in the match register.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value)
+{
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+ /*
+ * Write the value to the correct match register with MatchIndex
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param MatchIndex is the index to the match register to be set.
+* Valid values are 0, 1, or 2.
+*
+* @return The match register value
+*
+* @note None
+*
+****************************************************************************/
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+ u32 MatchReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+ MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTtcPs_Match_N_Offset(MatchIndex));
+
+ return (XMatchRegValue) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param PrescalerValue is a number from 0-16 that sets the prescaler
+* to use.
+* If the parameter is 0 - 15, use a prescaler on the clock of
+* 2^(PrescalerValue+1), or 2-65536.
+* If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+* prescaler.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+ u32 ClockReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+ /*
+ * Read the clock control register
+ */
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register
+ */
+ ClockReg &=
+ ~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+ if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+ /*
+ * Set the prescaler value and enable prescaler
+ */
+ ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+ (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+ ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+ }
+
+ /*
+ * Write the register with the new values.
+ */
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+*
+* @return The value(n) from which the prescalar value is calculated
+* as 2^(n+1). Some example values are given below :
+*
+* Value Prescaler
+* 0 2
+* 1 4
+* N 2^(n+1)
+* 15 65536
+* 16 1
+*
+*
+* @note None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+ u8 Status;
+ u32 ClockReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the clock control register
+ */
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+
+ if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+ /*
+ * Prescaler is disabled. Return the correct flag value
+ */
+ Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+ }
+ else {
+
+ Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+ (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Freq is the requested output frequency for the device.
+* @param Interval is the interval value for the given frequency,
+* it is the output value for this function.
+* @param Prescaler is the prescaler value for the given frequency,
+* it is the output value for this function.
+*
+* @return None.
+*
+* @note
+* Upon successful calculation for the given frequency, Interval and Prescaler
+* carry the settings for the timer counter; Upon unsuccessful calculation,
+* Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+* signal the caller of failure. Therefore, caller needs to check the return
+* interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler)
+{
+ u8 TmpPrescaler;
+ u32 TempValue;
+ u32 InputClock;
+
+ InputClock = InstancePtr->Config.InputClockHz;
+ /*
+ * Find the smallest prescaler that will work for a given frequency. The
+ * smaller the prescaler, the larger the count and the more accurate the
+ * PWM setting.
+ */
+ TempValue = InputClock/ Freq;
+
+ if (TempValue < 4U) {
+ /*
+ * The frequency is too high, it is too close to the input
+ * clock value. Use maximum values to signal caller.
+ */
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
+ *Prescaler = 0xFFU;
+ return;
+ }
+
+ /*
+ * First, do we need a prescaler or not?
+ */
+ if (((u32)65536U) > TempValue) {
+ /*
+ * We do not need a prescaler, so set the values appropriately
+ */
+ *Interval = (XInterval)TempValue;
+ *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+ return;
+ }
+
+
+ for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+ TmpPrescaler++) {
+ TempValue = InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+ /*
+ * The first value less than 2^16 is the best bet
+ */
+ if (((u32)65536U) > TempValue) {
+ /*
+ * Set the values appropriately
+ */
+ *Interval = (XInterval)TempValue;
+ *Prescaler = TmpPrescaler;
+ return;
+ }
+ }
+
+ /* Can not find interval values that work for the given frequency.
+ * Return maximum values to signal caller.
+ */
+ *Interval = XTTCPS_MAX_INTERVAL_COUNT;
+ *Prescaler = 0XFFU;
+ return;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b7b4e1950d5ab0c6a73ab70616dd549f8143d078
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h
@@ -0,0 +1,467 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_5
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+* . At a regular, predefined period, that is on a timed interval
+* . When the counter registers overflow
+* . When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+* - Overflow Mode
+* - Internal clock (pclk) selected
+* - Counter disabled
+* - All Interrupts disabled
+* - Output waveforms disabled
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
+* modified for MISRA-C:2012 compliance.
+* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+* macros to return 32 bit values for zynq ultrascale+mpsoc
+* ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of ttcps in xparameters.h
+* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
+*
+*
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H /* prevent circular inclusions */
+#define XTTCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
+ external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID for device */
+ u32 BaseAddress; /**< Base address for device */
+ u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+ XTtcPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count and Match register value
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+typedef u16 XMatchRegValue;
+#else
+typedef u32 XInterval;
+typedef u32 XMatchRegValue;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+ (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+ (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance
+*
+* @return Non-zero if the device has started, '0' otherwise.
+*
+* @note C-style signature:
+* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+ ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+ XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit counter value.
+* zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Value is the 16-bit value to be set in the interval register.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value) \
+ InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return zynq:16 bit interval value.
+* zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note C-style signature:
+* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None
+*
+* @note C-style signature:
+* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+ InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+ (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be enabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be enabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
+ (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be disabled.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be disabled, cleared bits
+* will not be disabled.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
+ (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
+ ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr) \
+ InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param InterruptMask defines which interrupt should be cleared.
+* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+* This is a bit mask, all set bits will be cleared, cleared bits
+* will not be cleared.
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+ InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+ (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+ XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+ XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..f88e5efbb920aafaee0121ef5da4eda42c6d2051
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c
@@ -0,0 +1,66 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+ {
+ XPAR_PS7_TTC_0_DEVICE_ID,
+ XPAR_PS7_TTC_0_BASEADDR,
+ XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
+ },
+ {
+ XPAR_PS7_TTC_1_DEVICE_ID,
+ XPAR_PS7_TTC_1_BASEADDR,
+ XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
+ },
+ {
+ XPAR_PS7_TTC_2_DEVICE_ID,
+ XPAR_PS7_TTC_2_BASEADDR,
+ XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..b1fa545bda22600511bbb0c4560a3c6729ae4678
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h
@@ -0,0 +1,233 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+* mask 16 bit values for zynq and 32 bit values for
+* zynq ultrascale+mpsoc "
+*
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H /* prevent circular inclusions */
+#define XTTCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */
+#endif
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */
+#endif
+#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param BaseAddress is the base address of the timer counter device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param MatchIndex is the 0-2 value of the match register
+*
+* @return MATCH_N_OFFSET.
+*
+* @note C-style signature:
+* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+ ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..01dd9efb33f7d711921577aaf4327a62121c2dbb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c
@@ -0,0 +1,243 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm 03/05/2012 Removed break statement after return to remove
+* compilation warnings.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+ u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+ {XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+ XTTCPS_CLK_CNTRL_OFFSET},
+ {XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+ XTTCPS_CLK_CNTRL_OFFSET},
+ {XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+ {XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+ XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+ sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on, and a 0 means to
+* turn the option off. One or more bit values may be contained
+* in the mask. See the bit definitions named XTTCPS_*_OPTION in
+* the file xttcps.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_FAILURE if any of the options are unknown.
+*
+* @note None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+ u32 CountReg;
+ u32 ClockReg;
+ u32 Index;
+ s32 Status = XST_SUCCESS;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET);
+ CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET);
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+ if(Status != (s32)XST_FAILURE) {
+ if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+ switch (TmrCtrOptionsTable[Index].Register) {
+
+ case XTTCPS_CLK_CNTRL_OFFSET:
+ /* Add option */
+ ClockReg |= TmrCtrOptionsTable[Index].Mask;
+ break;
+
+ case XTTCPS_CNT_CNTRL_OFFSET:
+ /* Add option */
+ CountReg |= TmrCtrOptionsTable[Index].Mask;
+ break;
+
+ default:
+ Status = XST_FAILURE;
+ break;
+ }
+ }
+ else {
+ switch (TmrCtrOptionsTable[Index].Register) {
+
+ case XTTCPS_CLK_CNTRL_OFFSET:
+ /* Remove option*/
+ ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+ break;
+
+ case XTTCPS_CNT_CNTRL_OFFSET:
+ /* Remove option*/
+ CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+ break;
+
+ default:
+ Status = XST_FAILURE;
+ break;
+ }
+ }
+ }
+ }
+
+ /*
+ * Now write the registers. Leave it to the upper layers to restart the
+ * device.
+ */
+ if (Status != (s32)XST_FAILURE ) {
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+ XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+ u32 OptionsFlag = 0U;
+ u32 Register;
+ u32 Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * Loop through the options table to determine which options are set
+ */
+ for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+ /*
+ * Get the control register to determine which options are
+ * currently set.
+ */
+ Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ TmrCtrOptionsTable[Index].
+ Register);
+
+ if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+ OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+ }
+ }
+
+ return OptionsFlag;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..b1dd7d0a204a34b49ff29dbb7321985338962872
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* - XST_SUCCESS if successful
+* - XST_FAILURE indicates a register did not read or write correctly
+*
+* @note This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+ s32 Status;
+ u32 TempReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * All the TTC registers should be in their default state right now.
+ */
+ TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XTTCPS_CNT_CNTRL_OFFSET);
+ if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+ Status = XST_FAILURE;
+ }
+ else {
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..4684c8a9c604f32b453484c5475edc9610c1234d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+ XTtcPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+ if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XTtcPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
new file mode 100644
index 0000000000000000000000000000000000000000..c33ec5481ebb744b1384eb4881ef7a76d98dbb9b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
@@ -0,0 +1,645 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount);
+
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XUartPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, pass in the physical
+* address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+* - XST_UART_BAUD_ERROR if the baud rate is not possible because
+* the inputclock frequency is not divisible with an acceptable
+* amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr)
+{
+ s32 Status;
+ u32 ModeRegister;
+ u32 BaudRate;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /* Setup the driver instance using passed in parameters */
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = Config->InputClockHz;
+ InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+ /* Initialize other instance data to default values */
+ InstancePtr->Handler = XUartPs_StubHandler;
+
+ InstancePtr->SendBuffer.NextBytePtr = NULL;
+ InstancePtr->SendBuffer.RemainingBytes = 0U;
+ InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+ InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+ InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+ InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+ /* Initialize the platform data */
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ InstancePtr->is_rxbs_error = 0U;
+
+ /* Flag that the driver instance is ready to use */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Set the default baud rate here, can be changed prior to
+ * starting the device
+ */
+ BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+ Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ InstancePtr->IsReady = 0U;
+ } else {
+
+ /*
+ * Set up the default data format: 8 bit data, 1 stop bit, no
+ * parity
+ */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Mask off what's already there */
+ ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+ (u32)XUARTPS_MR_STOPMODE_MASK |
+ (u32)XUARTPS_MR_PARITY_MASK));
+
+ /* Set the register value to the desired data format */
+ ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
+ (u32)XUARTPS_MR_STOPMODE_1_BIT |
+ (u32)XUARTPS_MR_PARITY_NONE);
+
+ /* Write the mode register out */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ /* Set the RX FIFO trigger at 8 data bytes. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, 0x08U);
+
+ /* Set the RX timeout to 1, which will be 4 character time */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+ /* Disable all interrupts, polled mode is the default */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param BufferPtr is pointer to a buffer of data to be sent.
+* @param NumBytes contains the number of bytes to be sent. A value of
+* zero will stop a previous send operation that is in progress
+* in interrupt mode. Any data that was already put into the
+* transmit FIFO will be sent.
+*
+* @return The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+*
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+ u32 NumBytes)
+{
+ u32 BytesSent;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the UART transmit interrupts to allow this call to stop a
+ * previous operation that may be interrupt driven.
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+ /* Setup the buffer parameters */
+ InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+ InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+ InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+ /*
+ * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+ * filling the TX FIFO.
+ */
+ BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+ return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BufferPtr is pointer to buffer for data to be received into
+* @param NumBytes is the number of bytes to be received. A value of zero
+* will stop a previous receive operation that is in progress in
+* interrupt mode.
+*
+* @return The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+ u8 *BufferPtr, u32 NumBytes)
+{
+ u32 ReceivedCount;
+ u32 ImrRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable all the interrupts.
+ * This stops a previous operation that may be interrupt driven
+ */
+ ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup the buffer parameters */
+ InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+ /* Receive the data from the device */
+ ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+ /* Restore the interrupt state */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ ImrRegister);
+
+ return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes actually sent
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+ u32 SentCount = 0U;
+ u32 ImrRegister;
+
+ /*
+ * If the TX FIFO is full, send nothing.
+ * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+ * data has been put into the FIFO.
+ */
+ while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+ (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+ /* Fill the FIFO from the buffer */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FIFO_OFFSET,
+ ((u32)InstancePtr->SendBuffer.
+ NextBytePtr[SentCount]));
+
+ /* Increment the send count. */
+ SentCount++;
+ }
+
+ /* Update the buffer to reflect the bytes that were sent from it */
+ InstancePtr->SendBuffer.NextBytePtr += SentCount;
+ InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+ /*
+ * If interrupts are enabled as indicated by the receive interrupt, then
+ * enable the TX FIFO empty interrupt, so further action can be taken
+ * for this sending.
+ */
+ ImrRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+ ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+ ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET,
+ ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+ }
+
+ return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes received.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+ u32 CsrRegister;
+ u32 ReceivedCount = 0U;
+ u32 ByteStatusValue, EventData;
+ u32 Event;
+
+ /*
+ * Read the Channel Status Register to determine if there is any data in
+ * the RX FIFO
+ */
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * Loop until there is no more data in RX FIFO or the specified
+ * number of bytes has been received
+ */
+ while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+ (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+ if (InstancePtr->is_rxbs_error) {
+ ByteStatusValue = XUartPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XUARTPS_RXBS_OFFSET);
+ if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+ EventData = ByteStatusValue;
+ Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event, EventData);
+ }
+ }
+
+ InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+ XUartPs_ReadReg(InstancePtr->Config.
+ BaseAddress,
+ XUARTPS_FIFO_OFFSET);
+
+ ReceivedCount++;
+
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+ }
+ InstancePtr->is_rxbs_error = 0;
+ /*
+ * Update the receive buffer to reflect the number of bytes just
+ * received
+ */
+ if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+ InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+ }
+ InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+ return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BaudRate to be set
+*
+* @return
+* - XST_SUCCESS if everything configured as expected
+* - XST_UART_BAUD_ERROR if the requested rate is not available
+* because there was too much error
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+ u32 IterBAUDDIV; /* Iterator for available baud divisor values */
+ u32 BRGR_Value; /* Calculated value for baud rate generator */
+ u32 CalcBaudRate; /* Calculated baud rate */
+ u32 BaudError; /* Diff between calculated and requested baud rate */
+ u32 Best_BRGR = 0U; /* Best value for baud rate generator */
+ u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
+ u32 Best_Error = 0xFFFFFFFFU;
+ u32 PercentError;
+ u32 ModeReg;
+ u32 InputClk;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+ Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+ /*
+ * Make sure the baud rate is not impossilby large.
+ * Fastest possible baud rate is Input Clock / 2.
+ */
+ if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+ return XST_UART_BAUD_ERROR;
+ }
+ /* Check whether the input clock is divided by 8 */
+ ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ InputClk = InstancePtr->Config.InputClockHz;
+ if(ModeReg & XUARTPS_MR_CLKSEL) {
+ InputClk = InstancePtr->Config.InputClockHz / 8;
+ }
+
+ /*
+ * Determine the Baud divider. It can be 4to 254.
+ * Loop through all possible combinations
+ */
+ for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+ /* Calculate the value for BRGR register */
+ BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+ /* Calculate the baud rate from the BRGR value */
+ CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+ /* Avoid unsigned integer underflow */
+ if (BaudRate > CalcBaudRate) {
+ BaudError = BaudRate - CalcBaudRate;
+ }
+ else {
+ BaudError = CalcBaudRate - BaudRate;
+ }
+
+ /* Find the calculated baud rate closest to requested baud rate. */
+ if (Best_Error > BaudError) {
+
+ Best_BRGR = BRGR_Value;
+ Best_BAUDDIV = IterBAUDDIV;
+ Best_Error = BaudError;
+ }
+ }
+
+ /* Make sure the best error is not too large. */
+ PercentError = (Best_Error * 100) / BaudRate;
+ if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+ return XST_UART_BAUD_ERROR;
+ }
+
+ /* Disable TX and RX to avoid glitches when setting the baud rate. */
+ XUartPs_DisableUart(InstancePtr);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+ /* RX and TX SW reset */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+ /* Enable device */
+ XUartPs_EnableUart(InstancePtr);
+
+ InstancePtr->BaudRate = BaudRate;
+
+ return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param CallBackRef is unused by this function.
+* @param Event is unused by this function.
+* @param ByteCount is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount)
+{
+ (void) CallBackRef;
+ (void) Event;
+ (void) ByteCount;
+ /* Assert occurs always since this is a stub and should never be called */
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
new file mode 100644
index 0000000000000000000000000000000000000000..33758c23b3733d2ffce9e1b8a27bfbdc22e0f4d1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..29566204605a56c79aa4371f56dc4503e4ad7fb3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_UART_1_DEVICE_ID,
+ XPAR_PS7_UART_1_BASEADDR,
+ XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+ XPAR_PS7_UART_1_HAS_MODEM
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..724c3cb40ece5f6cdea32bb885f3d15f2992ed4b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_5
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.05a hk 08/22/13 Added reset function
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param Data contains the byte to be sent.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+ /* Wait until there is space in TX FIFO */
+ while (XUartPs_IsTransmitFull(BaseAddress)) {
+ ;
+ }
+
+ /* Write the byte into the TX FIFO */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return The data byte received.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+ u32 RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+ /* Return the byte received */
+ return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+ /* Disable interrupts */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+ /* Disable receive and transmit */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+ /*
+ * Software reset of receive and transmit
+ * This clears the FIFO.
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+ /* Clear status flags - SW reset wont clear sticky flags. */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+ /*
+ * Mode register reset value : All zeroes
+ * Normal mode, even parity, 1 stop bit
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+ XUARTPS_MR_CHMODE_NORM);
+
+ /* Rx and TX trigger register reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+ XUARTPS_RXWM_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+ XUARTPS_TXWM_RESET_VAL);
+
+ /* Rx timeout disabled by default */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+ XUARTPS_RXTOUT_DISABLE);
+
+ /* Baud rate generator and dividor reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+ XUARTPS_BAUDGEN_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+ XUARTPS_BAUDDIV_RESET_VAL);
+
+ /*
+ * Control register reset value -
+ * RX and TX are disable by default
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+ (u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..9a2bc430544035bcbde490106a1b9b1f2c4c09cd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
@@ -0,0 +1,451 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+*
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..dff02fd6307c53fb6784df2c60814a4e6c300336
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* The current interrupt mask. The mask indicates which interupts
+* are enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+ /* Assert validates the input argument */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Read the Interrupt Mask register */
+ return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param Mask contains the interrupts to be enabled or disabled.
+* A '1' enables an interupt, and a '0' disables.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+ u32 TempMask = Mask;
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ TempMask &= (u32)XUARTPS_IXR_MASK;
+
+ /* Write the mask to the IER Register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET, TempMask);
+
+ /* Write the inverse of the Mask to the IDR register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param FuncPtr is the pointer to the callback function.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+*
+* @return None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = FuncPtr;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param InstancePtr contains a pointer to the driver instance
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+ u32 IsrStatus;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the interrupt ID register to determine which
+ * interrupt is active
+ */
+ IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+
+ IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_ISR_OFFSET);
+
+ /* Dispatch an appropriate handler. */
+ if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+ (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+ /* Received data interrupt */
+ ReceiveDataHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+ != (u32)0) {
+ /* Transmit data interrupt */
+ SendDataHandler(InstancePtr, IsrStatus);
+ }
+
+ /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+ if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+ (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+ /* Received Error Status interrupt */
+ ReceiveErrorHandler(InstancePtr, IsrStatus);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+ /* Received Timeout interrupt */
+ ReceiveTimeoutHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+ /* Modem status interrupt */
+ ModemHandler(InstancePtr);
+ }
+
+ /* Clear the interrupt status. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+ IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+ u32 EventData;
+ u32 Event;
+
+ InstancePtr->is_rxbs_error = 0;
+
+ if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+ (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+ | (u32)XUARTPS_IXR_FRAMING))) {
+ InstancePtr->is_rxbs_error = 1;
+ }
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+
+ if (!(InstancePtr->is_rxbs_error)) {
+ Event = XUARTPS_EVENT_RECV_ERROR;
+ EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes;
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event,
+ EventData);
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+ u32 Event;
+
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /*
+ * If there are no more bytes to receive then indicate that this is
+ * not a receive timeout but the end of the buffer reached, a timeout
+ * normally occurs if # of bytes is not divisible by FIFO threshold,
+ * don't rely on previous test of remaining bytes since receive
+ * function updates it
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ Event = XUARTPS_EVENT_RECV_TOUT;
+ } else {
+ Event = XUARTPS_EVENT_RECV_DATA;
+ }
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * timeout or data event
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+ InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /* If the last byte of a message was received then call the application
+ * handler, this code should not use an else from the previous check of
+ * the number of bytes to receive because the call to receive the buffer
+ * updates the bytes ramained
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_RECV_DATA,
+ (InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes));
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param IsrStatus is the register value for channel status register
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+ /*
+ * If there are not bytes to be sent from the specified buffer then disable
+ * the transmit interrupt so it will stop interrupting as it interrupts
+ * any time the FIFO is empty
+ */
+ if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET,
+ ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+ /* Call the application handler to indicate the sending is done */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_SENT_DATA,
+ InstancePtr->SendBuffer.RequestedBytes -
+ InstancePtr->SendBuffer.RemainingBytes);
+ }
+
+ /* If TX FIFO is empty, send more. */
+ else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+ (void)XUartPs_SendBuffer(InstancePtr);
+ }
+ else {
+ /* Else with dummy entry for MISRA-C Compliance.*/
+ ;
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts. It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+ u32 MsrRegister;
+
+ /*
+ * Read the modem status register so that the interrupt is acknowledged
+ * and it can be passed to the callback handler with the event
+ */
+ MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+
+ /*
+ * Call the application handler to indicate the modem status changed,
+ * passing the modem status and the event data in the call
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_MODEM,
+ MsrRegister);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..5d8d3017cbf5e34ca05af51d0216d2f542b977d5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
@@ -0,0 +1,764 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+* value was not being written to the register.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+ u16 Option;
+ u16 RegisterOffset;
+ u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+ {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+ {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+ {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+ {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+ {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+ {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_RTS},
+ {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_DTR},
+ {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+ u16 Options = 0U;
+ u32 Register;
+ u32 Index;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop thru the options table to map the physical options in the
+ * registers of the UART to the logical options to be returned
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the bit in the register which correlates to the option
+ * is set, then set the corresponding bit in the options,
+ * ignoring any bits which are zero since the options variable
+ * is initialized to zero
+ */
+ if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+ Options |= OptionsTable[Index].Option;
+ }
+ }
+
+ return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Options contains the options to be set which are bit masks
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+ u32 Index;
+ u32 Register;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop thru the options table to map the logical options to the
+ * physical options in the registers of the UART.
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+ /*
+ * Read the register which contains option so that the register
+ * can be changed without destoying any other bits of the
+ * register.
+ */
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the option is set in the input, then set the corresponding
+ * bit in the specified register, otherwise clear the bit in
+ * the register.
+ */
+ if ((Options & OptionsTable[Index].Option) != (u16)0) {
+ if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+ Register &= ~XUARTPS_CR_STOPBRK;
+ Register |= OptionsTable[Index].Mask;
+ }
+ else {
+ Register &= ~OptionsTable[Index].Mask;
+ }
+
+ /* Write the new value to the register to set the option */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].RegisterOffset,
+ Register);
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current receive FIFO trigger level. This is a value
+* from 0-31.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+ u8 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the value of the FIFO control register so that the threshold
+ * can be retrieved, this read takes special register processing
+ */
+ RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET);
+
+ /* Return only the trigger level from the register value */
+
+ RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+ return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param TriggerLevel contains the trigger level to set.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+ u32 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+ /*
+ * Write the new value for the FIFO control register to it such that the
+ * threshold is changed
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+ u32 ModemStatusRegister;
+ u16 TmpRegister;
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the modem status register to return
+ */
+ ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+ TmpRegister = (u16)ModemStatusRegister;
+ return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if the UART is sending data
+* - FALSE if UART is not sending data
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+ u32 ChanStatRegister;
+ u32 ChanTmpSRegister;
+ u32 ActiveResult;
+ u32 EmptyResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel status register to determine if the transmitter is
+ * active
+ */
+ ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * If the transmitter is active, or the TX FIFO is not empty, then indicate
+ * that the UART is still sending some data
+ */
+ ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+ EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+ ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+ (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+ return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+ u32 ModeRegister;
+ u8 OperMode;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+ /* Return the constant */
+ switch (ModeRegister) {
+ case XUARTPS_MR_CHMODE_NORM:
+ OperMode = XUARTPS_OPER_MODE_NORMAL;
+ break;
+ case XUARTPS_MR_CHMODE_ECHO:
+ OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+ break;
+ case XUARTPS_MR_CHMODE_L_LOOP:
+ OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+ break;
+ case XUARTPS_MR_CHMODE_R_LOOP:
+ OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+ break;
+ default:
+ OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+ XUARTPS_MR_CHMODE_SHIFT);
+ break;
+ }
+
+ return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param OperationMode is the mode of the UART.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+ u32 ModeRegister;
+
+ /* Assert validates the input arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Set the correct value by masking the bits, then ORing the const. */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+ switch (OperationMode) {
+ case XUARTPS_OPER_MODE_NORMAL:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+ break;
+ case XUARTPS_OPER_MODE_AUTO_ECHO:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+ break;
+ case XUARTPS_OPER_MODE_LOCAL_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+ break;
+ case XUARTPS_OPER_MODE_REMOTE_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+ break;
+ default:
+ /* Default case made for MISRA-C Compliance. */
+ break;
+ }
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+ u32 FdelTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET);
+
+ /* Return the contents of the flow delay register */
+ FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+ return FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FlowDelayValue is the Setting for the flow delay.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+ u32 FdelRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Set the correct value by shifting the input constant, then masking
+ * the bits
+ */
+ FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current setting for receive time out.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+ u32 RtoRegister;
+ u8 RtoRTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Receive Timeout register. */
+ RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET);
+
+ /* Return the contents of the mode register shifted appropriately */
+ RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+ return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RecvTimeout setting allows the UART to detect an idle connection
+* on the reciever data line.
+* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+* timeout function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+ u32 RtoRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Set the correct value by masking the bits */
+ RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+ /* Configure CR to restart the receiver timeout counter */
+ RtoRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_CR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure containing the data
+* format to be set.
+*
+* @return
+* - XST_SUCCESS if the data format was successfully set.
+* - XST_UART_BAUD_ERROR indicates the baud rate could not be
+* set because of the amount of error with the baud rate and
+* the input clock frequency.
+* - XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+*
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+ XUartPsFormat * FormatPtr)
+{
+ s32 Status;
+ u32 ModeRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FormatPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Verify the inputs specified are valid */
+ if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+ (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+ (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+ Status = XST_INVALID_PARAM;
+ } else {
+
+ /*
+ * Try to set the baud rate and if it's not successful then don't
+ * continue altering the data format, this is done first to avoid the
+ * format from being altered when an error occurs
+ */
+ Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ ;
+ } else {
+
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /*
+ * Set the length of data (8,7,6) by first clearing out the bits
+ * that control it in the register, then set the length in the register
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+ ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+ /*
+ * Set the number of stop bits in the mode register by first clearing
+ * out the bits that control it in the register, then set the number
+ * of stop bits in the register.
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+ ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+ /*
+ * Set the parity by first clearing out the bits that control it in the
+ * register, then set the bits in the register, the default is no parity
+ * after clearing the register bits
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+ ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+ /* Update the mode register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ Status = XST_SUCCESS;
+ }
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure that will contain
+* the data format after this call completes.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+ u32 ModeRegister;
+
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FormatPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the baud rate from the instance, this is not retrieved from the
+ * hardware because it is only kept as a divisor such that it is more
+ * difficult to get back to the baud rate
+ */
+ FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Get the length of data (8,7,6,5) */
+ FormatPtr->DataBits =
+ ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+ XUARTPS_MR_CHARLEN_SHIFT);
+
+ /* Get the number of stop bits */
+ FormatPtr->StopBits =
+ (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+ XUARTPS_MR_STOPMODE_SHIFT);
+
+ /* Determine what parity is */
+ FormatPtr->Parity =
+ (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+ XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..de58201a10defbbfdf435648be1c0aaa9f4ef924
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+* - XST_SUCCESS if the test was successful
+* - XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrRegister;
+ u32 ModeRegister;
+ u8 Index;
+ u32 ReceiveDataResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts in the interrupt disable register */
+ IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup for local loopback */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+ (u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+ /* Send a number of bytes and receive them, one at a time. */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ /*
+ * Send out the byte and if it was not sent then the failure
+ * will be caught in the comparison at the end
+ */
+ (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+ /*
+ * Wait until the byte is received. This can hang if the HW
+ * is broken. Watch for the FIFO empty flag to be false.
+ */
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ }
+
+ /* Receive the byte */
+ (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+ }
+
+ /*
+ * Compare the bytes received to the bytes sent to verify the exact data
+ * was received
+ */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ if (TestString[Index] != ReturnString[Index]) {
+ Status = XST_UART_TEST_FAIL;
+ }
+ }
+
+ /*
+ * Restore the registers which were altered to put into polling and
+ * loopback modes so that this test is not destructive
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ IntrRegister);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..22e2f7a83c0ee9f82e0659b6e4f6e4f2628a87c7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return A pointer to the configuration structure or NULL if the
+* specified device is not in the system.
+*
+* @note None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+ XUartPs_Config *CfgPtr = NULL;
+
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+ if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XUartPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
new file mode 100644
index 0000000000000000000000000000000000000000..b76c94a464535c5a1037e5452386357b7b613006
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The XUsbPs driver. Functions in this file are the minimum required
+ * functions for this driver. See xusbps.h for a detailed description of the
+ * driver.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 2.1 kpc 04/28/14 Removed ununsed functions
+ *
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+#include
+#include "xusbps.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a XUsbPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XUsbPs structure.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
+* structure. This structure will contain the requested
+* configuration for the device. Typically, this is a local
+* structure and the content of which will be copied into the
+* configuration structure within XUsbPs.
+* @param VirtBaseAddress is the base address of the device. For systems
+* with virtual memory, this address must be the virtual address
+* of the device.
+* For systems that do not support virtual memory this address
+* should be the physical address of the device. For backwards
+* compatibilty NULL may be passed in systems that do not support
+* virtual memory (deprecated).
+*
+* @return
+* - XST_SUCCESS no errors occured.
+* - XST_FAILURE an error occured during initialization.
+*
+* @note
+* After calling XUsbPs_CfgInitialize() the controller
+* IS NOT READY for use. Before the controller can be used its
+* DEVICE parameters must be configured. See xusbps.h
+* for details.
+*
+******************************************************************************/
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /* Copy the config structure. */
+ InstancePtr->Config = *ConfigPtr;
+
+ /* Check if the user provided a non-NULL base address. If so, we have
+ * to overwrite the base address in the configuration structure.
+ */
+ if (0 != VirtBaseAddress) {
+ InstancePtr->Config.BaseAddress = VirtBaseAddress;
+ }
+
+ /* Initialize the XUsbPs structure to default values. */
+ InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
+
+ InstancePtr->HandlerFunc = NULL;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs device reset, device is stopped at the end.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
+{
+ int Timeout;
+
+ /* Clear all setup token semaphores by reading the
+ * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+ * itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET));
+
+ /* Clear all the endpoint complete status bits by reading the
+ * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+ * to itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET));
+
+ /* Cancel all endpoint prime status by waiting until all bits
+ * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+ * to XUSBPS_EPFLUSH_OFFSET.
+ *
+ * Avoid hanging here by using a Timeout counter...
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET) &
+ XUSBPS_EP_ALL_MASK) && --Timeout) {
+ /* NOP */
+ }
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+ XUsbPs_Stop(InstancePtr);
+
+ /* Write to CR register for controller reset */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
+
+ /* Wait for reset to finish, hardware clears the reset bit once done */
+ Timeout = 1000000;
+ while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_RST_MASK) && --Timeout) {
+ /* NOP */
+ }
+}
+/*****************************************************************************/
+/**
+*
+* This function resets the USB device. All the configuration registers are
+* reset to their default values. The function waits until the reset operation
+* is complete or for a certain duration within which the reset operation is
+* expected to be completed.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS Reset operation completed successfully.
+* - XST_FAILURE Reset operation timed out.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_Reset(XUsbPs *InstancePtr)
+{
+ int Timeout;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
+ * RESET is complete.
+ *
+ * We are going to wait for the RESET bit to clear before we return
+ * from this function. Unfortunately we do not have timers available at
+ * this point to determine when we should report a Timeout.
+ *
+ * However, by using a large number for the poll loop we can assume
+ * that the polling operation will take longer than the expected time
+ * the HW needs to RESET. If the poll loop expires we can assume a
+ * Timeout. The drawback is that on a slow system (and even on a fast
+ * system) this can lead to _very_ long Timeout periods.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
+
+
+ /* Wait for the RESET bit to be cleared by HW. */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_RST_MASK) && --Timeout) {
+ /* NOP */
+ }
+
+ if (0 == Timeout) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * USB Suspend
+ *
+ * In order to conserve power, USB devices automatically enter the suspended
+ * state when the device has observed no bus traffic for a specified period.
+ * When suspended, the USB device maintains any internal status, including its
+ * address and configuration. Attached devices must be prepared to suspend at
+ * any time they are powered, regardless of if they have been assigned a
+ * non-default address, are configured, or neither. Bus activity may cease due
+ * to the host entering a suspend mode of its own. In addition, a USB device
+ * shall also enter the suspended state when the hub port it is attached to is
+ * disabled.
+ *
+ * A USB device exits suspend mode when there is bus activity. A USB device may
+ * also request the host to exit suspend mode or selective suspend by using
+ * electrical signaling to indicate remote wakeup. The ability of a device to
+ * signal remote wakeup is optional. If the USB device is capable of remote
+ * wakeup signaling, the device must support the ability of the host to enable
+ * and disable this capability. When the device is reset, remote wakeup
+ * signaling must be disabled.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ *
+ * @return
+ * - XST_SUCCESS if the USB device has entered Suspend mode
+ * successfully
+ * - XST_FAILURE on any error
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+int XUsbPs_Suspend(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Resume
+*
+ If the USB controller is suspended, its operation is resumed when any
+* non-idle signaling is received on its upstream facing port.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS if the USB device has Resumed successfully
+* - XST_FAILURE on any error
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_Resume(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Assert Resume
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - XST_SUCCESS if the USB device has Resumed successfully
+* - XST_FAILURE on any error
+*
+* @note None.
+*
+******************************************************************************/
+
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
+{
+ (void) InstancePtr;
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* This functions sets the controller's DEVICE address. It also sets the
+* advance bit so the controller will wait for the next IN-ACK before the new
+* address takes effect.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Address is the Address of the device.
+*
+* @return
+* - XST_SUCCESS: Address set successfully.
+* - XST_FAILURE: An error occured.
+* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
+* value too big.
+*
+* @note None.
+*
+*****************************************************************************/
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Check address range validity. */
+ if (Address > XUSBPS_DEVICEADDR_MAX) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Set the address register with the Address value provided. Also set
+ * the Address Advance Bit. This will cause the address to be set only
+ * after an IN occured and has been ACKed on the endpoint.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_DEVICEADDR_OFFSET,
+ (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
+ XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
+
+ return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
new file mode 100644
index 0000000000000000000000000000000000000000..b5c472ef9e3d912141993ac47da134013c9d3d06
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
@@ -0,0 +1,1098 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_4
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ *
Introduction
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ *
USB Controller Features
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ * High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ * cost connections
+ *
+ *
Initialization & Configuration
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ * In this stage the basic parameters for the driver are configured,
+ * including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ * If DEVICE mode is desired, the endpoints of the controller need to be
+ * configured using the XUsbPs_DeviceConfig data structure. Once the
+ * endpoint configuration is set up in the data structure, The user then
+ * needs to allocate the required amount of DMAable memory and
+ * finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ * e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ * In the second stage the parameters for DEVICE are configured.
+ * The caller only needs to configure the modes that are
+ * actually used. Configuration is done with the:
+ * XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ * into these functions using the:
+ * XUsbPs_DeviceConfig data structures.
+ *
+ *
+ *
USB Device Endpoints
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ *
Interrupt Handling
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ * - General device interrupts
+ * - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ * XUsbPs_IntrSetHandler()
+ * and
+ * XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ *
Data buffer handling
+ *
+ * Data buffers are sent to and received from endpoint using the
+ * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ * XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ *
Zero copy
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ *
DMA
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
+ * Tabs for CR 657898
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1 kpc 04/28/14 Removed unused function prototypes
+ * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ * code coverage tests.
+ * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ * moving of dTD Head/Tail Pointers. Invalidate the cache
+ * after buffer receive in Endpoint Buffer Handler.
+ * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ * ms 03/17/17 Added readme.txt file in examples folder for doxygen
+ * generation.
+ * ms 04/10/17 Modified filename tag to include the file in doxygen
+ * examples.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ * XUSBPS_CMD_OFFSET) &
+ * XUSBPS_CMD_RST_MASK) && --Timeout) {
+ * ;
+ * }
+ * if (0 == Timeout) {
+ * return XST_FAILURE;
+ * }
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER 1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ * The direction is always defined from the perspective of the HOST! This
+ * means that an IN endpoint on the controller is used for sending data while
+ * the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH 0x400
+#define ENDPOINT_MAXP_MULT_MASK 0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT 10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
+ /**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX 0x02
+ /**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX 0x03
+ /**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE 1024
+ /**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param EpNum is the Number of the endpoint that caused the event.
+ * @param EventType is the type of the event that occured on the endpoint.
+ * @param Data is a pointer to user data pointer specified when callback
+ * was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+ u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param CallBackRef is the Callback reference passed in by the upper
+ * layer when setting the handler, and is passed back to the upper
+ * layer when the handler is called.
+ * @param IrqMask is the Content of the interrupt status register. This
+ * value can be used by the callback function to distinguish the
+ * individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< Pointer to the first dTD of the dTD list for this
+ * endpoint. */
+
+ XUsbPs_dTD *dTDCurr;
+ /**< Buffer to the currently processed descriptor. */
+
+ u8 *dTDBufs;
+ /**< Pointer to the first buffer of the buffer list for this
+ * endpoint. */
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+ XUsbPs_dQH *dQH;
+ /**< Pointer to the Queue Head structure of the endpoint. */
+
+ XUsbPs_dTD *dTDs;
+ /**< List of pointers to the Transfer Descriptors of the
+ * endpoint. */
+
+ XUsbPs_dTD *dTDHead;
+ /**< Buffer to the next available descriptor in the list. */
+
+ XUsbPs_dTD *dTDTail;
+ /**< Buffer to the last unsent descriptor in the list*/
+
+ XUsbPs_EpHandlerFunc HandlerFunc;
+ /**< Handler function for this endpoint. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+ /* Each endpoint has an OUT and an IN component.
+ */
+ XUsbPs_EpOut Out; /**< OUT endpoint structure */
+ XUsbPs_EpIn In; /**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+ u8 bmRequestType; /**< bmRequestType in setup data */
+ u8 bRequest; /**< bRequest in setup data */
+ u16 wValue; /**< wValue in setup data */
+ u16 wIndex; /**< wIndex in setup data */
+ u16 wLength; /**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+ u32 Type;
+ /**< Endpoint type:
+ - XUSBPS_EP_TYPE_CONTROL
+ - XUSBPS_EP_TYPE_ISOCHRONOUS
+ - XUSBPS_EP_TYPE_BULK
+ - XUSBPS_EP_TYPE_INTERRUPT */
+
+ u32 NumBufs;
+ /**< Number of buffers to be handled by this endpoint. */
+ u32 BufSize;
+ /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+ u16 MaxPacketSize;
+ /**< Maximum packet size for this endpoint. This number will
+ * define the maximum number of bytes sent on the wire per
+ * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+ XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
+ XUsbPs_EpSetup In; /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+ u8 NumEndpoints; /**< Number of Endpoints for the controller.
+ This number depends on the runtime
+ configuration of driver. The driver may
+ configure fewer endpoints than are available
+ in the core. */
+
+ XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint configurations. */
+
+
+ u32 DMAMemPhys; /**< Physical base address of DMAable memory
+ allocated for the driver. */
+
+ /* The following members are used internally by the L0/L1 driver. They
+ * MUST NOT be accesses and/or modified in any way by the upper layers.
+ *
+ * The reason for having these members is that we generally try to
+ * avoid allocating memory in the L0/L1 driver as we want to be OS
+ * independent. In order to avoid allocating memory for this data
+ * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+ * structure which is allocated by the caller.
+ */
+ XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
+ /**< List of endpoint metadata structures. */
+
+ u32 PhysAligned; /**< 64 byte aligned base address of the DMA
+ memory block. Will be computed and set by
+ the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+ u16 DeviceID; /**< Unique ID of controller. */
+ u32 BaseAddress; /**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XUsbPs_Config Config; /**< Configuration structure */
+
+ int CurrentAltSetting; /**< Current alternative setting of interface */
+
+ void *UserDataPtr; /**< Data pointer to be used by upper layers to
+ store application dependent data structures.
+ The upper layers are responsible to allocated
+ and free the memory. The driver will not
+ mofidy this data pointer. */
+
+ /**
+ * The following structures hold the configuration for DEVICE mode
+ * of the controller. They are initialized using the
+ * XUsbPs_ConfigureDevice() function call.
+ */
+ XUsbPs_DeviceConfig DeviceConfig;
+ /**< Configuration for the DEVICE mode. */
+
+ XUsbPs_IntrHandlerFunc HandlerFunc;
+ /**< Handler function for the controller. */
+ void *HandlerRef;
+ /**< User data reference for the handler. */
+ u32 HandlerMask;
+ /**< User interrupt mask. Defines which interrupts will cause
+ * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @return The current frame number.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ *
+ * @note C-style signature:
+ * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note C-style signature:
+ * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) \
+{ \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK | \
+ XUSBPS_TIMER_RESET_MASK | \
+ XUSBPS_TIMER_REPEAT_MASK); \
+} \
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
+ XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_TIMER0_CTL_OFFSET) & \
+ XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
+ XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to enable.
+* @param Dir is direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to disable.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is number of the endpoint to stall.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the Number of the endpoint to unstall.
+* @param Dir is the Direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
+ ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+ ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to flush.
+* @param Dir is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @note C-style signature:
+* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
+ 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
+ XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note C-style signature:
+* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+* enabled.
+* @note C-style signature:
+* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+* disabled.
+*
+* @note
+* C-style signature:
+* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note C-style signature:
+* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param Threshold is the Interrupt threshold to be set.
+* Allowed values:
+* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* C-style signature:
+* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr) \
+ XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note C-style signature:
+* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr) \
+ XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
+ XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* - TRUE: The tripwire bit is still set.
+* - FALSE: The tripwire bit has been cleared.
+*
+* @note C-style signature:
+* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
+ (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XUSBPS_CMD_OFFSET) & \
+ XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits is the Bits to be set in the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param RegOffset is the register offset to be written.
+* @param Bits are the bits to be cleared in the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+ XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
+ XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+ const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b16d22b507e52a1edee897bf86bae92a5fcd775
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
@@ -0,0 +1,1454 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_endpoint.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * Endpoint specific function implementations.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names
+ * 2.1 kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
+ * code to XUsbPs_EpQueueRequest.
+ * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ * (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
+ * Caches After Buffer Receive in Endpoint Buffer Handler...)
+ *
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include /* for bzero() */
+#include
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+ const u8 *BufferPtr, u32 BufferLen);
+
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
+
+/* Functions to reconfigure endpoint upon host's set alternate interface
+ * request.
+ */
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+ int EpNum, unsigned short NewDirection);
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+ int EpNum, unsigned short NewDirection);
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
+
+/******************************* Functions ************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * This function configures the DEVICE side of the controller. The caller needs
+ * to pass in the desired configuration (e.g. number of endpoints) and a
+ * DMAable buffer that will hold the Queue Head List and the Transfer
+ * Descriptors. The required size for this buffer can be obtained by the caller
+ * using the: XUsbPs_DeviceMemRequired() macro.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param CfgPtr is a pointer to the configuration structure that contains
+ * the desired DEVICE side configuration.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ *
+ * @note
+ * The caller may configure the controller for both, DEVICE and
+ * HOST side.
+ *
+ ******************************************************************************/
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+ const XUsbPs_DeviceConfig *CfgPtr)
+{
+ int Status;
+ u32 ModeValue = 0x0;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Copy the configuration data over into the local instance structure */
+ InstancePtr->DeviceConfig = *CfgPtr;
+
+
+ /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
+ InstancePtr->DeviceConfig.PhysAligned =
+ (InstancePtr->DeviceConfig.DMAMemPhys +
+ XUSBPS_dQH_BASE_ALIGN) &
+ ~(XUSBPS_dQH_BASE_ALIGN -1);
+
+ /* Initialize the endpoint pointer list data structure. */
+ XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
+
+
+ /* Initialize the Queue Head structures in DMA memory. */
+ XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
+
+
+ /* Initialize the Transfer Descriptors in DMA memory.*/
+ Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+
+ /* Changing the DEVICE mode requires a controller RESET. */
+ if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
+ return XST_FAILURE;
+ }
+
+ /* Set the Queue Head List address. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPLISTADDR_OFFSET,
+ InstancePtr->DeviceConfig.PhysAligned);
+
+ /* Set the USB mode register to configure DEVICE mode.
+ *
+ * XUSBPS_MODE_SLOM_MASK note:
+ * Disable Setup Lockout. Setup Lockout is not required as we
+ * will be using the tripwire mechanism when handling setup
+ * packets.
+ */
+ ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
+
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_MODE_OFFSET, ModeValue);
+
+ XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
+ XUSBPS_OTGSC_OT_MASK);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occured.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+ BufferLen, FALSE);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also zero length packet if the
+* Bufferlen is in multiples of endpoint max packet size.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occured.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ u8 ReqZero = FALSE;
+ XUsbPs_EpSetup *Ep;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
+
+ if ((BufferLen >= Ep->MaxPacketSize) &&
+ (BufferLen % Ep->MaxPacketSize == 0)) {
+ ReqZero = TRUE;
+ }
+
+ return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+ BufferLen, ReqZero);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also sends ZLT packet if it is
+* requested.
+*
+* @param InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param BufferPtr is a pointer to the buffer to send.
+* @param BufferLen is the Buffer length.
+* @param ReqZero is the
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occured.
+* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+ const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
+{
+ int Status;
+ u32 Token;
+ XUsbPs_EpIn *Ep;
+ XUsbPs_dTD *DescPtr;
+ u32 Length;
+ u32 PipeEmpty = 1;
+ u32 Mask = 0x00010000;
+ u32 BitMask = Mask << EpNum;
+ u32 RegValue;
+ u32 Temp;
+ u32 exit = 1;
+
+
+ /* Locate the next available buffer in the ring. A buffer is available
+ * if its descriptor is not active.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
+
+ Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
+
+ if(Ep->dTDTail != Ep->dTDHead) {
+ PipeEmpty = 0;
+ }
+ XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+ /* Tell the caller if we do not have any descriptors available. */
+ if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+ return XST_USB_NO_DESC_AVAILABLE;
+ }
+
+ /* Remember the current head. */
+ DescPtr = Ep->dTDHead;
+
+ do {
+
+ /* Tell the caller if we do not have any descriptors available. */
+ if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+ return XST_USB_NO_DESC_AVAILABLE;
+ }
+
+ Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
+ /* Attach the provided buffer to the current descriptor.*/
+ Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+ BufferLen -= Length;
+ BufferPtr += Length;
+
+ XUsbPs_dTDSetActive(Ep->dTDHead);
+ if (BufferLen == 0 && (ReqZero == FALSE)) {
+ XUsbPs_dTDSetIOC(Ep->dTDHead);
+ exit = 0;
+ }
+ XUsbPs_dTDClrTerminate(Ep->dTDHead);
+ XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+ /* Advance the head descriptor pointer to the next descriptor. */
+ Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
+ /* Terminate the next descriptor and flush the cache.*/
+ XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+ if (ReqZero && BufferLen == 0) {
+ ReqZero = FALSE;
+ }
+
+ } while(BufferLen || exit);
+
+ XUsbPs_dTDSetTerminate(Ep->dTDHead);
+ XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+ if(!PipeEmpty) {
+ /* Read the endpoint prime register. */
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
+ if(RegValue & BitMask) {
+ return XST_SUCCESS;
+ }
+
+ do {
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ RegValue | XUSBPS_CMD_ATDTW_MASK);
+ Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
+ & BitMask;
+ } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
+ XUSBPS_CMD_ATDTW_MASK));
+
+ RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+ RegValue & ~XUSBPS_CMD_ATDTW_MASK);
+
+ if(Temp) {
+ return XST_SUCCESS;
+ }
+ }
+
+ /* Check, if the DMA engine is still running. If it is running, we do
+ * not clear Queue Head fields.
+ *
+ * Same cache rule as for the Transfer Descriptor applies for the Queue
+ * Head.
+ */
+ XUsbPs_dQHInvalidateCache(Ep->dQH);
+ /* Add the dTD to the dQH */
+ XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
+ Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
+ Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
+ XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
+
+ XUsbPs_dQHFlushCache(Ep->dQH);
+
+ Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function receives a data buffer from the endpoint of the given endpoint
+ * number.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param EpNum is the number of the endpoint to receive data from.
+ * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold
+ * the reference of the data buffer.
+ * @param BufferLenPtr (OUT param) is a pointer to the integer that will
+ * hold the buffer length.
+ * @param Handle is the opaque handle to be used when the buffer is
+ * released.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ * - XST_USB_NO_BUF: No buffer available.
+ *
+ * @note
+ * After handling the data in the buffer, the user MUST release
+ * the buffer using the Handle by calling the
+ * XUsbPs_EpBufferRelease() function.
+ *
+ ******************************************************************************/
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+ u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
+{
+ XUsbPs_EpOut *Ep;
+ XUsbPs_EpSetup *EpSetup;
+ u32 length = 0;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(BufferLenPtr != NULL);
+ Xil_AssertNonvoid(Handle != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ /* Locate the next available buffer in the ring. A buffer is available
+ * if its descriptor is not active.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+ if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+ return XST_USB_NO_BUF;
+ }
+
+ /* The buffer is not active which means that it has been processed by
+ * the DMA engine and contains valid data.
+ */
+ EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
+
+
+ /* Use the buffer pointer stored in the "user data" field of the
+ * Transfer Descriptor.
+ */
+ *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
+ XUSBPS_dTDUSERDATA);
+
+ length = EpSetup->BufSize -
+ XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
+
+ if(length > 0) {
+ *BufferLenPtr = length;
+ }else {
+ *BufferLenPtr = 0;
+ }
+
+ *Handle = (u32) Ep->dTDCurr;
+
+
+ /* Reset the descriptor's BufferPointer0 and Transfer Length fields to
+ * their original value. Note that we can not yet re-activate the
+ * descriptor as the caller will be using the attached buffer. Once the
+ * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
+ * can re-activate the descriptor.
+ */
+ XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
+ XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
+
+ XUsbPs_dTDFlushCache(Ep->dTDCurr);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function returns a previously received data buffer to the driver.
+*
+* @param Handle is a pointer to the buffer that is returned.
+*
+* @return None.
+*
+******************************************************************************/
+void XUsbPs_EpBufferRelease(u32 Handle)
+{
+ XUsbPs_dTD *dTDPtr;
+
+ /* Perform sanity check on Handle.*/
+ Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
+
+ /* Activate the descriptor and clear the Terminate bit. Make sure to do
+ * the proper cache handling.
+ */
+ dTDPtr = (XUsbPs_dTD *) Handle;
+
+ XUsbPs_dTDInvalidateCache(dTDPtr);
+
+ XUsbPs_dTDClrTerminate(dTDPtr);
+ XUsbPs_dTDSetActive(dTDPtr);
+ XUsbPs_dTDSetIOC(dTDPtr);
+
+ XUsbPs_dTDFlushCache(dTDPtr);
+
+}
+
+
+/*****************************************************************************/
+/**
+ * This function sets the handler for endpoint events.
+ *
+ * @param InstancePtr is a pointer to the XUsbPs instance of the
+ * controller.
+ * @param EpNum is the number of the endpoint to receive data from.
+ * @param Direction is the direction of the endpoint (bitfield):
+ * - XUSBPS_EP_DIRECTION_OUT
+ * - XUSBPS_EP_DIRECTION_IN
+ * @param CallBackFunc is the Handler callback function.
+ * Can be NULL if the user wants to disable the handler entry.
+ * @param CallBackRef is the user definable data pointer that will be
+ * passed back if the handler is called. May be NULL.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ * - XST_INVALID_PARAM: Invalid parameter passed.
+ *
+ * @note
+ * The user can disable a handler by setting the callback function
+ * pointer to NULL.
+ *
+ ******************************************************************************/
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+ XUsbPs_EpHandlerFunc CallBackFunc,
+ void *CallBackRef)
+{
+ XUsbPs_Endpoint *Ep;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CallBackFunc != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
+
+ if(Direction & XUSBPS_EP_DIRECTION_OUT) {
+ Ep->Out.HandlerFunc = CallBackFunc;
+ Ep->Out.HandlerRef = CallBackRef;
+ }
+
+ if(Direction & XUSBPS_EP_DIRECTION_IN) {
+ Ep->In.HandlerFunc = CallBackFunc;
+ Ep->In.HandlerRef = CallBackRef;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function primes an endpoint.
+*
+* @param InstancePtr is pointer to the XUsbPs instance.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param Direction is the direction of the endpoint (bitfield):
+* - XUSBPS_EP_DIRECTION_OUT
+* - XUSBPS_EP_DIRECTION_IN
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occured.
+* - XST_INVALID_PARAM: Invalid parameter passed.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
+{
+ u32 Mask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ /* Get the right bit mask for the endpoint direction. */
+ switch (Direction) {
+
+ case XUSBPS_EP_DIRECTION_OUT:
+ Mask = 0x00000001;
+ break;
+
+ case XUSBPS_EP_DIRECTION_IN:
+ Mask = 0x00010000;
+ break;
+
+ default:
+ return XST_INVALID_PARAM;
+ }
+
+ /* Write the endpoint prime register. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function extracts the Setup Data from a given endpoint.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpNum is the number of the endpoint to receive data from.
+* @param SetupDataPtr is a pointer to the setup data structure to be
+* filled.
+*
+* @return
+* - XST_SUCCESS: The operation completed successfully.
+* - XST_FAILURE: An error occured.
+*
+* @note None.
+******************************************************************************/
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+ XUsbPs_SetupData *SetupDataPtr)
+{
+ XUsbPs_EpOut *Ep;
+
+ u32 Data[2];
+ u8 *p;
+
+ int Timeout;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SetupDataPtr != NULL);
+ Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+ Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+
+ /* Get the data from the Queue Heads Setup buffer into local variables
+ * so we can extract the setup data values.
+ */
+ do {
+ /* Arm the tripwire. The tripwire will tell us if a new setup
+ * packet arrived (in which case the tripwire bit will be
+ * cleared) while we were reading the buffer. If a new setup
+ * packet arrived the buffer is corrupted and we continue
+ * reading.
+ */
+ XUsbPs_SetSetupTripwire(InstancePtr);
+
+ XUsbPs_dQHInvalidateCache(Ep->dQH);
+
+ Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
+ Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
+ } while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
+
+ /* Clear the pending endpoint setup stat bit.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
+
+ /* Clear the Tripwire bit and continue.
+ */
+ XUsbPs_ClrSetupTripwire(InstancePtr);
+
+
+ /* Data in the setup buffer is being converted by the core to big
+ * endian format. We have to take care of proper byte swapping when
+ * reading the setup data values.
+ *
+ * Need to check if there is a smarter way to do this and take the
+ * processor/memory-controller endianess into account?
+ */
+ p = (u8 *) Data;
+
+ SetupDataPtr->bmRequestType = p[0];
+ SetupDataPtr->bRequest = p[1];
+ SetupDataPtr->wValue = (p[3] << 8) | p[2];
+ SetupDataPtr->wIndex = (p[5] << 8) | p[4];
+ SetupDataPtr->wLength = (p[7] << 8) | p[6];
+
+ /* Before we leave we need to make sure that the endpoint setup bit has
+ * cleared. It needs to be 0 before the endpoint can be re-primed.
+ *
+ * Note: According to the documentation this endpoint setup bit should
+ * clear within 1-2us after it has been written above. This means that
+ * we should never catch it being 1 here. However, we still need to
+ * poll it to make sure. Just in case, we use a counter 'Timeout' so we
+ * won't hang here if the bit is stuck for some reason.
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET) &
+ (1 << EpNum)) && --Timeout) {
+ /* NOP */
+ }
+ if (0 == Timeout) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the endpoint pointer data structure.
+*
+* The function sets up the local data structure with the aligned addresses for
+* the Queue Head and Transfer Descriptors.
+*
+* @param DevCfgPtr is pointer to the XUsbPs DEVICE configuration
+* structure.
+*
+* @return none
+*
+* @note
+* Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
+* system. Therefore no memory is reserved for them.
+*
+******************************************************************************/
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+ u8 *p;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Set up the XUsbPs_Endpoint array. This array is used to define the
+ * location of the Queue Head list and the Transfer Descriptors in the
+ * block of DMA memory that has been passed into the driver.
+ *
+ * 'p' is used to set the pointers in the local data structure.
+ * Initially 'p' is pointed to the beginning of the DMAable memory
+ * block. As pointers are assigned, 'p' is incremented by the size of
+ * the respective object.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+ /* Start off with 'p' pointing to the (aligned) beginning of the DMA
+ * buffer.
+ */
+ p = (u8 *) DevCfgPtr->PhysAligned;
+
+
+ /* Initialize the Queue Head pointer list.
+ *
+ * Each endpoint has two Queue Heads. One for the OUT direction and one
+ * for the IN direction. An OUT Queue Head is always followed by an IN
+ * Queue Head.
+ *
+ * Queue Head alignment is XUSBPS_dQH_ALIGN.
+ *
+ * Note that we have to reserve space here for unused endpoints.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ /* OUT Queue Head */
+ Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
+ p += XUSBPS_dQH_ALIGN;
+
+ /* IN Queue Head */
+ Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
+ p += XUSBPS_dQH_ALIGN;
+ }
+
+
+ /* 'p' now points to the first address after the Queue Head list. The
+ * Transfer Descriptors start here.
+ *
+ * Each endpoint has a variable number of Transfer Descriptors
+ * depending on user configuration.
+ *
+ * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ /* OUT Descriptors.
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ Ep[EpNum].Out.dTDs = (XUsbPs_dTD *) p;
+ Ep[EpNum].Out.dTDCurr = (XUsbPs_dTD *) p;
+ p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
+ }
+
+ /* IN Descriptors.
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ Ep[EpNum].In.dTDs = (XUsbPs_dTD *) p;
+ Ep[EpNum].In.dTDHead = (XUsbPs_dTD *) p;
+ Ep[EpNum].In.dTDTail = (XUsbPs_dTD *) p;
+ p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
+ }
+ }
+
+
+ /* 'p' now points to the first address after the Transfer Descriptors.
+ * The data buffers for the OUT Transfer Desciptors start here.
+ *
+ * Note that IN (TX) Transfer Descriptors are not assigned buffers at
+ * this point. Buffers will be assigned when the user calls the send()
+ * function.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ /* If BufSize for this endpoint is set to 0 it means
+ * that we do not need to attach a buffer to this
+ * descriptor. We also initialize it's buffer pointer
+ * to NULL.
+ */
+ if (0 == EpCfg[EpNum].Out.BufSize) {
+ Ep[EpNum].Out.dTDBufs = NULL;
+ continue;
+ }
+
+ Ep[EpNum].Out.dTDBufs = p;
+ p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
+ }
+ }
+
+
+ /* Initialize the endpoint event handlers to NULL.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ Ep[EpNum].Out.HandlerFunc = NULL;
+ Ep[EpNum].In.HandlerFunc = NULL;
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the Queue Head List in memory.
+*
+* @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+* structure.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access. */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Go through the list of Queue Head entries and:
+ *
+ * - Set Transfer Descriptor addresses
+ * - Set Maximum Packet Size
+ * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+ * - Enable Interrupt On Setup (IOS)
+ *
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+ /* OUT Queue Heads.*/
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+ /* For isochronous, ep max packet size translates to different
+ * values in queue head than other types.
+ * Also enable ZLT for isochronous.
+ */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+ }
+
+ /* Only control OUT needs this */
+ if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+ }
+
+ /* Set up the overlay next dTD pointer. */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+ }
+
+
+ /* IN Queue Heads. */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+
+ /* Isochronous ep packet size can be larger than 1024.*/
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+ }
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+ }
+ }
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function initializes the Transfer Descriptors lists in memory.
+ *
+ * @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+ * structure.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+ int EpNum;
+
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access. */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Walk through the list of endpoints and initialize their Transfer
+ * Descriptors.
+ */
+ for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+ int Td;
+ int NumdTD;
+
+ XUsbPs_EpOut *Out = &Ep[EpNum].Out;
+ XUsbPs_EpIn *In = &Ep[EpNum].In;
+
+
+ /* OUT Descriptors
+ * ===============
+ *
+ * + Set the next link pointer
+ * + Set the interrupt complete and the active bit
+ * + Attach the buffer to the dTD
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+ NumdTD = EpCfg[EpNum].Out.NumBufs;
+ }
+ else {
+ NumdTD = 0;
+ }
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int Status;
+
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+ /* Set NEXT link pointer. */
+ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+ &Out->dTDs[NextTd]);
+
+ /* Set the OUT descriptor ACTIVE and enable the
+ * interrupt on complete.
+ */
+ XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+ XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+
+ /* Set up the data buffer with the descriptor. If the
+ * buffer pointer is NULL it means that we do not need
+ * to attach a buffer to this descriptor.
+ */
+ if (NULL == Out->dTDBufs) {
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ continue;
+ }
+
+ Status = XUsbPs_dTDAttachBuffer(
+ &Out->dTDs[Td],
+ Out->dTDBufs +
+ (Td * EpCfg[EpNum].Out.BufSize),
+ EpCfg[EpNum].Out.BufSize);
+ if (XST_SUCCESS != Status) {
+ return XST_FAILURE;
+ }
+
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ }
+
+
+ /* IN Descriptors
+ * ==============
+ *
+ * + Set the next link pointer
+ * + Set the Terminate bit to mark it available
+ */
+ if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+ NumdTD = EpCfg[EpNum].In.NumBufs;
+ }
+ else {
+ NumdTD = 0;
+ }
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+ /* Set NEXT link pointer. */
+ XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
+ In->dTDs[NextTd]);
+
+ /* Set the IN descriptor's TERMINATE bits. */
+ XUsbPs_dTDSetTerminate(In->dTDs[Td]);
+
+ XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function associates a buffer with a Transfer Descriptor. The function
+ * will take care of splitting the buffer into multiple 4kB aligned segments if
+ * the buffer happens to span one or more 4kB pages.
+ *
+ * @param dTDIndex is a pointer to the Transfer Descriptor
+ * @param BufferPtr is pointer to the buffer to link to the descriptor.
+ * @param BufferLen is the length of the buffer.
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ * - XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
+ * maximum allowed buffer size (16k).
+ *
+ * @note
+ * Cache invalidation and flushing needs to be handler by the
+ * caller of this function.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+ const u8 *BufferPtr, u32 BufferLen)
+{
+ u32 BufAddr;
+ u32 BufEnd;
+ u32 PtrNum;
+
+ Xil_AssertNonvoid(dTDPtr != NULL);
+
+ /* Check if the buffer is smaller than 16kB. */
+ if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
+ return XST_USB_BUF_TOO_BIG;
+ }
+
+ /* Get a u32 of the buffer pointer to avoid casting in the following
+ * logic operations.
+ */
+ BufAddr = (u32) BufferPtr;
+
+
+ /* Set the buffer pointer 0. Buffer pointer 0 can point to any location
+ * in memory. It does not need to be 4kB aligned. However, if the
+ * provided buffer spans one or more 4kB boundaries, we need to set up
+ * the subsequent buffer pointers which must be 4kB aligned.
+ */
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
+
+ /* Check if the buffer spans a 4kB boundary.
+ *
+ * Only do this check, if we are not sending a 0-length buffer.
+ */
+ if (BufferLen > 0) {
+ BufEnd = BufAddr + BufferLen -1;
+ PtrNum = 1;
+
+ while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
+ /* The buffer spans at least one boundary, let's set
+ * the next buffer pointer and repeat the procedure
+ * until the end of the buffer and the pointer written
+ * are in the same 4kB page.
+ */
+ BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
+ BufAddr);
+ PtrNum++;
+ }
+ }
+
+ /* Set the length of the buffer. */
+ XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
+
+
+ /* We remember the buffer pointer in the user data field (reserved
+ * field in the dTD). This makes it easier to reset the buffer pointer
+ * after a buffer has been received on the endpoint. The buffer pointer
+ * needs to be reset because the DMA engine modifies the buffer pointer
+ * while receiving.
+ */
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function set the Max PacketLen for the queue head for isochronous EP.
+ *
+ * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
+ * Mult bits are set to reflect that.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the Length to be set.
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
+{
+ u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
+ u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
+
+ if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
+ return;
+ }
+
+ if (Mult > 3) {
+ return;
+ }
+
+ /* Set Max packet size */
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+ ~XUSBPS_dQHCFG_MPL_MASK) |
+ (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
+
+ /* Set Mult to tell hardware how many transactions in each microframe */
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+ ~XUSBPS_dQHCFG_MULT_MASK) |
+ (Mult << XUSBPS_dQHCFG_MULT_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+* This function reconfigures one Ep corresponding to host's request of setting
+* alternate interface. The endpoint has been disabled before this call.
+*
+* Both QH and dTDs are updated for the new configuration.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param CfgPtr
+* Pointer to the updated XUsbPs DEVICE configuration structure.
+*
+* @param EpNum
+* The endpoint to be reconfigured.
+*
+* @param NewDirection
+* The new transfer direction the endpoint.
+*
+* @param DirectionChanged
+* A boolean value indicate whether the transfer direction has changed.
+*
+* @return
+* XST_SUCCESS upon success, XST_FAILURE otherwise.
+*
+******************************************************************************/
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+ int EpNum, unsigned short NewDirection,
+ int DirectionChanged) {
+
+ int Status = XST_SUCCESS;
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ Ep = CfgPtr->Ep;
+ EpCfg = CfgPtr->EpCfg;
+
+ /* If transfer direction changes, dTDs has to be reset
+ * Number of buffers are preset and should not to be changed.
+ */
+ if(DirectionChanged) {
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ u8 *p;
+
+ /* Swap the pointer to the dTDs.
+ */
+ Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
+ p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
+
+ /* Set the OUT buffer if buffer size is not zero
+ */
+ if(EpCfg[EpNum].Out.BufSize > 0) {
+ Ep[EpNum].Out.dTDBufs = p;
+ }
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
+ }
+ }
+
+ /* Reset dTD progress tracking pointers
+ */
+ if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
+ }
+
+ /* Reinitialize information in QH
+ */
+ XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
+
+ /* Reinitialize the dTD linked list, and flush the cache
+ */
+ Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
+ if(Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function re-initializes the Queue Head List in memory.
+ * The endpoint 1 has been disabled before this call.
+ *
+ * @param DevCfgPtr
+ * Pointer to the updated XUsbPs DEVICE configuration structure.
+ *
+ * @param EpNum
+ * The endpoint to be reconfigured.
+ *
+ * @param NewDirection
+ * The new transfer direction of endpoint 1
+ *
+ * @return none
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+
+ /* Setup pointers for simpler access.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ /* Go through the list of Queue Head entries and:
+ *
+ * - Set Transfer Descriptor addresses
+ * - Set Maximum Packet Size
+ * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+ * - Enable Interrupt On Setup (IOS)
+ *
+ */
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ /* OUT Queue Heads.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+ /* For isochronous, ep max packet size translates to different
+ * values in queue head than other types.
+ * Also enable ZLT for isochronous.
+ */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+ EpCfg[EpNum].Out.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+ }
+
+ XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+
+ /* Set up the overlay next dTD pointer.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+ XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+
+ /* IN Queue Heads.
+ */
+ XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+ XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+ /* Isochronous ep packet size can be larger than 1024. */
+ if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+ XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+ }else {
+ XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+ EpCfg[EpNum].In.MaxPacketSize);
+ XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+ }
+
+ XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
+
+ XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+ }
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function re-initializes the Transfer Descriptors lists in memory.
+ * The endpoint has been disabled before the call. The transfer descriptors
+ * list pointer has been initialized too.
+ *
+ * @param DevCfgPtr
+ * Pointer to the XUsbPs DEVICE configuration structure.
+ *
+ * @param EpNum
+ * The endpoint to be reconfigured.
+ *
+ * @param NewDirection
+ * The new transfer direction of endpoint 1
+ *
+ * @return
+ * - XST_SUCCESS: The operation completed successfully.
+ * - XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+ XUsbPs_Endpoint *Ep;
+ XUsbPs_EpConfig *EpCfg;
+ int Td;
+ int NumdTD;
+
+
+ /* Setup pointers for simpler access.
+ */
+ Ep = DevCfgPtr->Ep;
+ EpCfg = DevCfgPtr->EpCfg;
+
+
+ if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+ XUsbPs_EpOut *Out = &Ep[EpNum].Out;
+
+ /* OUT Descriptors
+ * ===============
+ *
+ * + Set the next link pointer
+ * + Set the interrupt complete and the active bit
+ * + Attach the buffer to the dTD
+ */
+ NumdTD = EpCfg[EpNum].Out.NumBufs;
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int Status;
+
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+ /* Set NEXT link pointer.
+ */
+ XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+ &Out->dTDs[NextTd]);
+
+ /* Set the OUT descriptor ACTIVE and enable the
+ * interrupt on complete.
+ */
+ XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+ XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+ /* Set up the data buffer with the descriptor. If the
+ * buffer pointer is NULL it means that we do not need
+ * to attach a buffer to this descriptor.
+ */
+ if (Out->dTDBufs != NULL) {
+
+ Status = XUsbPs_dTDAttachBuffer(
+ &Out->dTDs[Td],
+ Out->dTDBufs +
+ (Td * EpCfg[EpNum].Out.BufSize),
+ EpCfg[EpNum].Out.BufSize);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+ XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+ }
+ } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+ XUsbPs_EpIn *In = &Ep[EpNum].In;
+
+ /* IN Descriptors
+ * ==============
+ *
+ * + Set the next link pointer
+ * + Set the Terminate bit to mark it available
+ */
+ NumdTD = EpCfg[EpNum].In.NumBufs;
+
+ for (Td = 0; Td < NumdTD; ++Td) {
+ int NextTd = (Td + 1) % NumdTD;
+
+ XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+ /* Set NEXT link pointer.
+ */
+ XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
+ &In->dTDs[NextTd]);
+
+ /* Set the IN descriptor's TERMINATE bits.
+ */
+ XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
+
+ XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..1cb0cfcd3e755d485abb3837c546125ee65b4418
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDNLP_T_MASK 0x00000001
+ /**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
+ /**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ * @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * XUsbPs_dQHInvalidateCache()
+ * XUsbPs_dQHFlushCache()
+ * XUsbPs_dTDInvalidateCache()
+ * XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+ Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+ Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+ Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Len is the length to be set. Range: 0..16384
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr) \
+ (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+ & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param NLP is the Next Link Pointer
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_ADDR_MASK) | \
+ ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return TransferLength field of the descriptor.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr) \
+ (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
+ & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
+ XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
+ ~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * - TRUE: The buffer is active.
+ * - FALSE: The buffer is not active.
+ *
+ * @note C-style signature:
+ * int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr) \
+ ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr) \
+ XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
+ XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
+ XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is a pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param dTDPtr is pointer to the dTD element.
+ * @param Id is the field ID inside the dTD element to read.
+ * @param Val is the value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
+ (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ * Software must ensure that no interface data structure reachable by the
+ * Device Controller spans a 4K-page boundary. The first element of the
+ * Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
+ overlay */
+#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ * @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
+ /**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
+ /**< USB dQH Maximum Packet Length
+ * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT 16
+#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
+ /**< USB dQH Zero Length Termination
+ * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
+ /* USB dQH Number of Transactions Field
+ * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT 30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Len is the length to be set.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
+ ~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ *
+ * @note C-style signature:
+ * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr) \
+ XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
+ XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
+ XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param dQHPtr is a pointer to the dQH element.
+ * @param Id is the Field ID inside the dQH element to read.
+ * @param Val is the Value to write to the field.
+ *
+ * @note C-style signature:
+ * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
+ (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..9f20ba86880015af00d9c8b964608f82503c14a7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_USB_0_DEVICE_ID,
+ XPAR_PS7_USB_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..04963b28874195ffb6fcba1c6fd8885059edcec5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs interface reset functionality
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.05a kpc 10/10/10 first version
+ *
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+
+/************************** Constant Definitions ****************************/
+#define XUSBPS_RESET_TIMEOUT 0xFFFFF
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given usbps interface by
+* configuring the appropriate control bits in the usbps specifc registers.
+* the usbps reset sequence involves the below steps
+* Disbale the interrupts
+* Clear the status registers
+* Apply the reset command and wait for reset complete status
+* Update the relevant control registers with reset values
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XUsbPs_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+ u32 Timeout = 0;
+
+ /* Host and device mode */
+ /* Disable the interrupts */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
+ /* Clear the interuupt status */
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
+
+ /* Perform the reset operation using USB CMD register */
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ RegVal = RegVal | XUSBPS_CMD_RST_MASK;
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ /* Wait till the reset operation returns success */
+ /*
+ * FIX ME: right now no indication to the caller or user about
+ * timeout overflow
+ */
+ while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
+ {
+ RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+ Timeout++;
+ }
+ /* Update periodic list base address register with reset value */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);
+ /* Update async/endpoint list base address register with reset value */
+ XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);
+
+}
+
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..69f3ebffb4fef5b1f9ff7ad459509df87b94882c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ * 1.04a nm 10/23/12 Fixed CR# 679106.
+ * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
+ *
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING 4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK 0x80000000
+#define XUSBPS_TIMER_STOP_MASK 0x80000000
+#define XUSBPS_TIMER_RESET_MASK 0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
+
+#define XUSBPS_EP_NUM_MASK 0x3E
+#define XUSBPS_EP_NUM_SHIFT 1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n) \
+ (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
+ * this core. */
+#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
+ * registers */
+#define XUSBPS_EPCRn_OFFSET(n) \
+ (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define XUSBPS_EPFLUSH_RX_SHIFT 0
+#define XUSBPS_EPFLUSH_TX_SHIFT 16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ * @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
+#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ * @{
+ */
+#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ * @{
+ */
+#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
+ * Read Only */
+#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
+#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
+ * Read Only */
+#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
+ XUSBPS_IXR_UE_MASK | \
+ XUSBPS_IXR_PC_MASK | \
+ XUSBPS_IXR_FRE_MASK | \
+ XUSBPS_IXR_AA_MASK | \
+ XUSBPS_IXR_UR_MASK | \
+ XUSBPS_IXR_SR_MASK | \
+ XUSBPS_IXR_SLE_MASK | \
+ XUSBPS_IXR_ULPI_MASK | \
+ XUSBPS_IXR_HCH_MASK | \
+ XUSBPS_IXR_RCL_MASK | \
+ XUSBPS_IXR_PS_MASK | \
+ XUSBPS_IXR_AS_MASK | \
+ XUSBPS_IXR_NAK_MASK | \
+ XUSBPS_IXR_UA_MASK | \
+ XUSBPS_IXR_UP_MASK | \
+ XUSBPS_IXR_TI0_MASK | \
+ XUSBPS_IXR_TI1_MASK)
+ /**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ * @{
+ */
+#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
+#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK 0x00000010
+#define XUSBPS_MODE_VALID_MASK 0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ * @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
+ /**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
+ /**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
+ /**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX 127
+ /**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ * @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ * @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ * @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
+ /**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
+ /**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
+ /**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ * @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ * @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+ * Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+ * Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ * @{
+ */
+#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
+ * Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
+ * Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
+ * Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
+ * B Disconnect to A
+ * Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
+ * Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
+ * Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
+ XUSBPS_OTGSC_AVVIS_MASK | \
+ XUSBPS_OTGSC_ASVIS_MASK | \
+ XUSBPS_OTGSC_BSVIS_MASK | \
+ XUSBPS_OTGSC_BSEIS_MASK | \
+ XUSBPS_OTGSC_1MSS_MASK | \
+ XUSBPS_OTGSC_DPIS_MASK)
+ /** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
+ XUSBPS_OTGSC_AVVIE_MASK | \
+ XUSBPS_OTGSC_ASVIE_MASK | \
+ XUSBPS_OTGSC_BSVIE_MASK | \
+ XUSBPS_OTGSC_BSEE_IEB_MASK | \
+ XUSBPS_OTGSC_1MSE_MASK | \
+ XUSBPS_OTGSC_DPIE_MASK)
+ /** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN 2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN 64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN 32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE 4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN 4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddress is the base address for the USB registers.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register.
+*
+* @note C-style signature:
+* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param BaseAddress is the the base address for the USB registers.
+* @param RegOffset is the register offset to be written.
+* @param Data is the the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..83463bdfeb840a618b197a5ba7cb2ba06658cd9b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
@@ -0,0 +1,472 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_intr.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This file contains the functions that are related to interrupt processing
+ * for the EPB USB driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a jz 10/10/10 First release
+ * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ * handling.
+ * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ * (moving of dTD Head/Tail Pointers properly).
+ *
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+* This function is the first-level interrupt handler for the USB core. All USB
+* interrupts will be handled here. Depending on the type of the interrupt,
+* second level interrupt handler may be called. Second level interrupt
+* handlers will be registered by the user using the:
+* XUsbPs_IntrSetHandler()
+* and/or
+* XUsbPs_EpSetHandler()
+* functions.
+*
+*
+* @param HandlerRef is a Reference passed to the interrupt register
+* function. In our case this will be a pointer to the XUsbPs
+* instance.
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void XUsbPs_IntrHandler(void *HandlerRef)
+{
+ XUsbPs *InstancePtr;
+
+ u32 IrqSts;
+
+ Xil_AssertVoid(HandlerRef != NULL);
+
+ InstancePtr = (XUsbPs *) HandlerRef;
+
+ /* Handle controller (non-endpoint) related interrupts. */
+ IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_ISR_OFFSET);
+
+ /* Clear the interrupt status register. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_ISR_OFFSET, IrqSts);
+
+ /* Nak interrupt, used to respond to host's IN request */
+ if(IrqSts & XUSBPS_IXR_NAK_MASK) {
+ /* Ack the hardware */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPNAKISR_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPNAKISR_OFFSET));
+ }
+
+
+ /***************************************************************
+ *
+ * Handle general interrupts. Endpoint interrupts will be handler
+ * later.
+ *
+ */
+
+ /* RESET interrupt.*/
+ if (IrqSts & XUSBPS_IXR_UR_MASK) {
+ XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
+ return;
+ }
+
+ /* Check if we have a user handler that needs to be called. Note that
+ * this is the handler for general interrupts. Endpoint interrupts will
+ * be handled below.
+ */
+ if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+ }
+
+
+ /***************************************************************
+ *
+ * Handle Endpoint interrupts.
+ *
+ */
+ if (IrqSts & XUSBPS_IXR_UI_MASK) {
+ u32 EpStat;
+ u32 EpCompl;
+
+ /* ENDPOINT 0 SETUP PACKET HANDLING
+ *
+ * Check if we got a setup packet on endpoint 0. Currently we
+ * only check for setup packets on endpoint 0 as we would not
+ * expect setup packets on any other endpoint (even though it
+ * is possible to send setup packets on other endpoints).
+ */
+ EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET);
+ if (EpStat & 0x0001) {
+ /* Handle the setup packet */
+ XUsbPs_IntrHandleEp0Setup(InstancePtr);
+
+ /* Re-Prime the endpoint.
+ * Endpoint is de-primed if a setup packet comes in.
+ */
+ XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
+ }
+
+ /* Check for RX and TX complete interrupts. */
+ EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET);
+
+
+ /* ACK the complete interrupts. */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET, EpCompl);
+
+ /* Check OUT (RX) endpoints. */
+ if (EpCompl & XUSBPS_EP_OUT_MASK) {
+ XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
+ }
+
+ /* Check IN (TX) endpoints. */
+ if (EpCompl & XUSBPS_EP_IN_MASK) {
+ XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
+ }
+ }
+}
+
+
+/*****************************************************************************/
+/**
+* This function registers the user callback handler for controller
+* (non-endpoint) interrupts.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param CallBackFunc is the Callback function to register.
+* CallBackFunc may be NULL to clear the entry.
+* @param CallBackRef is the user data reference passed to the
+* callback function. CallBackRef may be NULL.
+* @param Mask is the User interrupt mask. Defines which interrupts
+* will cause the callback to be called.
+*
+* @return
+* - XST_SUCCESS: Callback registered successfully.
+* - XST_FAILURE: Callback could not be registered.
+*
+* @note None.
+*
+******************************************************************************/
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+ XUsbPs_IntrHandlerFunc CallBackFunc,
+ void *CallBackRef, u32 Mask)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ InstancePtr->HandlerFunc = CallBackFunc;
+ InstancePtr->HandlerRef = CallBackRef;
+ InstancePtr->HandlerMask = Mask;
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles TX buffer interrupts. It is called by the interrupt
+* when a transmit complete interrupt occurs. It returns buffers of completed
+* descriptors to the caller.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+* @param EpCompl is the Bit mask of endpoints that caused a transmit
+* complete interrupt.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+ int Index;
+ u32 Mask;
+ int NumEp;
+
+ /* Check all endpoints for TX complete bits.
+ */
+ Mask = 0x00010000;
+ NumEp = InstancePtr->DeviceConfig.NumEndpoints;
+
+ /* Check for every endpoint if its TX complete bit is
+ * set.
+ */
+ for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+ XUsbPs_EpIn *Ep;
+
+ if (!(EpCompl & Mask)) {
+ continue;
+ }
+ /* The TX complete bit for this endpoint is
+ * set. Walk the list of descriptors to see
+ * which ones are completed.
+ */
+ Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
+ do {
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDTail);
+
+ /* If the descriptor is not active then the buffer has
+ * not been sent yet.
+ */
+ if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
+ break;
+ }
+
+ if (Ep->HandlerFunc) {
+ void *BufPtr;
+
+ BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
+ XUSBPS_dTDUSERDATA);
+
+ Ep->HandlerFunc(Ep->HandlerRef, Index,
+ XUSBPS_EP_EVENT_DATA_TX,
+ BufPtr);
+ }
+
+ Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
+ } while(Ep->dTDTail != Ep->dTDHead);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+ * This function handles RX buffer interrupts. It is called by the interrupt
+ * when a receive complete interrupt occurs. It notifies the callback functions
+ * that have been registered with the individual endpoints that data has been
+ * received.
+ *
+ * @param InstancePtr
+ * Pointer to the XUsbPs instance of the controller.
+ *
+ * @param EpCompl
+ * Bit mask of endpoints that caused a receive complete interrupt.
+ * @return
+ * none
+ *
+ ******************************************************************************/
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+ XUsbPs_EpOut *Ep;
+ int Index;
+ u32 Mask;
+ int NumEp;
+
+ /* Check all endpoints for RX complete bits. */
+ Mask = 0x00000001;
+ NumEp = InstancePtr->DeviceConfig.NumEndpoints;
+
+
+ /* Check for every endpoint if its RX complete bit is set.*/
+ for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+ int numP = 0;
+
+ if (!(EpCompl & Mask)) {
+ continue;
+ }
+ Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
+
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+ /* Handle all finished dTDs */
+ while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+ numP += 1;
+ if (Ep->HandlerFunc) {
+ Ep->HandlerFunc(Ep->HandlerRef, Index,
+ XUSBPS_EP_EVENT_DATA_RX, NULL);
+ }
+
+ Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
+ XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+ }
+ /* Re-Prime the endpoint.*/
+ XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a RESET interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param InstancePtr is pointer to the XUsbPs instance of the controller
+* @param IrqSts is the Interrupt status register content.
+* To be passed on to the user.
+*
+* @return None
+*
+* @Note None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
+{
+ int Timeout;
+
+ /* Clear all setup token semaphores by reading the
+ * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+ * itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPSTAT_OFFSET));
+
+ /* Clear all the endpoint complete status bits by reading the
+ * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+ * to itself.
+ */
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET,
+ XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPCOMPL_OFFSET));
+
+ /* Cancel all endpoint prime status by waiting until all bits
+ * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+ * to XUSBPS_EPFLUSH_OFFSET.
+ *
+ * Avoid hanging here by using a Timeout counter...
+ */
+ Timeout = XUSBPS_TIMEOUT_COUNTER;
+ while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPPRIME_OFFSET) &
+ XUSBPS_EP_ALL_MASK) && --Timeout) {
+ /* NOP */
+ }
+ XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+ /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
+ * still set at this point. If the code gets to this point and
+ * the reset bit has already been cleared we are in trouble and
+ * hardware reset is necessary.
+ */
+ if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUSBPS_PORTSCR1_OFFSET) &
+ XUSBPS_PORTSCR_PR_MASK)) {
+ /* Send a notification to the user that a hardware
+ * RESET is required. At this point we can only hope
+ * that the user registered an interrupt handler and
+ * will issue a hardware RESET.
+ */
+ if (InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
+ IrqSts);
+ }
+ else {
+ for (;;);
+ }
+
+ /* If we get here there is nothing more to do. The user
+ * should have reset the core.
+ */
+ return;
+ }
+
+ /* Check if we have a user handler that needs to be called.
+ */
+ if (InstancePtr->HandlerFunc) {
+ (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+ }
+
+ /* We are done. After RESET we don't proceed in the interrupt
+ * handler.
+ */
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a Setup Packet interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param InstancePtr is a pointer to the XUsbPs instance of the
+* controller.
+*
+* @return None
+*
+* @Note None
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
+{
+
+ XUsbPs_EpOut *Ep;
+
+ /* Notifiy the user. */
+ Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
+
+ if (Ep->HandlerFunc) {
+ Ep->HandlerFunc(Ep->HandlerRef, 0,
+ XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
+ }
+}
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..a2070a76e69b73bcb9e553f4f2b4ce1e8e51817d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_sinit.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs driver's static initialzation
+ * functionality.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr 10/10/10 First release
+ *
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XUsbPs_Config XUsbPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param DeviceID is the ID of the controller to look up the
+* configuration for.
+*
+* @return
+* A pointer to the configuration found or NULL if the specified
+* controller ID was not found.
+*
+******************************************************************************/
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
+{
+ XUsbPs_Config *CfgPtr = NULL;
+
+ int Index;
+
+ for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
+ if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
+ CfgPtr = &XUsbPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
new file mode 100644
index 0000000000000000000000000000000000000000..92a86560bfe169b7172c2be80b5512f777f7f0a9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
@@ -0,0 +1,1831 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* to fix CR #693371
+* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
+* CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address
+* (CR#854437).
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ConfigPtr points to the XAdcPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return
+* - XST_SUCCESS if successful.
+*
+* @note The user needs to first call the XAdcPs_LookupConfig() API
+* which returns the Configuration structure pointer which is
+* passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+
+ u32 RegValue;
+ /*
+ * Assert the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+ /*
+ * Set the values read from the device config and the base address.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+ /* Write Unlock value to Device Config Unlock register */
+ XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+ XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+ /* Enable the PS access of xadc and set FIFO thresholds */
+
+ RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+
+ RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+ XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, RegValue);
+
+ /* Release xadc from reset */
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+
+ /*
+ * Indicate the instance is now ready to use and
+ * initialized without error.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Config Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Miscellaneous
+* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+* in xadcps_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Status Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the Miscellaneous control register Register.
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous control register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param InstancePtr is a pointer to the Xxadc instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Generate the reset by Control
+ * register and release from reset
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x10);
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number. Use the XADCPS_CH_* defined in
+* the file xadcps.h.
+* The valid channels are
+* - 0 to 6
+* - 13 to 31
+*
+* @return A 16-bit value representing the ADC converted data for the
+* specified channel. The XADC Monitor/ADC device guarantees
+* a 10 bit resolution for the ADC converted data and data is the
+* 10 MSB bits of the 16 data read from the device.
+*
+* @note The channels 7,8,9 are used for calibration of the device and
+* hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_TEMP_OFFSET +
+ Channel));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param CoeffType specifies the calibration coefficient
+* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+* specify the calibration coefficient to be read.
+*
+* @return A 16-bit value representing the calibration coefficient.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+ /*
+ * Read the selected calibration coefficient.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+ CoeffType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MeasurementType specifies the parameter for which the
+* Minimum/Maximum measurement has to be read.
+* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+* specify the data to be read.
+*
+* @return A 16-bit value representing the maximum/minimum measurement for
+* specified parameter.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+ ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+ (MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+ /*
+ * Read and return the specified Minimum/Maximum measurement.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_MAX_TEMP_OFFSET +
+ MeasurementType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Average is the number of samples of averaging programmed to the
+* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+* in xadcps.h file :
+* - XADCPS_AVG_0_SAMPLES for no averaging
+* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+ /*
+ * Write the averaging value into the Configuration Register 0.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_AVG_VALID_MASK);
+
+ RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The averaging read from the Configuration Register 0 is
+* returned. Use the XADCPS_AVG_* bit definitions defined in
+* xadcps.h file to interpret the returned value :
+* - XADCPS_AVG_0_SAMPLES means no averaging
+* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+ u32 Average;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging value from the Configuration Register 0.
+ */
+ Average = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+ return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number for the singel channel mode.
+* The valid channels are 0 to 6, 8, and 13 to 31.
+* If the external Mux is used then this specifies the channel
+* oonnected to the external Mux. Please read the Device Spec
+* to know which channels are valid.
+* @param IncreaseAcqCycles is a boolean parameter which specifies whether
+* the Acquisition time for the external channels has to be
+* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+* default 4 ADCCLK cycles (specify FALSE). This parameter is
+* only valid for the external channels.
+* @param IsDifferentialMode is a boolean parameter which specifies
+* unipolar(specify FALSE) or differential mode (specify TRUE) for
+* the analog inputs. The input mode is only valid for the
+* external channels.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Configuration Register 0.
+* - XST_FAILURE if the channel sequencer is enabled or the input
+* parameters are not valid for the selected channel.
+*
+* @note
+* - The number of samples for the averaging for all the channels
+* is set by using the function XAdcPs_SetAvg.
+* - The calibration of the device is done by doing a ADC
+* conversion on the calibration channel(channel 8). The input
+* parameters IncreaseAcqCycles, IsDifferentialMode and
+* IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ (Channel == XADCPS_CH_ADC_CALIB) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+ Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+ (IncreaseAcqCycles == FALSE));
+ Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+ Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+ (IsDifferentialMode == FALSE));
+
+ /*
+ * Check if the device is in single channel mode else return failure
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SINGCHAN)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_AVG_VALID_MASK;
+
+ /*
+ * Select the number of acquisition cycles. The acquisition cycles is
+ * only valid for the external channels.
+ */
+ if (IncreaseAcqCycles == TRUE) {
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_ACQ_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+
+ }
+
+ /*
+ * Select the input mode. The input mode is only valid for the
+ * external channels.
+ */
+ if (IsDifferentialMode == TRUE) {
+
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_DU_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Select the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ }
+
+ /*
+ * Write the given values into the Configuration Register 0.
+ */
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+* in the Configuration Register 1.
+* Bit positions of 1 will be enabled. Bit positions of 0 will be
+* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that the alarms for bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The alarm outputs specified by the AlmEnableMask are negated
+* before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+ RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+ RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+ /*
+ * Enable/disables the alarm enables for the specified alarm bits in the
+ * Configuration Register 1.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return This is the bit-mask of the enabled alarm outputs in the
+* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+* returned value.
+* Bit positions of 1 indicate that the alarm output is enabled.
+* Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that alarms for the bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The enabled alarm outputs returned by this function is the
+* negated value of the the data read from the Configuration
+* Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the status of alarm output enables from the Configuration
+ * Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+ return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+* offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Calibration is the Calibration to be applied.
+* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+* Multiple calibrations can be enabled at a time by oring the
+* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+* Calibration can be disabled by specifying
+ XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+ (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+ (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+ /*
+ * Set the specified calibration in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+
+ RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+ RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The value of the calibration enables in the Configuration
+* Register 1 :
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+* correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the calibration enables from the Configuration Register 1.
+ */
+ return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
+* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param SequencerMode is the sequencer mode to be set.
+* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return None.
+*
+* @note Only one of the modes can be enabled at a time. Please
+* read the Spec of the XADC for further information about the
+* sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+ (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+ /*
+ * Set the specified sequencer mode in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+ RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+ RegValue |= ((SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
+ XADCPS_CFR1_SEQ_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The channel sequencer mode :
+* - XADCPS_SEQ_MODE_SAFE : Default safe mode
+* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel sequencer mode from the Configuration Register 1.
+ */
+ return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+ XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
+* Valid values of the divisor are
+* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+* Refer to the device specification for more details
+*
+* @return None.
+*
+* @note - The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+* - There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write the divisor value into the Configuration Register #2.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The divisor read from the Configuration Register 2.
+*
+* @note The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+ u16 Divisor;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the divisor value from the Configuration Register 2.
+ */
+ Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET);
+
+ return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ChEnableMask is the bit mask of all the channels to be enabled.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+* be disabled.
+* The ChEnableMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Selection Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable the specified channels in the ADC Channel Selection Sequencer
+ * Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET,
+ (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET,
+ (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ01_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+* are the channels that are enabled and bit mask of 0 are
+* the channels that are disabled.
+*
+* @return None
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValEnable;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel enable bits for all the channels from the ADC
+ * Channel Selection Register.
+ */
+ RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET) &
+ XADCPS_SEQ00_CH_VALID_MASK;
+ RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET) &
+ XADCPS_SEQ01_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+ return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AvgEnableChMask is the bit mask of all the channels for which
+* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to specify the Channel numbers. Averaging will be
+* enabled for bit masks of 1 and disabled for bit mask of 0.
+* The AvgEnableChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Averaging Enables Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable/disable the averaging for the specified channels in the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET,
+ (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET,
+ (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ03_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The status of averaging (enabled/disabled) for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* averaging is enabled and bit mask of 0 are the channels for
+* averaging is disabled
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValAvg;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging enable status for all the channels from the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+ RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param InputModeChMask is the bit mask of all the channels for which
+* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+* in xadcps_hw.h to specify the channel numbers. Differential
+* input mode will be set for bit masks of 1 and unipolar input
+* mode for bit masks of 0.
+* The InputModeChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the input mode for the specified channels in the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET,
+ (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET,
+ (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ05_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The input mode for all the channels.
+* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* input mode is differential and bit mask of 0 are the channels
+* for which input mode is unipolar.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+ u32 InputMode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the input mode for all the channels from the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET) &
+ XADCPS_SEQ04_CH_VALID_MASK;
+ InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET) &
+ XADCPS_SEQ05_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AcqCyclesChMask is the bit mask of all the channels for which
+* the number of acquisition cycles is to be extended.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+* for bit masks of 1 and will be the default 4 ADCCLK cycles for
+* bit masks of 0.
+* The AcqCyclesChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Channel Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the Acquisition time for the specified channels in the
+ * ADC Channel Acquisition Time Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET,
+ (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET,
+ (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ07_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The acquisition time for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* acquisition cycles are extended and bit mask of 0 are the
+* channels for which acquisition cycles are not extended.
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+ u32 RegValAcq;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the Acquisition cycles for the specified channels from the ADC
+ * Channel Acquisition Time Sequencer Registers.
+ */
+ RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET) &
+ XADCPS_SEQ06_CH_VALID_MASK;
+ RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET) &
+ XADCPS_SEQ07_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register to
+* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+* specify the index.
+* @param Value is the 16-bit threshold value to write into the register.
+*
+* @return None.
+*
+* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+* threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Write the value into the specified Alarm Threshold Register.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+ AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register
+* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
+* to specify the index.
+*
+* @return A 16-bit value representing the contents of the selected Alarm
+* Threshold Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Read the specified Alarm Threshold Register and return
+ * the value
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+ return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ /*
+ * Preserve the powerdown value and write OT enable value the into the
+ * OT Upper Alarm Threshold Register.
+ */
+ OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT Upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param IsEventMode is a boolean parameter that specifies continuous
+* sampling (specify FALSE) or event driven sampling mode (specify
+* TRUE) for the given channel.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_EC_MASK);
+
+ /*
+ * Set the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ } else {
+ RegValue &= ~XADCPS_CFR0_EC_MASK;
+ }
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The sampling mode
+* - 0 specifies continuous sampling
+* - 1 specifies event driven sampling mode
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+ u32 Mode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the sampling mode from the Configuration Register 0.
+ */
+ Mode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_EC_MASK;
+ if (Mode) {
+
+ return 1;
+ }
+
+ return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MuxMode specifies whether External Mux is used
+* - FALSE specifies NO external MUX
+* - TRUE specifies External Mux is used
+* @param Channel specifies the channel to be used for the
+* external Mux. Please read the Device Spec for which
+* channels are valid for which mode.
+*
+* @return None.
+*
+* @note There is no Assert in this function for checking the channel
+* number if the external Mux is used. The user should provide a
+* valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_MUX_MASK);
+ /*
+ * Select the Mux mode and the channel to be used.
+ */
+ if (MuxMode == TRUE) {
+ RegValue |= XADCPS_CFR0_MUX_MASK;
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+ }
+
+ /*
+ * Write the mux mode into the Configuration Register 0.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+ /*
+ * Read the Configuration Register 2.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Select the Power Down mode.
+ */
+ RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Power Down Mode.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Return the Power Down mode.
+ */
+ return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be written.
+* @param Data is the data to be written.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+ u32 RegData;
+
+ /*
+ * Write the Data into the FIFO Register.
+ */
+ RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Read the Read FIFO after any write since for each write
+ * one location of Read FIFO gets updated
+ */
+ XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be read.
+*
+* @return Data read from the FIFO
+*
+* @note None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+ u32 RegData;
+
+ RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+ /* Read cmd to FIFO*/
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do a Dummy read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ /* Do a Dummy write to get the actual read */
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do the Actual read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ return RegData;
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..549bfff298f5c67a35b28b5231b1636dafd4396c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* XADC Channel Sequencer Modes
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - Default : This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - One pass through sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - Continuous cycling of sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - Single channel mode: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - Simultaneous Sampling Mode: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - Independent ADC mode: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* Building the driver
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* Limitations of the driver
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..22757f39bfd2609cbf57b6802dc4811a55600b81
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_XADC_0_DEVICE_ID,
+ XPAR_PS7_XADC_0_BASEADDR
+ }
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..55a47a440a6a9933952aa7d70ad73b5e198c689b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the I.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Enable Register.
+ */
+ return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the IPISR.
+*
+* @note The device must be configured at hardware build time to include
+* interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Clear the specified interrupts in the Interrupt Status register.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET);
+ RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+ RegValue);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f171b416b5b576416d5d71f25ed4952fffcd0cf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
@@ -0,0 +1,141 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+* - Resets the device,
+* - Writes a value into the Alarm Threshold register and reads it back
+* for comparison.
+* - Resets the device again.
+*
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - XST_SUCCESS if the value read from the Alarm Threshold
+* register is the same as the value written.
+* - XST_FAILURE Otherwise
+*
+* @note This is a destructive test in that resets of the device are
+* performed. Refer to the device specification for the
+* device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+ int Status;
+ u32 RegValue;
+
+ /*
+ * Assert the argument
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * Reset the device to get it back to its default state
+ */
+ XAdcPs_Reset(InstancePtr);
+
+ /*
+ * Write a value into the Alarm Threshold registers, read it back, and
+ * do the comparison
+ */
+ XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+ XADCPS_ATR_TEST_VALUE);
+ RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+ if (RegValue == XADCPS_ATR_TEST_VALUE) {
+ Status = XST_SUCCESS;
+ } else {
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Reset the device again to its default state.
+ */
+ XAdcPs_Reset(InstancePtr);
+ /*
+ * Return the test result.
+ */
+ return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..5fb7cdeadfa46d0e590913dd89d81925ade784cf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
+*
+*