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開始行:
CENTER:SIZE(50){COLOR(green){VDEC & other Tools}}
***CADENCE Design Tutorials [#h5437ce7]
-[[Local VLSI CAD Design Tutorials >http://aslweb.u-aizu....
- [[RTL Compiler & First Encounter Tutorial >http://cecs....
- [[Digital VLSI Chip Design with Cadence and Synopsys CA...
***VDEC - VLSI Design and Education Center ([[Jump to VDE...
-Go to [[''this site''>http://www.vdec.u-tokyo.ac.jp/PROT...
***VDEC Supported OS (Downloaded from VDEC site on Oct. 1...
|&ref(encounter.gif,,80%);|&ref(f2.gif,,80%);|
-Cadence_Platform_Support_Plan ([[PDF>http://webfs-int.u-...
-Cadence_Support ([[PDF>http://webfs-int.u-aizu.ac.jp/~be...
-IC61move (IC613?ܹԤ???????) ([[PDF>http://webfs-int.u-aiz...
-[[Layout Tutorial>http://www.eda.ncsu.edu/wiki/Tutorial:...
--[[Other CAD tutorials>http://www.eda.ncsu.edu/wiki/Tuto...
----
-VDEC VLSI Design tools Literature
--??, ????, [[LSI??ȯ???߷??顢?ڤӡ??????ƥൻ?Ѹ???>http://www....
//-- [[Designing with VDEC VLSI Tools>http://aslweb.u-aiz...
//--[[VLS Course>http://sharif.ir/~hessabi/VLSI/]]
Basic Design Tools:
--Coding - Tool: Verilog HDL
-- Logic Synthesis - Tool:[[Design Compiler>http://www.tk...
-- Timing Siumlation - Tool: Verilog-XL, [[NC-Verilog>htt...
-- Place and Route - Tool: [[SoC Encounter>http://www.ee....
---Reference: [[placement and routing>http://sharif.ir/~h...
-[[HSPICE>http://www.synopsys.com/Tools/Verification/AMSV...
--[[Synopsys Power Compiler>http://www.synopsys.com/tools...
---Power Compiler™ automatically minimizes power co...
-RTqualify from [[HDLab>http://www.hdlab.co.jp/web/x030en...
WWW VLSI Educational services:
-Japan: [[VDEC>http://www.vdec.u-tokyo.ac.jp/welcome.html]]
-U.S.: [[MOSIS>http://www.mosis.com/]]
--[[Cadence Tutorials from the University of Virginia>htt...
-EC: [[EuroPractice>http://www.europractice-ic.com/]]
-Taiwan: [[CIC>http://www.cic.edu.tw/cic_v13/english/]]
*Matrix computation on CPUs and GPUs libraries [#s62ede65]
-[[Intel Math Kernel Library>http://software.intel.com/en...
-[[CUDA CUBLAS Library2.0>http://developer.download.nvidi...
---
**Simulators [#nff4d163]
-[[M5 multicore simulator>http://www.m5sim.org/Main_Page]]
-- N.L. Binkert et al., ??[[The M5 Simulator: Modeling Ne...
-- [[The GEM5 simulator>http://research.cs.wisc.edu/multi...
----
-[[GPGPU-Sim>http://www.ece.ubc.ca/~aamodt/gpgpu-sim/]]
-Off-Chip/On-Chip Network Simulator [[ns-2>http://www.isi...
- Random Task Graph Generator [[TGFF>http://ziyang.eecs.u...
-Super-scalar Microprocessor Simulator [[SimpleScalar>ht...
-[[HotSpot>http://lava.cs.virginia.edu/HotSpot/]]
-[[TOP500 Supercomputer Sites webpage>http://www.top500.o...
***Cell BE [#wcbaab17]
-Cellsim: [[Cell Simulator>http://swarm.cs.virginia.edu/c...
--[[UNISIM>http://unisim.org/site/]]
--[[Barcelona Supercomputer Center>http://www.bsc.es/plan...
--[[Synergistic Processor Unit - Instruction Set Architec...
-IBM Blade Server: [[Cell Broadband Engine resource cente...
-[[IBM cellsystemsim>http://www.alphaworks.ibm.com/tech/c...
(only executable)
***Libraries [#l1431589]
-QSpace - Queen's University Library
--[[Design and Evaluation of Efficient Collective Communi...
--[[A Configurable Router for Embedded Network-on-Chip Su...
*** CPU Design [#b0c99357]
-Floorplan:
-- [[Analyzing and Optimizing the Design Floorplan in Qua...
--[[Design Analysis & Engineering Change Management with ...
***Major FPGA Vendors [#wda2e15f]
-[[Xilinx>http://www.xilinx.com]]
-[[Altera>http://www.altera.com]]
-Mentor Graphics
-Synplicity
-Cadence
These vendors not only provide FPGA
boards but Electronic Design Automation tools so that des...
make best use of these FPGAs. These tools can be used for...
placement, routing , synthesis and verification. These ve...
provide libraries of reference designs and Intellectual P...
**Verilog [#b089478b]
-[[Verilog source>http://www.eehomepage.com/query.php?Fin...
**STANDARS [#dfa18701]
-Unified Power Format
--http://www.accellera.org
-- IEEE 1801-2009 – Unified Power Format (UPF)
**List of system-on-a-chip suppliers [#e487f4e0]
-[[SoC List>http://en.wikipedia.org/wiki/List_of_system-o...
- Matrix Transpose http://www.programmingsimplified.com/c...
*Fabrication Process [#qf8ddc16]
-VLSI Design Lectures http://www.coe.montana.edu/ee/andyo...
*Air Pollution Monitor [#va6b24d5]
*Links [#p651a726]
- http://www.computerhope.com/issues/ch001002.htm
http://aqicn.org/map/
終了行:
CENTER:SIZE(50){COLOR(green){VDEC & other Tools}}
***CADENCE Design Tutorials [#h5437ce7]
-[[Local VLSI CAD Design Tutorials >http://aslweb.u-aizu....
- [[RTL Compiler & First Encounter Tutorial >http://cecs....
- [[Digital VLSI Chip Design with Cadence and Synopsys CA...
***VDEC - VLSI Design and Education Center ([[Jump to VDE...
-Go to [[''this site''>http://www.vdec.u-tokyo.ac.jp/PROT...
***VDEC Supported OS (Downloaded from VDEC site on Oct. 1...
|&ref(encounter.gif,,80%);|&ref(f2.gif,,80%);|
-Cadence_Platform_Support_Plan ([[PDF>http://webfs-int.u-...
-Cadence_Support ([[PDF>http://webfs-int.u-aizu.ac.jp/~be...
-IC61move (IC613?ܹԤ???????) ([[PDF>http://webfs-int.u-aiz...
-[[Layout Tutorial>http://www.eda.ncsu.edu/wiki/Tutorial:...
--[[Other CAD tutorials>http://www.eda.ncsu.edu/wiki/Tuto...
----
-VDEC VLSI Design tools Literature
--??, ????, [[LSI??ȯ???߷??顢?ڤӡ??????ƥൻ?Ѹ???>http://www....
//-- [[Designing with VDEC VLSI Tools>http://aslweb.u-aiz...
//--[[VLS Course>http://sharif.ir/~hessabi/VLSI/]]
Basic Design Tools:
--Coding - Tool: Verilog HDL
-- Logic Synthesis - Tool:[[Design Compiler>http://www.tk...
-- Timing Siumlation - Tool: Verilog-XL, [[NC-Verilog>htt...
-- Place and Route - Tool: [[SoC Encounter>http://www.ee....
---Reference: [[placement and routing>http://sharif.ir/~h...
-[[HSPICE>http://www.synopsys.com/Tools/Verification/AMSV...
--[[Synopsys Power Compiler>http://www.synopsys.com/tools...
---Power Compiler™ automatically minimizes power co...
-RTqualify from [[HDLab>http://www.hdlab.co.jp/web/x030en...
WWW VLSI Educational services:
-Japan: [[VDEC>http://www.vdec.u-tokyo.ac.jp/welcome.html]]
-U.S.: [[MOSIS>http://www.mosis.com/]]
--[[Cadence Tutorials from the University of Virginia>htt...
-EC: [[EuroPractice>http://www.europractice-ic.com/]]
-Taiwan: [[CIC>http://www.cic.edu.tw/cic_v13/english/]]
*Matrix computation on CPUs and GPUs libraries [#s62ede65]
-[[Intel Math Kernel Library>http://software.intel.com/en...
-[[CUDA CUBLAS Library2.0>http://developer.download.nvidi...
---
**Simulators [#nff4d163]
-[[M5 multicore simulator>http://www.m5sim.org/Main_Page]]
-- N.L. Binkert et al., ??[[The M5 Simulator: Modeling Ne...
-- [[The GEM5 simulator>http://research.cs.wisc.edu/multi...
----
-[[GPGPU-Sim>http://www.ece.ubc.ca/~aamodt/gpgpu-sim/]]
-Off-Chip/On-Chip Network Simulator [[ns-2>http://www.isi...
- Random Task Graph Generator [[TGFF>http://ziyang.eecs.u...
-Super-scalar Microprocessor Simulator [[SimpleScalar>ht...
-[[HotSpot>http://lava.cs.virginia.edu/HotSpot/]]
-[[TOP500 Supercomputer Sites webpage>http://www.top500.o...
***Cell BE [#wcbaab17]
-Cellsim: [[Cell Simulator>http://swarm.cs.virginia.edu/c...
--[[UNISIM>http://unisim.org/site/]]
--[[Barcelona Supercomputer Center>http://www.bsc.es/plan...
--[[Synergistic Processor Unit - Instruction Set Architec...
-IBM Blade Server: [[Cell Broadband Engine resource cente...
-[[IBM cellsystemsim>http://www.alphaworks.ibm.com/tech/c...
(only executable)
***Libraries [#l1431589]
-QSpace - Queen's University Library
--[[Design and Evaluation of Efficient Collective Communi...
--[[A Configurable Router for Embedded Network-on-Chip Su...
*** CPU Design [#b0c99357]
-Floorplan:
-- [[Analyzing and Optimizing the Design Floorplan in Qua...
--[[Design Analysis & Engineering Change Management with ...
***Major FPGA Vendors [#wda2e15f]
-[[Xilinx>http://www.xilinx.com]]
-[[Altera>http://www.altera.com]]
-Mentor Graphics
-Synplicity
-Cadence
These vendors not only provide FPGA
boards but Electronic Design Automation tools so that des...
make best use of these FPGAs. These tools can be used for...
placement, routing , synthesis and verification. These ve...
provide libraries of reference designs and Intellectual P...
**Verilog [#b089478b]
-[[Verilog source>http://www.eehomepage.com/query.php?Fin...
**STANDARS [#dfa18701]
-Unified Power Format
--http://www.accellera.org
-- IEEE 1801-2009 – Unified Power Format (UPF)
**List of system-on-a-chip suppliers [#e487f4e0]
-[[SoC List>http://en.wikipedia.org/wiki/List_of_system-o...
- Matrix Transpose http://www.programmingsimplified.com/c...
*Fabrication Process [#qf8ddc16]
-VLSI Design Lectures http://www.coe.montana.edu/ee/andyo...
*Air Pollution Monitor [#va6b24d5]
*Links [#p651a726]
- http://www.computerhope.com/issues/ch001002.htm
http://aqicn.org/map/
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