OASIS-VP-Topic-3
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開始行:
CENTER:SIZE(40){COLOR(blue){ Implementation and Evaluatio...
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[[OASIS-VP]]
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*Overview [#of0ac920]
This topic is implementation and evaluation of OpenRISC c...
The OpenRISC project has several features:
- Support 32 and 64 bits instruction set; vector, floatin...
- Support cache coherence, virtual memory support.
- Available in HDL: Verilog and VHDL.
- ASIC and FPGA implementation proof.
- Supported software: 32-bit GNU toolchain, simulators, O...
CENTER:&ref(OR1200_CPU.png,,50%);
CENTER:Figure 1: OpenRISC OR1200 architecture.
*Research Description [#sa9adf8b]
As a part of OASIS-VP, this topic investigates the implem...
// Note: This topic can be extended as an implementation ...
*Expected Output [#lfbc15c0]
- Investigate the operation and architecture of OpenRISC.
- Implement the OpenRISC core into an FPGA board.
- Evaluate the performance of OpenRISC core.
*References [#ba027dbf]
- Main references: Japanese spec: https://github.com/open...
- Other Documents: [[Link>https://drive.google.com/file/d...
-- [1] OpenRISC website: http://opencores.org/or1k/Main_P...
-- [2] Tutorials provided by community: http://openrisc.i...
-- [3] Source code, tutorial download: https://github.com...
-- [4] Japanese spec: https://github.com/openrisc/or1200/...
-- [5] Web-based emulator: https://s-macke.github.io/jor1...
終了行:
CENTER:SIZE(40){COLOR(blue){ Implementation and Evaluatio...
----
[[OASIS-VP]]
----
*Overview [#of0ac920]
This topic is implementation and evaluation of OpenRISC c...
The OpenRISC project has several features:
- Support 32 and 64 bits instruction set; vector, floatin...
- Support cache coherence, virtual memory support.
- Available in HDL: Verilog and VHDL.
- ASIC and FPGA implementation proof.
- Supported software: 32-bit GNU toolchain, simulators, O...
CENTER:&ref(OR1200_CPU.png,,50%);
CENTER:Figure 1: OpenRISC OR1200 architecture.
*Research Description [#sa9adf8b]
As a part of OASIS-VP, this topic investigates the implem...
// Note: This topic can be extended as an implementation ...
*Expected Output [#lfbc15c0]
- Investigate the operation and architecture of OpenRISC.
- Implement the OpenRISC core into an FPGA board.
- Evaluate the performance of OpenRISC core.
*References [#ba027dbf]
- Main references: Japanese spec: https://github.com/open...
- Other Documents: [[Link>https://drive.google.com/file/d...
-- [1] OpenRISC website: http://opencores.org/or1k/Main_P...
-- [2] Tutorials provided by community: http://openrisc.i...
-- [3] Source code, tutorial download: https://github.com...
-- [4] Japanese spec: https://github.com/openrisc/or1200/...
-- [5] Web-based emulator: https://s-macke.github.io/jor1...
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