OASIS-VP-Topic 3-2
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開始行:
[[OASIS-VP-Topic-1]]
[[Available Research Topics]]
Design of RISC-V Processor System on Altera FPGA.
(Tentative title)
*Research Overview [#p93d4a3e]
In this research, you part a RISC core processor and peri...
*Research Description [#ob708645]
+ Learn from current design: Run an implementation for Xi...
+ Analyze inside of LowRISC: Investigate source code for ...
+ Learn Qsys tools for altera SoC design: Investigate how...
+ Implementation
*Expected outputs [#j8cb2a39]
You will write four documents
+ How to run RISC-V on Xilinx FPGA
+ Overview of RISC-V processor
+ How to implement RISC-V on Altera FPGA
+ Benchmark result
*Reference [#e4ce9a01]
+ [[RISC-V Web Page>http://www.riscv.org]]
終了行:
[[OASIS-VP-Topic-1]]
[[Available Research Topics]]
Design of RISC-V Processor System on Altera FPGA.
(Tentative title)
*Research Overview [#p93d4a3e]
In this research, you part a RISC core processor and peri...
*Research Description [#ob708645]
+ Learn from current design: Run an implementation for Xi...
+ Analyze inside of LowRISC: Investigate source code for ...
+ Learn Qsys tools for altera SoC design: Investigate how...
+ Implementation
*Expected outputs [#j8cb2a39]
You will write four documents
+ How to run RISC-V on Xilinx FPGA
+ Overview of RISC-V processor
+ How to implement RISC-V on Altera FPGA
+ Benchmark result
*Reference [#e4ce9a01]
+ [[RISC-V Web Page>http://www.riscv.org]]
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