OASIS-Project
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開始行:
[[OASIS]]
CENTER:SIZE(30){Design and Evaluation of Efficient Error ...
//CENTER:&ref(pipeline.jpg,,18%);
CENTER:COLOR(green){Router to Router Detection and Correc...
CENTER:&ref(3Dpack.jpeg,,70%);
CENTER:COLOR(green){3D-OASIS-NoC flit format}
//Contents:
//#CONTENTS
**Background [#nec7d6fe]
During the past decade, 3D-Network-on-Chips (3D-NoCs) hav...
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been des...
In addition, to perform the evaluation logic modules were...
**Research goal[#mec7d6fe]
-1. Study OASIS 3D-FTO Router Architecture
-2. Implement the detection mechanism to be able to detec...
-- Source to destination: Flits are checked once arrived ...
-- Router to router: Flits are checked at every router (i...
-3. Design the Physical router using Design Compiler (for...
-4. Verify the correctness at each step using ModelSim
-5. Evaluate the performance of the final 3D Router:
-- Hardware complexity (Area, Power, and Speed)
-- Performance (Latency, throughput)
-6. Make the comparison between:
-- Source to destination
-- Router to router
-7. Write a thesis
*Design Steps and Research plan[#lec7d6fe]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,100%);
CENTER:COLOR(green){3D-OASIS-NoC Router Design Steps}
1- Understand the router architecture of 3D-FTO
2- Modify the flit format
3- Decide the code detection and correction algorithm
4- Implement "Source to destination" approach by modifyin...
5- Implement "Router to router" approach by modifying the...
6- Evaluation following the design steps illustrated in t...
7- Write thesis
//** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References Set I [#x0fe7b0f]
-[[CRC_study_in_Hardware_In_Japanese.pdf(????Ĺ???? CRC32 ...
-[[A CRC Verilog description module for a hard real time ...
-[[Altera_CRC Compiler User Guide.pdf>http://web-ext.u-ai...
-[[Analysis of Error Recovery Schemes for NoCS.pdf>http:/...
-[[Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf>ht...
-[[Design and Verification of An Automatic CRC Engine Usi...
-[[OKADA Network Interface>http://aslweb.u-aizu.ac.jp/asl...
**References Set II [#ec63a302]
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- On the Design of a 3D Network-on-Chip for Many-core SoC...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- OASIS Network-on-Chip Prototyping on FPGA, Master's The...
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- On the Design of a 3D Network-on-Chip for Many-core SoC...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- OASIS Network-on-Chip Prototyping on FPGA, Master's The...
-[[Altera_CRC Compiler User Guide.pdf>http://web-ext.u-ai...
-[[Analysis of Error Recovery Schemes for NoCS.pdf>http:/...
-[[Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf>ht...
-[[Design and Verification of An Automatic CRC Engine Usi...
** Benchmark suite [#c4629d5d]
-[[PDF>http://web-ext.u-aizu.ac.jp/~benab/research/benchm...
-[[ppt>http://web-ext.u-aizu.ac.jp/~benab/research/benchm...
終了行:
[[OASIS]]
CENTER:SIZE(30){Design and Evaluation of Efficient Error ...
//CENTER:&ref(pipeline.jpg,,18%);
CENTER:COLOR(green){Router to Router Detection and Correc...
CENTER:&ref(3Dpack.jpeg,,70%);
CENTER:COLOR(green){3D-OASIS-NoC flit format}
//Contents:
//#CONTENTS
**Background [#nec7d6fe]
During the past decade, 3D-Network-on-Chips (3D-NoCs) hav...
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been des...
In addition, to perform the evaluation logic modules were...
**Research goal[#mec7d6fe]
-1. Study OASIS 3D-FTO Router Architecture
-2. Implement the detection mechanism to be able to detec...
-- Source to destination: Flits are checked once arrived ...
-- Router to router: Flits are checked at every router (i...
-3. Design the Physical router using Design Compiler (for...
-4. Verify the correctness at each step using ModelSim
-5. Evaluate the performance of the final 3D Router:
-- Hardware complexity (Area, Power, and Speed)
-- Performance (Latency, throughput)
-6. Make the comparison between:
-- Source to destination
-- Router to router
-7. Write a thesis
*Design Steps and Research plan[#lec7d6fe]
CENTER:&ref(OASIS-Router-Design-Steps.jpg,,100%);
CENTER:COLOR(green){3D-OASIS-NoC Router Design Steps}
1- Understand the router architecture of 3D-FTO
2- Modify the flit format
3- Decide the code detection and correction algorithm
4- Implement "Source to destination" approach by modifyin...
5- Implement "Router to router" approach by modifying the...
6- Evaluation following the design steps illustrated in t...
7- Write thesis
//** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References Set I [#x0fe7b0f]
-[[CRC_study_in_Hardware_In_Japanese.pdf(????Ĺ???? CRC32 ...
-[[A CRC Verilog description module for a hard real time ...
-[[Altera_CRC Compiler User Guide.pdf>http://web-ext.u-ai...
-[[Analysis of Error Recovery Schemes for NoCS.pdf>http:/...
-[[Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf>ht...
-[[Design and Verification of An Automatic CRC Engine Usi...
-[[OKADA Network Interface>http://aslweb.u-aizu.ac.jp/asl...
**References Set II [#ec63a302]
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- On the Design of a 3D Network-on-Chip for Many-core SoC...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- OASIS Network-on-Chip Prototyping on FPGA, Master's The...
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- On the Design of a 3D Network-on-Chip for Many-core SoC...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- OASIS Network-on-Chip Prototyping on FPGA, Master's The...
-[[Altera_CRC Compiler User Guide.pdf>http://web-ext.u-ai...
-[[Analysis of Error Recovery Schemes for NoCS.pdf>http:/...
-[[Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf>ht...
-[[Design and Verification of An Automatic CRC Engine Usi...
** Benchmark suite [#c4629d5d]
-[[PDF>http://web-ext.u-aizu.ac.jp/~benab/research/benchm...
-[[ppt>http://web-ext.u-aizu.ac.jp/~benab/research/benchm...
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